1 files changed, 16 insertions, 5 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index dd4a5b685a00..721ef3208eb5 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         if (c->x86 > 0x11)
                 set_cpu_cap(c, X86_FEATURE_ARAT);
 
-        /*
-         * Disable GART TLB Walk Errors on Fam10h. We do this here
-         * because this is always needed when GART is enabled, even in a
-         * kernel which has no MCE support built in.
-         */
         if (c->x86 == 0x10) {
                 /*
+                 * Disable GART TLB Walk Errors on Fam10h. We do this here
+                 * because this is always needed when GART is enabled, even in a
+                 * kernel which has no MCE support built in.
                  * BIOS should disable GartTlbWlk Errors themself. If
                  * it doesn't do it here as suggested by the BKDG.
                  *
@@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                         mask |= (1 << 10);
                         wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
                 }
+
+                /*
+                 * On family 10h BIOS may not have properly enabled WC+ support,
+                 * causing it to be converted to CD memtype. This may result in
+                 * performance degradation for certain nested-paging guests.
+                 * Prevent this conversion by clearing bit 24 in
+                 * MSR_AMD64_BU_CFG2.
+                 */
+                if (c->x86 == 0x10) {
+                        rdmsrl(MSR_AMD64_BU_CFG2, value);
+                        value &= ~(1ULL << 24);
+                        wrmsrl(MSR_AMD64_BU_CFG2, value);
+                }
         }
 
         rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);