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-rw-r--r--arch/sparc/Kconfig8
-rw-r--r--arch/sparc/include/asm/spitfire.h1
-rw-r--r--arch/sparc/kernel/cpu.c6
-rw-r--r--arch/sparc/kernel/head_64.S25
-rw-r--r--arch/sparc/kernel/leon_pci_grpci2.c41
5 files changed, 57 insertions, 24 deletions
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 289127d5241c..3d361f236308 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -84,12 +84,6 @@ config ARCH_DEFCONFIG
84 default "arch/sparc/configs/sparc32_defconfig" if SPARC32 84 default "arch/sparc/configs/sparc32_defconfig" if SPARC32
85 default "arch/sparc/configs/sparc64_defconfig" if SPARC64 85 default "arch/sparc/configs/sparc64_defconfig" if SPARC64
86 86
87# CONFIG_BITS can be used at source level to get 32/64 bits
88config BITS
89 int
90 default 32 if SPARC32
91 default 64 if SPARC64
92
93config IOMMU_HELPER 87config IOMMU_HELPER
94 bool 88 bool
95 default y if SPARC64 89 default y if SPARC64
@@ -197,7 +191,7 @@ config RWSEM_XCHGADD_ALGORITHM
197 191
198config GENERIC_HWEIGHT 192config GENERIC_HWEIGHT
199 bool 193 bool
200 default y if !ULTRA_HAS_POPULATION_COUNT 194 default y
201 195
202config GENERIC_CALIBRATE_DELAY 196config GENERIC_CALIBRATE_DELAY
203 bool 197 bool
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index d06a26601753..6b67e50fb9b4 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -45,6 +45,7 @@
45#define SUN4V_CHIP_NIAGARA3 0x03 45#define SUN4V_CHIP_NIAGARA3 0x03
46#define SUN4V_CHIP_NIAGARA4 0x04 46#define SUN4V_CHIP_NIAGARA4 0x04
47#define SUN4V_CHIP_NIAGARA5 0x05 47#define SUN4V_CHIP_NIAGARA5 0x05
48#define SUN4V_CHIP_SPARC64X 0x8a
48#define SUN4V_CHIP_UNKNOWN 0xff 49#define SUN4V_CHIP_UNKNOWN 0xff
49 50
50#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index a6c94a2bf9d4..5c5125895db8 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -493,6 +493,12 @@ static void __init sun4v_cpu_probe(void)
493 sparc_pmu_type = "niagara5"; 493 sparc_pmu_type = "niagara5";
494 break; 494 break;
495 495
496 case SUN4V_CHIP_SPARC64X:
497 sparc_cpu_type = "SPARC64-X";
498 sparc_fpu_type = "SPARC64-X integrated FPU";
499 sparc_pmu_type = "sparc64-x";
500 break;
501
496 default: 502 default:
497 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", 503 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
498 prom_cpu_compatible); 504 prom_cpu_compatible);
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 2feb15c35d9e..26b706a1867d 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -134,6 +134,8 @@ prom_niagara_prefix:
134 .asciz "SUNW,UltraSPARC-T" 134 .asciz "SUNW,UltraSPARC-T"
135prom_sparc_prefix: 135prom_sparc_prefix:
136 .asciz "SPARC-" 136 .asciz "SPARC-"
137prom_sparc64x_prefix:
138 .asciz "SPARC64-X"
137 .align 4 139 .align 4
138prom_root_compatible: 140prom_root_compatible:
139 .skip 64 141 .skip 64
@@ -412,7 +414,7 @@ sun4v_chip_type:
412 cmp %g2, 'T' 414 cmp %g2, 'T'
413 be,pt %xcc, 70f 415 be,pt %xcc, 70f
414 cmp %g2, 'M' 416 cmp %g2, 'M'
415 bne,pn %xcc, 4f 417 bne,pn %xcc, 49f
416 nop 418 nop
417 419
41870: ldub [%g1 + 7], %g2 42070: ldub [%g1 + 7], %g2
@@ -425,7 +427,7 @@ sun4v_chip_type:
425 cmp %g2, '5' 427 cmp %g2, '5'
426 be,pt %xcc, 5f 428 be,pt %xcc, 5f
427 mov SUN4V_CHIP_NIAGARA5, %g4 429 mov SUN4V_CHIP_NIAGARA5, %g4
428 ba,pt %xcc, 4f 430 ba,pt %xcc, 49f
429 nop 431 nop
430 432
43191: sethi %hi(prom_cpu_compatible), %g1 43391: sethi %hi(prom_cpu_compatible), %g1
@@ -439,6 +441,25 @@ sun4v_chip_type:
439 mov SUN4V_CHIP_NIAGARA2, %g4 441 mov SUN4V_CHIP_NIAGARA2, %g4
440 442
4414: 4434:
444 /* Athena */
445 sethi %hi(prom_cpu_compatible), %g1
446 or %g1, %lo(prom_cpu_compatible), %g1
447 sethi %hi(prom_sparc64x_prefix), %g7
448 or %g7, %lo(prom_sparc64x_prefix), %g7
449 mov 9, %g3
45041: ldub [%g7], %g2
451 ldub [%g1], %g4
452 cmp %g2, %g4
453 bne,pn %icc, 49f
454 add %g7, 1, %g7
455 subcc %g3, 1, %g3
456 bne,pt %xcc, 41b
457 add %g1, 1, %g1
458 mov SUN4V_CHIP_SPARC64X, %g4
459 ba,pt %xcc, 5f
460 nop
461
46249:
442 mov SUN4V_CHIP_UNKNOWN, %g4 463 mov SUN4V_CHIP_UNKNOWN, %g4
4435: sethi %hi(sun4v_chip_type), %g2 4645: sethi %hi(sun4v_chip_type), %g2
444 or %g2, %lo(sun4v_chip_type), %g2 465 or %g2, %lo(sun4v_chip_type), %g2
diff --git a/arch/sparc/kernel/leon_pci_grpci2.c b/arch/sparc/kernel/leon_pci_grpci2.c
index fc4320886a3a..4d1487138d26 100644
--- a/arch/sparc/kernel/leon_pci_grpci2.c
+++ b/arch/sparc/kernel/leon_pci_grpci2.c
@@ -186,6 +186,8 @@ struct grpci2_cap_first {
186#define CAP9_IOMAP_OFS 0x20 186#define CAP9_IOMAP_OFS 0x20
187#define CAP9_BARSIZE_OFS 0x24 187#define CAP9_BARSIZE_OFS 0x24
188 188
189#define TGT 256
190
189struct grpci2_priv { 191struct grpci2_priv {
190 struct leon_pci_info info; /* must be on top of this structure */ 192 struct leon_pci_info info; /* must be on top of this structure */
191 struct grpci2_regs *regs; 193 struct grpci2_regs *regs;
@@ -237,8 +239,12 @@ static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
237 if (where & 0x3) 239 if (where & 0x3)
238 return -EINVAL; 240 return -EINVAL;
239 241
240 if (bus == 0 && PCI_SLOT(devfn) != 0) 242 if (bus == 0) {
241 devfn += (0x8 * 6); 243 devfn += (0x8 * 6); /* start at AD16=Device0 */
244 } else if (bus == TGT) {
245 bus = 0;
246 devfn = 0; /* special case: bridge controller itself */
247 }
242 248
243 /* Select bus */ 249 /* Select bus */
244 spin_lock_irqsave(&grpci2_dev_lock, flags); 250 spin_lock_irqsave(&grpci2_dev_lock, flags);
@@ -303,8 +309,12 @@ static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
303 if (where & 0x3) 309 if (where & 0x3)
304 return -EINVAL; 310 return -EINVAL;
305 311
306 if (bus == 0 && PCI_SLOT(devfn) != 0) 312 if (bus == 0) {
307 devfn += (0x8 * 6); 313 devfn += (0x8 * 6); /* start at AD16=Device0 */
314 } else if (bus == TGT) {
315 bus = 0;
316 devfn = 0; /* special case: bridge controller itself */
317 }
308 318
309 /* Select bus */ 319 /* Select bus */
310 spin_lock_irqsave(&grpci2_dev_lock, flags); 320 spin_lock_irqsave(&grpci2_dev_lock, flags);
@@ -368,7 +378,7 @@ static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
368 unsigned int busno = bus->number; 378 unsigned int busno = bus->number;
369 int ret; 379 int ret;
370 380
371 if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) { 381 if (PCI_SLOT(devfn) > 15 || busno > 255) {
372 *val = ~0; 382 *val = ~0;
373 return 0; 383 return 0;
374 } 384 }
@@ -406,7 +416,7 @@ static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
406 struct grpci2_priv *priv = grpci2priv; 416 struct grpci2_priv *priv = grpci2priv;
407 unsigned int busno = bus->number; 417 unsigned int busno = bus->number;
408 418
409 if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) 419 if (PCI_SLOT(devfn) > 15 || busno > 255)
410 return 0; 420 return 0;
411 421
412#ifdef GRPCI2_DEBUG_CFGACCESS 422#ifdef GRPCI2_DEBUG_CFGACCESS
@@ -578,15 +588,15 @@ void grpci2_hw_init(struct grpci2_priv *priv)
578 REGSTORE(regs->ahbmst_map[i], priv->pci_area); 588 REGSTORE(regs->ahbmst_map[i], priv->pci_area);
579 589
580 /* Get the GRPCI2 Host PCI ID */ 590 /* Get the GRPCI2 Host PCI ID */
581 grpci2_cfg_r32(priv, 0, 0, PCI_VENDOR_ID, &priv->pciid); 591 grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
582 592
583 /* Get address to first (always defined) capability structure */ 593 /* Get address to first (always defined) capability structure */
584 grpci2_cfg_r8(priv, 0, 0, PCI_CAPABILITY_LIST, &capptr); 594 grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
585 595
586 /* Enable/Disable Byte twisting */ 596 /* Enable/Disable Byte twisting */
587 grpci2_cfg_r32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, &io_map); 597 grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
588 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0); 598 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
589 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, io_map); 599 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
590 600
591 /* Setup the Host's PCI Target BARs for other peripherals to access, 601 /* Setup the Host's PCI Target BARs for other peripherals to access,
592 * and do DMA to the host's memory. The target BARs can be sized and 602 * and do DMA to the host's memory. The target BARs can be sized and
@@ -617,17 +627,18 @@ void grpci2_hw_init(struct grpci2_priv *priv)
617 pciadr = 0; 627 pciadr = 0;
618 } 628 }
619 } 629 }
620 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BARSIZE_OFS+i*4, bar_sz); 630 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
621 grpci2_cfg_w32(priv, 0, 0, PCI_BASE_ADDRESS_0+i*4, pciadr); 631 bar_sz);
622 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr); 632 grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
633 grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
623 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n", 634 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
624 i, pciadr, ahbadr); 635 i, pciadr, ahbadr);
625 } 636 }
626 637
627 /* set as bus master and enable pci memory responses */ 638 /* set as bus master and enable pci memory responses */
628 grpci2_cfg_r32(priv, 0, 0, PCI_COMMAND, &data); 639 grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
629 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 640 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
630 grpci2_cfg_w32(priv, 0, 0, PCI_COMMAND, data); 641 grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
631 642
632 /* Enable Error respone (CPU-TRAP) on illegal memory access. */ 643 /* Enable Error respone (CPU-TRAP) on illegal memory access. */
633 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE); 644 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);