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-rw-r--r--arch/sparc64/kernel/pci.c375
-rw-r--r--arch/sparc64/kernel/pci_common.c707
-rw-r--r--arch/sparc64/kernel/pci_impl.h15
-rw-r--r--arch/sparc64/kernel/pci_iommu.c47
-rw-r--r--arch/sparc64/kernel/pci_psycho.c26
-rw-r--r--arch/sparc64/kernel/pci_sabre.c53
-rw-r--r--arch/sparc64/kernel/pci_schizo.c26
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c199
8 files changed, 409 insertions, 1039 deletions
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 12109886bb1e..246b8009a2b4 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -1,9 +1,11 @@
1/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $ 1/* pci.c: UltraSparc PCI controller support.
2 * pci.c: UltraSparc PCI controller support.
3 * 2 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
7 */ 9 */
8 10
9#include <linux/module.h> 11#include <linux/module.h>
@@ -300,6 +302,329 @@ static void __init pci_controller_probe(void)
300 pci_controller_scan(pci_controller_init); 302 pci_controller_scan(pci_controller_init);
301} 303}
302 304
305static unsigned long pci_parse_of_flags(u32 addr0)
306{
307 unsigned long flags = 0;
308
309 if (addr0 & 0x02000000) {
310 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
311 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
312 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
313 if (addr0 & 0x40000000)
314 flags |= IORESOURCE_PREFETCH
315 | PCI_BASE_ADDRESS_MEM_PREFETCH;
316 } else if (addr0 & 0x01000000)
317 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
318 return flags;
319}
320
321/* The of_device layer has translated all of the assigned-address properties
322 * into physical address resources, we only have to figure out the register
323 * mapping.
324 */
325static void pci_parse_of_addrs(struct of_device *op,
326 struct device_node *node,
327 struct pci_dev *dev)
328{
329 struct resource *op_res;
330 const u32 *addrs;
331 int proplen;
332
333 addrs = of_get_property(node, "assigned-addresses", &proplen);
334 if (!addrs)
335 return;
336 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
337 op_res = &op->resource[0];
338 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
339 struct resource *res;
340 unsigned long flags;
341 int i;
342
343 flags = pci_parse_of_flags(addrs[0]);
344 if (!flags)
345 continue;
346 i = addrs[0] & 0xff;
347 printk(" start: %lx, end: %lx, i: %x\n",
348 op_res->start, op_res->end, i);
349
350 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
351 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
352 } else if (i == dev->rom_base_reg) {
353 res = &dev->resource[PCI_ROM_RESOURCE];
354 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
355 } else {
356 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
357 continue;
358 }
359 res->start = op_res->start;
360 res->end = op_res->end;
361 res->flags = flags;
362 res->name = pci_name(dev);
363 }
364}
365
366struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
367 struct device_node *node,
368 struct pci_bus *bus, int devfn)
369{
370 struct dev_archdata *sd;
371 struct pci_dev *dev;
372 const char *type;
373
374 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
375 if (!dev)
376 return NULL;
377
378 sd = &dev->dev.archdata;
379 sd->iommu = pbm->iommu;
380 sd->stc = &pbm->stc;
381 sd->host_controller = pbm;
382 sd->prom_node = node;
383 sd->op = of_find_device_by_node(node);
384 sd->msi_num = 0xffffffff;
385
386 type = of_get_property(node, "device_type", NULL);
387 if (type == NULL)
388 type = "";
389
390 printk(" create device, devfn: %x, type: %s\n", devfn, type);
391
392 dev->bus = bus;
393 dev->sysdata = node;
394 dev->dev.parent = bus->bridge;
395 dev->dev.bus = &pci_bus_type;
396 dev->devfn = devfn;
397 dev->multifunction = 0; /* maybe a lie? */
398
399 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
400 dev->device = of_getintprop_default(node, "device-id", 0xffff);
401 dev->subsystem_vendor =
402 of_getintprop_default(node, "subsystem-vendor-id", 0);
403 dev->subsystem_device =
404 of_getintprop_default(node, "subsystem-id", 0);
405
406 dev->cfg_size = pci_cfg_space_size(dev);
407
408 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
409 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
410 dev->class = of_getintprop_default(node, "class-code", 0);
411
412 printk(" class: 0x%x\n", dev->class);
413
414 dev->current_state = 4; /* unknown power state */
415 dev->error_state = pci_channel_io_normal;
416
417 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
418 /* a PCI-PCI bridge */
419 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
420 dev->rom_base_reg = PCI_ROM_ADDRESS1;
421 } else if (!strcmp(type, "cardbus")) {
422 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
423 } else {
424 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
425 dev->rom_base_reg = PCI_ROM_ADDRESS;
426
427 dev->irq = sd->op->irqs[0];
428 if (dev->irq == 0xffffffff)
429 dev->irq = PCI_IRQ_NONE;
430 }
431
432 pci_parse_of_addrs(sd->op, node, dev);
433
434 printk(" adding to system ...\n");
435
436 pci_device_add(dev, bus);
437
438 return dev;
439}
440
441static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
442 struct device_node *node,
443 struct pci_bus *bus);
444
445#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
446
447void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
448 struct device_node *node,
449 struct pci_dev *dev)
450{
451 struct pci_bus *bus;
452 const u32 *busrange, *ranges;
453 int len, i;
454 struct resource *res;
455 unsigned int flags;
456 u64 size;
457
458 printk("of_scan_pci_bridge(%s)\n", node->full_name);
459
460 /* parse bus-range property */
461 busrange = of_get_property(node, "bus-range", &len);
462 if (busrange == NULL || len != 8) {
463 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
464 node->full_name);
465 return;
466 }
467 ranges = of_get_property(node, "ranges", &len);
468 if (ranges == NULL) {
469 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
470 node->full_name);
471 return;
472 }
473
474 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
475 if (!bus) {
476 printk(KERN_ERR "Failed to create pci bus for %s\n",
477 node->full_name);
478 return;
479 }
480
481 bus->primary = dev->bus->number;
482 bus->subordinate = busrange[1];
483 bus->bridge_ctl = 0;
484
485 /* parse ranges property */
486 /* PCI #address-cells == 3 and #size-cells == 2 always */
487 res = &dev->resource[PCI_BRIDGE_RESOURCES];
488 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
489 res->flags = 0;
490 bus->resource[i] = res;
491 ++res;
492 }
493 i = 1;
494 for (; len >= 32; len -= 32, ranges += 8) {
495 struct resource *root;
496
497 flags = pci_parse_of_flags(ranges[0]);
498 size = GET_64BIT(ranges, 6);
499 if (flags == 0 || size == 0)
500 continue;
501 if (flags & IORESOURCE_IO) {
502 res = bus->resource[0];
503 if (res->flags) {
504 printk(KERN_ERR "PCI: ignoring extra I/O range"
505 " for bridge %s\n", node->full_name);
506 continue;
507 }
508 root = &pbm->io_space;
509 } else {
510 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
511 printk(KERN_ERR "PCI: too many memory ranges"
512 " for bridge %s\n", node->full_name);
513 continue;
514 }
515 res = bus->resource[i];
516 ++i;
517 root = &pbm->mem_space;
518 }
519
520 res->start = GET_64BIT(ranges, 1);
521 res->end = res->start + size - 1;
522 res->flags = flags;
523
524 /* Another way to implement this would be to add an of_device
525 * layer routine that can calculate a resource for a given
526 * range property value in a PCI device.
527 */
528 pbm->parent->resource_adjust(dev, res, root);
529 }
530 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
531 bus->number);
532 printk(" bus name: %s\n", bus->name);
533
534 pci_of_scan_bus(pbm, node, bus);
535}
536
537static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
538 struct device_node *node,
539 struct pci_bus *bus)
540{
541 struct device_node *child;
542 const u32 *reg;
543 int reglen, devfn;
544 struct pci_dev *dev;
545
546 printk("PCI: scan_bus[%s] bus no %d\n",
547 node->full_name, bus->number);
548
549 child = NULL;
550 while ((child = of_get_next_child(node, child)) != NULL) {
551 printk(" * %s\n", child->full_name);
552 reg = of_get_property(child, "reg", &reglen);
553 if (reg == NULL || reglen < 20)
554 continue;
555 devfn = (reg[0] >> 8) & 0xff;
556
557 /* create a new pci_dev for this device */
558 dev = of_create_pci_dev(pbm, child, bus, devfn);
559 if (!dev)
560 continue;
561 printk("PCI: dev header type: %x\n", dev->hdr_type);
562
563 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
564 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
565 of_scan_pci_bridge(pbm, child, dev);
566 }
567}
568
569static ssize_t
570show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
571{
572 struct pci_dev *pdev;
573 struct device_node *dp;
574
575 pdev = to_pci_dev(dev);
576 dp = pdev->dev.archdata.prom_node;
577
578 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
579}
580
581static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
582
583static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
584{
585 struct pci_dev *dev;
586 int err;
587
588 list_for_each_entry(dev, &bus->devices, bus_list) {
589 /* we don't really care if we can create this file or
590 * not, but we need to assign the result of the call
591 * or the world will fall under alien invasion and
592 * everybody will be frozen on a spaceship ready to be
593 * eaten on alpha centauri by some green and jelly
594 * humanoid.
595 */
596 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
597 }
598}
599
600struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
601{
602 struct pci_controller_info *p = pbm->parent;
603 struct device_node *node = pbm->prom_node;
604 struct pci_bus *bus;
605
606 printk("PCI: Scanning PBM %s\n", node->full_name);
607
608 /* XXX parent device? XXX */
609 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
610 if (!bus) {
611 printk(KERN_ERR "Failed to create bus for %s\n",
612 node->full_name);
613 return NULL;
614 }
615 bus->secondary = pbm->pci_first_busno;
616 bus->subordinate = pbm->pci_last_busno;
617
618 bus->resource[0] = &pbm->io_space;
619 bus->resource[1] = &pbm->mem_space;
620
621 pci_of_scan_bus(pbm, node, bus);
622 pci_bus_add_devices(bus);
623 pci_bus_register_of_sysfs(bus);
624
625 return bus;
626}
627
303static void __init pci_scan_each_controller_bus(void) 628static void __init pci_scan_each_controller_bus(void)
304{ 629{
305 struct pci_controller_info *p; 630 struct pci_controller_info *p;
@@ -360,8 +685,33 @@ void pcibios_align_resource(void *data, struct resource *res,
360{ 685{
361} 686}
362 687
363int pcibios_enable_device(struct pci_dev *pdev, int mask) 688int pcibios_enable_device(struct pci_dev *dev, int mask)
364{ 689{
690 u16 cmd, oldcmd;
691 int i;
692
693 pci_read_config_word(dev, PCI_COMMAND, &cmd);
694 oldcmd = cmd;
695
696 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
697 struct resource *res = &dev->resource[i];
698
699 /* Only set up the requested stuff */
700 if (!(mask & (1<<i)))
701 continue;
702
703 if (res->flags & IORESOURCE_IO)
704 cmd |= PCI_COMMAND_IO;
705 if (res->flags & IORESOURCE_MEM)
706 cmd |= PCI_COMMAND_MEMORY;
707 }
708
709 if (cmd != oldcmd) {
710 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
711 pci_name(dev), cmd);
712 /* Enable the appropriate bits in the PCI command register. */
713 pci_write_config_word(dev, PCI_COMMAND, cmd);
714 }
365 return 0; 715 return 0;
366} 716}
367 717
@@ -422,17 +772,10 @@ char * __devinit pcibios_setup(char *str)
422static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, 772static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
423 enum pci_mmap_state mmap_state) 773 enum pci_mmap_state mmap_state)
424{ 774{
425 struct pcidev_cookie *pcp = pdev->sysdata; 775 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
426 struct pci_pbm_info *pbm;
427 struct pci_controller_info *p; 776 struct pci_controller_info *p;
428 unsigned long space_size, user_offset, user_size; 777 unsigned long space_size, user_offset, user_size;
429 778
430 if (!pcp)
431 return -ENXIO;
432 pbm = pcp->pbm;
433 if (!pbm)
434 return -ENXIO;
435
436 p = pbm->parent; 779 p = pbm->parent;
437 if (p->pbms_same_domain) { 780 if (p->pbms_same_domain) {
438 unsigned long lowest, highest; 781 unsigned long lowest, highest;
@@ -651,8 +994,7 @@ EXPORT_SYMBOL(pci_domain_nr);
651#ifdef CONFIG_PCI_MSI 994#ifdef CONFIG_PCI_MSI
652int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 995int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
653{ 996{
654 struct pcidev_cookie *pcp = pdev->sysdata; 997 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
655 struct pci_pbm_info *pbm = pcp->pbm;
656 struct pci_controller_info *p = pbm->parent; 998 struct pci_controller_info *p = pbm->parent;
657 int virt_irq, err; 999 int virt_irq, err;
658 1000
@@ -670,8 +1012,7 @@ void arch_teardown_msi_irq(unsigned int virt_irq)
670{ 1012{
671 struct msi_desc *entry = get_irq_msi(virt_irq); 1013 struct msi_desc *entry = get_irq_msi(virt_irq);
672 struct pci_dev *pdev = entry->dev; 1014 struct pci_dev *pdev = entry->dev;
673 struct pcidev_cookie *pcp = pdev->sysdata; 1015 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
674 struct pci_pbm_info *pbm = pcp->pbm;
675 struct pci_controller_info *p = pbm->parent; 1016 struct pci_controller_info *p = pbm->parent;
676 1017
677 if (!pbm->msi_num || !p->setup_msi_irq) 1018 if (!pbm->msi_num || !p->setup_msi_irq)
@@ -683,9 +1024,7 @@ void arch_teardown_msi_irq(unsigned int virt_irq)
683 1024
684struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) 1025struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
685{ 1026{
686 struct pcidev_cookie *pc = pdev->sysdata; 1027 return pdev->dev.archdata.prom_node;
687
688 return pc->op->node;
689} 1028}
690EXPORT_SYMBOL(pci_device_to_OF_node); 1029EXPORT_SYMBOL(pci_device_to_OF_node);
691 1030
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index 5a92cb90ebe0..0d3c95df0d95 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -16,713 +16,6 @@
16 16
17#include "pci_impl.h" 17#include "pci_impl.h"
18 18
19/* Fix self device of BUS and hook it into BUS->self.
20 * The pci_scan_bus does not do this for the host bridge.
21 */
22void __init pci_fixup_host_bridge_self(struct pci_bus *pbus)
23{
24 struct pci_dev *pdev;
25
26 list_for_each_entry(pdev, &pbus->devices, bus_list) {
27 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_HOST) {
28 pbus->self = pdev;
29 return;
30 }
31 }
32
33 prom_printf("PCI: Critical error, cannot find host bridge PDEV.\n");
34 prom_halt();
35}
36
37/* Find the OBP PROM device tree node for a PCI device. */
38static struct device_node * __init
39find_device_prom_node(struct pci_pbm_info *pbm, struct pci_dev *pdev,
40 struct device_node *bus_node,
41 struct linux_prom_pci_registers **pregs,
42 int *nregs)
43{
44 struct device_node *dp;
45
46 *nregs = 0;
47
48 /*
49 * Return the PBM's PROM node in case we are it's PCI device,
50 * as the PBM's reg property is different to standard PCI reg
51 * properties. We would delete this device entry otherwise,
52 * which confuses XFree86's device probing...
53 */
54 if ((pdev->bus->number == pbm->pci_bus->number) && (pdev->devfn == 0) &&
55 (pdev->vendor == PCI_VENDOR_ID_SUN) &&
56 (pdev->device == PCI_DEVICE_ID_SUN_PBM ||
57 pdev->device == PCI_DEVICE_ID_SUN_SCHIZO ||
58 pdev->device == PCI_DEVICE_ID_SUN_TOMATILLO ||
59 pdev->device == PCI_DEVICE_ID_SUN_SABRE ||
60 pdev->device == PCI_DEVICE_ID_SUN_HUMMINGBIRD))
61 return bus_node;
62
63 dp = bus_node->child;
64 while (dp) {
65 struct linux_prom_pci_registers *regs;
66 struct property *prop;
67 int len;
68
69 prop = of_find_property(dp, "reg", &len);
70 if (!prop)
71 goto do_next_sibling;
72
73 regs = prop->value;
74 if (((regs[0].phys_hi >> 8) & 0xff) == pdev->devfn) {
75 *pregs = regs;
76 *nregs = len / sizeof(struct linux_prom_pci_registers);
77 return dp;
78 }
79
80 do_next_sibling:
81 dp = dp->sibling;
82 }
83
84 return NULL;
85}
86
87/* Older versions of OBP on PCI systems encode 64-bit MEM
88 * space assignments incorrectly, this fixes them up. We also
89 * take the opportunity here to hide other kinds of bogus
90 * assignments.
91 */
92static void __init fixup_obp_assignments(struct pci_dev *pdev,
93 struct pcidev_cookie *pcp)
94{
95 int i;
96
97 if (pdev->vendor == PCI_VENDOR_ID_AL &&
98 (pdev->device == PCI_DEVICE_ID_AL_M7101 ||
99 pdev->device == PCI_DEVICE_ID_AL_M1533)) {
100 int i;
101
102 /* Zap all of the normal resources, they are
103 * meaningless and generate bogus resource collision
104 * messages. This is OpenBoot's ill-fated attempt to
105 * represent the implicit resources that these devices
106 * have.
107 */
108 pcp->num_prom_assignments = 0;
109 for (i = 0; i < 6; i++) {
110 pdev->resource[i].start =
111 pdev->resource[i].end =
112 pdev->resource[i].flags = 0;
113 }
114 pdev->resource[PCI_ROM_RESOURCE].start =
115 pdev->resource[PCI_ROM_RESOURCE].end =
116 pdev->resource[PCI_ROM_RESOURCE].flags = 0;
117 return;
118 }
119
120 for (i = 0; i < pcp->num_prom_assignments; i++) {
121 struct linux_prom_pci_registers *ap;
122 int space;
123
124 ap = &pcp->prom_assignments[i];
125 space = ap->phys_hi >> 24;
126 if ((space & 0x3) == 2 &&
127 (space & 0x4) != 0) {
128 ap->phys_hi &= ~(0x7 << 24);
129 ap->phys_hi |= 0x3 << 24;
130 }
131 }
132}
133
134static ssize_t
135show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
136{
137 struct pci_dev *pdev;
138 struct pcidev_cookie *sysdata;
139
140 pdev = to_pci_dev(dev);
141 sysdata = pdev->sysdata;
142
143 return snprintf (buf, PAGE_SIZE, "%s\n", sysdata->prom_node->full_name);
144}
145
146static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
147
148/* Fill in the PCI device cookie sysdata for the given
149 * PCI device. This cookie is the means by which one
150 * can get to OBP and PCI controller specific information
151 * for a PCI device.
152 */
153static void __init pdev_cookie_fillin(struct pci_pbm_info *pbm,
154 struct pci_dev *pdev,
155 struct device_node *bus_node)
156{
157 struct linux_prom_pci_registers *pregs = NULL;
158 struct pcidev_cookie *pcp;
159 struct device_node *dp;
160 struct property *prop;
161 int nregs, len, err;
162
163 dp = find_device_prom_node(pbm, pdev, bus_node,
164 &pregs, &nregs);
165 if (!dp) {
166 /* If it is not in the OBP device tree then
167 * there must be a damn good reason for it.
168 *
169 * So what we do is delete the device from the
170 * PCI device tree completely. This scenario
171 * is seen, for example, on CP1500 for the
172 * second EBUS/HappyMeal pair if the external
173 * connector for it is not present.
174 */
175 pci_remove_bus_device(pdev);
176 return;
177 }
178
179 pcp = kzalloc(sizeof(*pcp), GFP_ATOMIC);
180 if (pcp == NULL) {
181 prom_printf("PCI_COOKIE: Fatal malloc error, aborting...\n");
182 prom_halt();
183 }
184 pcp->pbm = pbm;
185 pcp->prom_node = dp;
186 pcp->op = of_find_device_by_node(dp);
187 memcpy(pcp->prom_regs, pregs,
188 nregs * sizeof(struct linux_prom_pci_registers));
189 pcp->num_prom_regs = nregs;
190
191 /* We can't have the pcidev_cookie assignments be just
192 * direct pointers into the property value, since they
193 * are potentially modified by the probing process.
194 */
195 prop = of_find_property(dp, "assigned-addresses", &len);
196 if (!prop) {
197 pcp->num_prom_assignments = 0;
198 } else {
199 memcpy(pcp->prom_assignments, prop->value, len);
200 pcp->num_prom_assignments =
201 (len / sizeof(pcp->prom_assignments[0]));
202 }
203
204 if (strcmp(dp->name, "ebus") == 0) {
205 struct linux_prom_ebus_ranges *erng;
206 int iter;
207
208 /* EBUS is special... */
209 prop = of_find_property(dp, "ranges", &len);
210 if (!prop) {
211 prom_printf("EBUS: Fatal error, no range property\n");
212 prom_halt();
213 }
214 erng = prop->value;
215 len = (len / sizeof(erng[0]));
216 for (iter = 0; iter < len; iter++) {
217 struct linux_prom_ebus_ranges *ep = &erng[iter];
218 struct linux_prom_pci_registers *ap;
219
220 ap = &pcp->prom_assignments[iter];
221
222 ap->phys_hi = ep->parent_phys_hi;
223 ap->phys_mid = ep->parent_phys_mid;
224 ap->phys_lo = ep->parent_phys_lo;
225 ap->size_hi = 0;
226 ap->size_lo = ep->size;
227 }
228 pcp->num_prom_assignments = len;
229 }
230
231 fixup_obp_assignments(pdev, pcp);
232
233 pdev->sysdata = pcp;
234
235 /* we don't really care if we can create this file or not,
236 * but we need to assign the result of the call or the world will fall
237 * under alien invasion and everybody will be frozen on a spaceship
238 * ready to be eaten on alpha centauri by some green and jelly humanoid.
239 */
240 err = sysfs_create_file(&pdev->dev.kobj, &dev_attr_obppath.attr);
241}
242
243void __init pci_fill_in_pbm_cookies(struct pci_bus *pbus,
244 struct pci_pbm_info *pbm,
245 struct device_node *dp)
246{
247 struct pci_dev *pdev, *pdev_next;
248 struct pci_bus *this_pbus, *pbus_next;
249
250 /* This must be _safe because the cookie fillin
251 routine can delete devices from the tree. */
252 list_for_each_entry_safe(pdev, pdev_next, &pbus->devices, bus_list)
253 pdev_cookie_fillin(pbm, pdev, dp);
254
255 list_for_each_entry_safe(this_pbus, pbus_next, &pbus->children, node) {
256 struct pcidev_cookie *pcp = this_pbus->self->sysdata;
257
258 pci_fill_in_pbm_cookies(this_pbus, pbm, pcp->prom_node);
259 }
260}
261
262static void __init bad_assignment(struct pci_dev *pdev,
263 struct linux_prom_pci_registers *ap,
264 struct resource *res,
265 int do_prom_halt)
266{
267 prom_printf("PCI: Bogus PROM assignment. BUS[%02x] DEVFN[%x]\n",
268 pdev->bus->number, pdev->devfn);
269 if (ap)
270 prom_printf("PCI: phys[%08x:%08x:%08x] size[%08x:%08x]\n",
271 ap->phys_hi, ap->phys_mid, ap->phys_lo,
272 ap->size_hi, ap->size_lo);
273 if (res)
274 prom_printf("PCI: RES[%016lx-->%016lx:(%lx)]\n",
275 res->start, res->end, res->flags);
276 if (do_prom_halt)
277 prom_halt();
278}
279
280static struct resource *
281__init get_root_resource(struct linux_prom_pci_registers *ap,
282 struct pci_pbm_info *pbm)
283{
284 int space = (ap->phys_hi >> 24) & 3;
285
286 switch (space) {
287 case 0:
288 /* Configuration space, silently ignore it. */
289 return NULL;
290
291 case 1:
292 /* 16-bit IO space */
293 return &pbm->io_space;
294
295 case 2:
296 /* 32-bit MEM space */
297 return &pbm->mem_space;
298
299 case 3:
300 /* 64-bit MEM space, these are allocated out of
301 * the 32-bit mem_space range for the PBM, ie.
302 * we just zero out the upper 32-bits.
303 */
304 return &pbm->mem_space;
305
306 default:
307 printk("PCI: What is resource space %x?\n", space);
308 return NULL;
309 };
310}
311
312static struct resource *
313__init get_device_resource(struct linux_prom_pci_registers *ap,
314 struct pci_dev *pdev)
315{
316 struct resource *res;
317 int breg = (ap->phys_hi & 0xff);
318
319 switch (breg) {
320 case PCI_ROM_ADDRESS:
321 /* Unfortunately I have seen several cases where
322 * buggy FCODE uses a space value of '1' (I/O space)
323 * in the register property for the ROM address
324 * so disable this sanity check for now.
325 */
326#if 0
327 {
328 int space = (ap->phys_hi >> 24) & 3;
329
330 /* It had better be MEM space. */
331 if (space != 2)
332 bad_assignment(pdev, ap, NULL, 0);
333 }
334#endif
335 res = &pdev->resource[PCI_ROM_RESOURCE];
336 break;
337
338 case PCI_BASE_ADDRESS_0:
339 case PCI_BASE_ADDRESS_1:
340 case PCI_BASE_ADDRESS_2:
341 case PCI_BASE_ADDRESS_3:
342 case PCI_BASE_ADDRESS_4:
343 case PCI_BASE_ADDRESS_5:
344 res = &pdev->resource[(breg - PCI_BASE_ADDRESS_0) / 4];
345 break;
346
347 default:
348 bad_assignment(pdev, ap, NULL, 0);
349 res = NULL;
350 break;
351 };
352
353 return res;
354}
355
356static void __init pdev_record_assignments(struct pci_pbm_info *pbm,
357 struct pci_dev *pdev)
358{
359 struct pcidev_cookie *pcp = pdev->sysdata;
360 int i;
361
362 for (i = 0; i < pcp->num_prom_assignments; i++) {
363 struct linux_prom_pci_registers *ap;
364 struct resource *root, *res;
365
366 /* The format of this property is specified in
367 * the PCI Bus Binding to IEEE1275-1994.
368 */
369 ap = &pcp->prom_assignments[i];
370 root = get_root_resource(ap, pbm);
371 res = get_device_resource(ap, pdev);
372 if (root == NULL || res == NULL ||
373 res->flags == 0)
374 continue;
375
376 /* Ok we know which resource this PROM assignment is
377 * for, sanity check it.
378 */
379 if ((res->start & 0xffffffffUL) != ap->phys_lo)
380 bad_assignment(pdev, ap, res, 1);
381
382 /* If it is a 64-bit MEM space assignment, verify that
383 * the resource is too and that the upper 32-bits match.
384 */
385 if (((ap->phys_hi >> 24) & 3) == 3) {
386 if (((res->flags & IORESOURCE_MEM) == 0) ||
387 ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
388 != PCI_BASE_ADDRESS_MEM_TYPE_64))
389 bad_assignment(pdev, ap, res, 1);
390 if ((res->start >> 32) != ap->phys_mid)
391 bad_assignment(pdev, ap, res, 1);
392
393 /* PBM cannot generate cpu initiated PIOs
394 * to the full 64-bit space. Therefore the
395 * upper 32-bits better be zero. If it is
396 * not, just skip it and we will assign it
397 * properly ourselves.
398 */
399 if ((res->start >> 32) != 0UL) {
400 printk(KERN_ERR "PCI: OBP assigns out of range MEM address "
401 "%016lx for region %ld on device %s\n",
402 res->start, (res - &pdev->resource[0]), pci_name(pdev));
403 continue;
404 }
405 }
406
407 /* Adjust the resource into the physical address space
408 * of this PBM.
409 */
410 pbm->parent->resource_adjust(pdev, res, root);
411
412 if (request_resource(root, res) < 0) {
413 int rnum;
414
415 /* OK, there is some conflict. But this is fine
416 * since we'll reassign it in the fixup pass.
417 *
418 * Do not print the warning for ROM resources
419 * as such a conflict is quite common and
420 * harmless as the ROM bar is disabled.
421 */
422 rnum = (res - &pdev->resource[0]);
423 if (rnum != PCI_ROM_RESOURCE)
424 printk(KERN_ERR "PCI: Resource collision, "
425 "region %d "
426 "[%016lx:%016lx] of device %s\n",
427 rnum,
428 res->start, res->end,
429 pci_name(pdev));
430 }
431 }
432}
433
434void __init pci_record_assignments(struct pci_pbm_info *pbm,
435 struct pci_bus *pbus)
436{
437 struct pci_dev *dev;
438 struct pci_bus *bus;
439
440 list_for_each_entry(dev, &pbus->devices, bus_list)
441 pdev_record_assignments(pbm, dev);
442
443 list_for_each_entry(bus, &pbus->children, node)
444 pci_record_assignments(pbm, bus);
445}
446
447/* Return non-zero if PDEV has implicit I/O resources even
448 * though it may not have an I/O base address register
449 * active.
450 */
451static int __init has_implicit_io(struct pci_dev *pdev)
452{
453 int class = pdev->class >> 8;
454
455 if (class == PCI_CLASS_NOT_DEFINED ||
456 class == PCI_CLASS_NOT_DEFINED_VGA ||
457 class == PCI_CLASS_STORAGE_IDE ||
458 (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
459 return 1;
460
461 return 0;
462}
463
464static void __init pdev_assign_unassigned(struct pci_pbm_info *pbm,
465 struct pci_dev *pdev)
466{
467 u32 reg;
468 u16 cmd;
469 int i, io_seen, mem_seen;
470
471 io_seen = mem_seen = 0;
472 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
473 struct resource *root, *res;
474 unsigned long size, min, max, align;
475
476 res = &pdev->resource[i];
477
478 if (res->flags & IORESOURCE_IO)
479 io_seen++;
480 else if (res->flags & IORESOURCE_MEM)
481 mem_seen++;
482
483 /* If it is already assigned or the resource does
484 * not exist, there is nothing to do.
485 */
486 if (res->parent != NULL || res->flags == 0UL)
487 continue;
488
489 /* Determine the root we allocate from. */
490 if (res->flags & IORESOURCE_IO) {
491 root = &pbm->io_space;
492 min = root->start + 0x400UL;
493 max = root->end;
494 } else {
495 root = &pbm->mem_space;
496 min = root->start;
497 max = min + 0x80000000UL;
498 }
499
500 size = res->end - res->start;
501 align = size + 1;
502 if (allocate_resource(root, res, size + 1, min, max, align, NULL, NULL) < 0) {
503 /* uh oh */
504 prom_printf("PCI: Failed to allocate resource %d for %s\n",
505 i, pci_name(pdev));
506 prom_halt();
507 }
508
509 /* Update PCI config space. */
510 pbm->parent->base_address_update(pdev, i);
511 }
512
513 /* Special case, disable the ROM. Several devices
514 * act funny (ie. do not respond to memory space writes)
515 * when it is left enabled. A good example are Qlogic,ISP
516 * adapters.
517 */
518 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &reg);
519 reg &= ~PCI_ROM_ADDRESS_ENABLE;
520 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, reg);
521
522 /* If we saw I/O or MEM resources, enable appropriate
523 * bits in PCI command register.
524 */
525 if (io_seen || mem_seen) {
526 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
527 if (io_seen || has_implicit_io(pdev))
528 cmd |= PCI_COMMAND_IO;
529 if (mem_seen)
530 cmd |= PCI_COMMAND_MEMORY;
531 pci_write_config_word(pdev, PCI_COMMAND, cmd);
532 }
533
534 /* If this is a PCI bridge or an IDE controller,
535 * enable bus mastering. In the former case also
536 * set the cache line size correctly.
537 */
538 if (((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) ||
539 (((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) &&
540 ((pdev->class & 0x80) != 0))) {
541 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
542 cmd |= PCI_COMMAND_MASTER;
543 pci_write_config_word(pdev, PCI_COMMAND, cmd);
544
545 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
546 pci_write_config_byte(pdev,
547 PCI_CACHE_LINE_SIZE,
548 (64 / sizeof(u32)));
549 }
550}
551
552void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
553 struct pci_bus *pbus)
554{
555 struct pci_dev *dev;
556 struct pci_bus *bus;
557
558 list_for_each_entry(dev, &pbus->devices, bus_list)
559 pdev_assign_unassigned(pbm, dev);
560
561 list_for_each_entry(bus, &pbus->children, node)
562 pci_assign_unassigned(pbm, bus);
563}
564
565static void __init pdev_fixup_irq(struct pci_dev *pdev)
566{
567 struct pcidev_cookie *pcp = pdev->sysdata;
568 struct of_device *op = pcp->op;
569
570 if (op->irqs[0] == 0xffffffff) {
571 pdev->irq = PCI_IRQ_NONE;
572 return;
573 }
574
575 pdev->irq = op->irqs[0];
576
577 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
578 pdev->irq & PCI_IRQ_INO);
579}
580
581void __init pci_fixup_irq(struct pci_pbm_info *pbm,
582 struct pci_bus *pbus)
583{
584 struct pci_dev *dev;
585 struct pci_bus *bus;
586
587 list_for_each_entry(dev, &pbus->devices, bus_list)
588 pdev_fixup_irq(dev);
589
590 list_for_each_entry(bus, &pbus->children, node)
591 pci_fixup_irq(pbm, bus);
592}
593
594static void pdev_setup_busmastering(struct pci_dev *pdev, int is_66mhz)
595{
596 u16 cmd;
597 u8 hdr_type, min_gnt, ltimer;
598
599 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
600 cmd |= PCI_COMMAND_MASTER;
601 pci_write_config_word(pdev, PCI_COMMAND, cmd);
602
603 /* Read it back, if the mastering bit did not
604 * get set, the device does not support bus
605 * mastering so we have nothing to do here.
606 */
607 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
608 if ((cmd & PCI_COMMAND_MASTER) == 0)
609 return;
610
611 /* Set correct cache line size, 64-byte on all
612 * Sparc64 PCI systems. Note that the value is
613 * measured in 32-bit words.
614 */
615 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
616 64 / sizeof(u32));
617
618 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr_type);
619 hdr_type &= ~0x80;
620 if (hdr_type != PCI_HEADER_TYPE_NORMAL)
621 return;
622
623 /* If the latency timer is already programmed with a non-zero
624 * value, assume whoever set it (OBP or whoever) knows what
625 * they are doing.
626 */
627 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ltimer);
628 if (ltimer != 0)
629 return;
630
631 /* XXX Since I'm tipping off the min grant value to
632 * XXX choose a suitable latency timer value, I also
633 * XXX considered making use of the max latency value
634 * XXX as well. Unfortunately I've seen too many bogusly
635 * XXX low settings for it to the point where it lacks
636 * XXX any usefulness. In one case, an ethernet card
637 * XXX claimed a min grant of 10 and a max latency of 5.
638 * XXX Now, if I had two such cards on the same bus I
639 * XXX could not set the desired burst period (calculated
640 * XXX from min grant) without violating the max latency
641 * XXX bound. Duh...
642 * XXX
643 * XXX I blame dumb PC bios implementors for stuff like
644 * XXX this, most of them don't even try to do something
645 * XXX sensible with latency timer values and just set some
646 * XXX default value (usually 32) into every device.
647 */
648
649 pci_read_config_byte(pdev, PCI_MIN_GNT, &min_gnt);
650
651 if (min_gnt == 0) {
652 /* If no min_gnt setting then use a default
653 * value.
654 */
655 if (is_66mhz)
656 ltimer = 16;
657 else
658 ltimer = 32;
659 } else {
660 int shift_factor;
661
662 if (is_66mhz)
663 shift_factor = 2;
664 else
665 shift_factor = 3;
666
667 /* Use a default value when the min_gnt value
668 * is erroneously high.
669 */
670 if (((unsigned int) min_gnt << shift_factor) > 512 ||
671 ((min_gnt << shift_factor) & 0xff) == 0) {
672 ltimer = 8 << shift_factor;
673 } else {
674 ltimer = min_gnt << shift_factor;
675 }
676 }
677
678 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ltimer);
679}
680
681void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
682 struct pci_bus *pbus)
683{
684 struct pci_dev *pdev;
685 int all_are_66mhz;
686 u16 status;
687
688 if (pbm->is_66mhz_capable == 0) {
689 all_are_66mhz = 0;
690 goto out;
691 }
692
693 all_are_66mhz = 1;
694 list_for_each_entry(pdev, &pbus->devices, bus_list) {
695 pci_read_config_word(pdev, PCI_STATUS, &status);
696 if (!(status & PCI_STATUS_66MHZ)) {
697 all_are_66mhz = 0;
698 break;
699 }
700 }
701out:
702 pbm->all_devs_66mhz = all_are_66mhz;
703
704 printk("PCI%d(PBM%c): Bus running at %dMHz\n",
705 pbm->parent->index,
706 (pbm == &pbm->parent->pbm_A) ? 'A' : 'B',
707 (all_are_66mhz ? 66 : 33));
708}
709
710void pci_setup_busmastering(struct pci_pbm_info *pbm,
711 struct pci_bus *pbus)
712{
713 struct pci_dev *dev;
714 struct pci_bus *bus;
715 int is_66mhz;
716
717 is_66mhz = pbm->is_66mhz_capable && pbm->all_devs_66mhz;
718
719 list_for_each_entry(dev, &pbus->devices, bus_list)
720 pdev_setup_busmastering(dev, is_66mhz);
721
722 list_for_each_entry(bus, &pbus->children, node)
723 pci_setup_busmastering(pbm, bus);
724}
725
726void pci_register_legacy_regions(struct resource *io_res, 19void pci_register_legacy_regions(struct resource *io_res,
727 struct resource *mem_res) 20 struct resource *mem_res)
728{ 21{
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index 971e2bea30b4..ea8a6bd146ae 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -17,20 +17,7 @@ extern struct pci_controller_info *pci_controller_root;
17extern int pci_num_controllers; 17extern int pci_num_controllers;
18 18
19/* PCI bus scanning and fixup support. */ 19/* PCI bus scanning and fixup support. */
20extern void pci_fixup_host_bridge_self(struct pci_bus *pbus); 20extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
21extern void pci_fill_in_pbm_cookies(struct pci_bus *pbus,
22 struct pci_pbm_info *pbm,
23 struct device_node *prom_node);
24extern void pci_record_assignments(struct pci_pbm_info *pbm,
25 struct pci_bus *pbus);
26extern void pci_assign_unassigned(struct pci_pbm_info *pbm,
27 struct pci_bus *pbus);
28extern void pci_fixup_irq(struct pci_pbm_info *pbm,
29 struct pci_bus *pbus);
30extern void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
31 struct pci_bus *pbus);
32extern void pci_setup_busmastering(struct pci_pbm_info *pbm,
33 struct pci_bus *pbus);
34extern void pci_register_legacy_regions(struct resource *io_res, 21extern void pci_register_legacy_regions(struct resource *io_res,
35 struct resource *mem_res); 22 struct resource *mem_res);
36 23
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index 7aca0f33f885..554daabb381e 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -220,7 +220,6 @@ static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
220 */ 220 */
221static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp) 221static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
222{ 222{
223 struct pcidev_cookie *pcp;
224 struct pci_iommu *iommu; 223 struct pci_iommu *iommu;
225 iopte_t *iopte; 224 iopte_t *iopte;
226 unsigned long flags, order, first_page; 225 unsigned long flags, order, first_page;
@@ -237,8 +236,7 @@ static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr
237 return NULL; 236 return NULL;
238 memset((char *)first_page, 0, PAGE_SIZE << order); 237 memset((char *)first_page, 0, PAGE_SIZE << order);
239 238
240 pcp = pdev->sysdata; 239 iommu = pdev->dev.archdata.iommu;
241 iommu = pcp->pbm->iommu;
242 240
243 spin_lock_irqsave(&iommu->lock, flags); 241 spin_lock_irqsave(&iommu->lock, flags);
244 iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT); 242 iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
@@ -268,14 +266,12 @@ static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr
268/* Free and unmap a consistent DMA translation. */ 266/* Free and unmap a consistent DMA translation. */
269static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma) 267static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
270{ 268{
271 struct pcidev_cookie *pcp;
272 struct pci_iommu *iommu; 269 struct pci_iommu *iommu;
273 iopte_t *iopte; 270 iopte_t *iopte;
274 unsigned long flags, order, npages; 271 unsigned long flags, order, npages;
275 272
276 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; 273 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
277 pcp = pdev->sysdata; 274 iommu = pdev->dev.archdata.iommu;
278 iommu = pcp->pbm->iommu;
279 iopte = iommu->page_table + 275 iopte = iommu->page_table +
280 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); 276 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
281 277
@@ -295,7 +291,6 @@ static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu,
295 */ 291 */
296static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction) 292static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
297{ 293{
298 struct pcidev_cookie *pcp;
299 struct pci_iommu *iommu; 294 struct pci_iommu *iommu;
300 struct pci_strbuf *strbuf; 295 struct pci_strbuf *strbuf;
301 iopte_t *base; 296 iopte_t *base;
@@ -304,9 +299,8 @@ static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz,
304 u32 bus_addr, ret; 299 u32 bus_addr, ret;
305 unsigned long iopte_protection; 300 unsigned long iopte_protection;
306 301
307 pcp = pdev->sysdata; 302 iommu = pdev->dev.archdata.iommu;
308 iommu = pcp->pbm->iommu; 303 strbuf = pdev->dev.archdata.stc;
309 strbuf = &pcp->pbm->stc;
310 304
311 if (unlikely(direction == PCI_DMA_NONE)) 305 if (unlikely(direction == PCI_DMA_NONE))
312 goto bad_no_ctx; 306 goto bad_no_ctx;
@@ -416,7 +410,6 @@ do_flush_sync:
416/* Unmap a single streaming mode DMA translation. */ 410/* Unmap a single streaming mode DMA translation. */
417static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) 411static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
418{ 412{
419 struct pcidev_cookie *pcp;
420 struct pci_iommu *iommu; 413 struct pci_iommu *iommu;
421 struct pci_strbuf *strbuf; 414 struct pci_strbuf *strbuf;
422 iopte_t *base; 415 iopte_t *base;
@@ -428,9 +421,8 @@ static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_
428 return; 421 return;
429 } 422 }
430 423
431 pcp = pdev->sysdata; 424 iommu = pdev->dev.archdata.iommu;
432 iommu = pcp->pbm->iommu; 425 strbuf = pdev->dev.archdata.stc;
433 strbuf = &pcp->pbm->stc;
434 426
435 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); 427 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
436 npages >>= IO_PAGE_SHIFT; 428 npages >>= IO_PAGE_SHIFT;
@@ -549,7 +541,6 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
549 */ 541 */
550static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) 542static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
551{ 543{
552 struct pcidev_cookie *pcp;
553 struct pci_iommu *iommu; 544 struct pci_iommu *iommu;
554 struct pci_strbuf *strbuf; 545 struct pci_strbuf *strbuf;
555 unsigned long flags, ctx, npages, iopte_protection; 546 unsigned long flags, ctx, npages, iopte_protection;
@@ -570,9 +561,8 @@ static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int n
570 return 1; 561 return 1;
571 } 562 }
572 563
573 pcp = pdev->sysdata; 564 iommu = pdev->dev.archdata.iommu;
574 iommu = pcp->pbm->iommu; 565 strbuf = pdev->dev.archdata.stc;
575 strbuf = &pcp->pbm->stc;
576 566
577 if (unlikely(direction == PCI_DMA_NONE)) 567 if (unlikely(direction == PCI_DMA_NONE))
578 goto bad_no_ctx; 568 goto bad_no_ctx;
@@ -636,7 +626,6 @@ bad_no_ctx:
636/* Unmap a set of streaming mode DMA translations. */ 626/* Unmap a set of streaming mode DMA translations. */
637static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) 627static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
638{ 628{
639 struct pcidev_cookie *pcp;
640 struct pci_iommu *iommu; 629 struct pci_iommu *iommu;
641 struct pci_strbuf *strbuf; 630 struct pci_strbuf *strbuf;
642 iopte_t *base; 631 iopte_t *base;
@@ -648,9 +637,8 @@ static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, in
648 WARN_ON(1); 637 WARN_ON(1);
649 } 638 }
650 639
651 pcp = pdev->sysdata; 640 iommu = pdev->dev.archdata.iommu;
652 iommu = pcp->pbm->iommu; 641 strbuf = pdev->dev.archdata.stc;
653 strbuf = &pcp->pbm->stc;
654 642
655 bus_addr = sglist->dma_address & IO_PAGE_MASK; 643 bus_addr = sglist->dma_address & IO_PAGE_MASK;
656 644
@@ -696,14 +684,12 @@ static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, in
696 */ 684 */
697static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) 685static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
698{ 686{
699 struct pcidev_cookie *pcp;
700 struct pci_iommu *iommu; 687 struct pci_iommu *iommu;
701 struct pci_strbuf *strbuf; 688 struct pci_strbuf *strbuf;
702 unsigned long flags, ctx, npages; 689 unsigned long flags, ctx, npages;
703 690
704 pcp = pdev->sysdata; 691 iommu = pdev->dev.archdata.iommu;
705 iommu = pcp->pbm->iommu; 692 strbuf = pdev->dev.archdata.stc;
706 strbuf = &pcp->pbm->stc;
707 693
708 if (!strbuf->strbuf_enabled) 694 if (!strbuf->strbuf_enabled)
709 return; 695 return;
@@ -736,15 +722,13 @@ static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_
736 */ 722 */
737static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) 723static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
738{ 724{
739 struct pcidev_cookie *pcp;
740 struct pci_iommu *iommu; 725 struct pci_iommu *iommu;
741 struct pci_strbuf *strbuf; 726 struct pci_strbuf *strbuf;
742 unsigned long flags, ctx, npages, i; 727 unsigned long flags, ctx, npages, i;
743 u32 bus_addr; 728 u32 bus_addr;
744 729
745 pcp = pdev->sysdata; 730 iommu = pdev->dev.archdata.iommu;
746 iommu = pcp->pbm->iommu; 731 strbuf = pdev->dev.archdata.stc;
747 strbuf = &pcp->pbm->stc;
748 732
749 if (!strbuf->strbuf_enabled) 733 if (!strbuf->strbuf_enabled)
750 return; 734 return;
@@ -809,13 +793,12 @@ static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
809 793
810int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) 794int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
811{ 795{
812 struct pcidev_cookie *pcp = pdev->sysdata;
813 u64 dma_addr_mask; 796 u64 dma_addr_mask;
814 797
815 if (pdev == NULL) { 798 if (pdev == NULL) {
816 dma_addr_mask = 0xffffffff; 799 dma_addr_mask = 0xffffffff;
817 } else { 800 } else {
818 struct pci_iommu *iommu = pcp->pbm->iommu; 801 struct pci_iommu *iommu = pdev->dev.archdata.iommu;
819 802
820 dma_addr_mask = iommu->dma_addr_mask; 803 dma_addr_mask = iommu->dma_addr_mask;
821 804
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index fda5db223d96..12ea30d30b2f 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -905,8 +905,7 @@ static void psycho_resource_adjust(struct pci_dev *pdev,
905 905
906static void psycho_base_address_update(struct pci_dev *pdev, int resource) 906static void psycho_base_address_update(struct pci_dev *pdev, int resource)
907{ 907{
908 struct pcidev_cookie *pcp = pdev->sysdata; 908 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
909 struct pci_pbm_info *pbm = pcp->pbm;
910 struct resource *res, *root; 909 struct resource *res, *root;
911 u32 reg; 910 u32 reg;
912 int where, size, is_64bit; 911 int where, size, is_64bit;
@@ -968,28 +967,7 @@ static void pbm_config_busmastering(struct pci_pbm_info *pbm)
968static void pbm_scan_bus(struct pci_controller_info *p, 967static void pbm_scan_bus(struct pci_controller_info *p,
969 struct pci_pbm_info *pbm) 968 struct pci_pbm_info *pbm)
970{ 969{
971 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); 970 pbm->pci_bus = pci_scan_one_pbm(pbm);
972
973 if (!cookie) {
974 prom_printf("PSYCHO: Critical allocation failure.\n");
975 prom_halt();
976 }
977
978 /* All we care about is the PBM. */
979 cookie->pbm = pbm;
980
981 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
982 p->pci_ops,
983 pbm);
984 pci_fixup_host_bridge_self(pbm->pci_bus);
985 pbm->pci_bus->self->sysdata = cookie;
986
987 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
988 pci_record_assignments(pbm, pbm->pci_bus);
989 pci_assign_unassigned(pbm, pbm->pci_bus);
990 pci_fixup_irq(pbm, pbm->pci_bus);
991 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
992 pci_setup_busmastering(pbm, pbm->pci_bus);
993} 971}
994 972
995static void psycho_scan_bus(struct pci_controller_info *p) 973static void psycho_scan_bus(struct pci_controller_info *p)
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 94bb681f2323..bbf624517508 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -710,8 +710,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
710 p->index); 710 p->index);
711 ret = IRQ_HANDLED; 711 ret = IRQ_HANDLED;
712 } 712 }
713 pci_read_config_word(sabre_root_bus->self, 713 pci_bus_read_config_word(sabre_root_bus, 0,
714 PCI_STATUS, &stat); 714 PCI_STATUS, &stat);
715 if (stat & (PCI_STATUS_PARITY | 715 if (stat & (PCI_STATUS_PARITY |
716 PCI_STATUS_SIG_TARGET_ABORT | 716 PCI_STATUS_SIG_TARGET_ABORT |
717 PCI_STATUS_REC_TARGET_ABORT | 717 PCI_STATUS_REC_TARGET_ABORT |
@@ -719,8 +719,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
719 PCI_STATUS_SIG_SYSTEM_ERROR)) { 719 PCI_STATUS_SIG_SYSTEM_ERROR)) {
720 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n", 720 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
721 p->index, stat); 721 p->index, stat);
722 pci_write_config_word(sabre_root_bus->self, 722 pci_bus_write_config_word(sabre_root_bus, 0,
723 PCI_STATUS, 0xffff); 723 PCI_STATUS, 0xffff);
724 ret = IRQ_HANDLED; 724 ret = IRQ_HANDLED;
725 } 725 }
726 return ret; 726 return ret;
@@ -887,8 +887,7 @@ static void sabre_resource_adjust(struct pci_dev *pdev,
887 887
888static void sabre_base_address_update(struct pci_dev *pdev, int resource) 888static void sabre_base_address_update(struct pci_dev *pdev, int resource)
889{ 889{
890 struct pcidev_cookie *pcp = pdev->sysdata; 890 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
891 struct pci_pbm_info *pbm = pcp->pbm;
892 struct resource *res; 891 struct resource *res;
893 unsigned long base; 892 unsigned long base;
894 u32 reg; 893 u32 reg;
@@ -978,27 +977,11 @@ static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
978 } 977 }
979} 978}
980 979
981static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
982{
983 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
984
985 if (!cookie) {
986 prom_printf("SABRE: Critical allocation failure.\n");
987 prom_halt();
988 }
989
990 /* All we care about is the PBM. */
991 cookie->pbm = pbm;
992
993 return cookie;
994}
995
996static void sabre_scan_bus(struct pci_controller_info *p) 980static void sabre_scan_bus(struct pci_controller_info *p)
997{ 981{
998 static int once; 982 static int once;
999 struct pci_bus *sabre_bus, *pbus; 983 struct pci_bus *sabre_bus, *pbus;
1000 struct pci_pbm_info *pbm; 984 struct pci_pbm_info *pbm;
1001 struct pcidev_cookie *cookie;
1002 int sabres_scanned; 985 int sabres_scanned;
1003 986
1004 /* The APB bridge speaks to the Sabre host PCI bridge 987 /* The APB bridge speaks to the Sabre host PCI bridge
@@ -1020,13 +1003,9 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1020 } 1003 }
1021 once++; 1004 once++;
1022 1005
1023 cookie = alloc_bridge_cookie(&p->pbm_A); 1006 sabre_bus = pci_scan_one_pbm(&p->pbm_A);
1024 1007 if (!sabre_bus)
1025 sabre_bus = pci_scan_bus(p->pci_first_busno, 1008 return;
1026 p->pci_ops,
1027 &p->pbm_A);
1028 pci_fixup_host_bridge_self(sabre_bus);
1029 sabre_bus->self->sysdata = cookie;
1030 1009
1031 sabre_root_bus = sabre_bus; 1010 sabre_root_bus = sabre_bus;
1032 1011
@@ -1043,19 +1022,9 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1043 } else 1022 } else
1044 continue; 1023 continue;
1045 1024
1046 cookie = alloc_bridge_cookie(pbm);
1047 pbus->self->sysdata = cookie;
1048
1049 sabres_scanned++; 1025 sabres_scanned++;
1050
1051 pbus->sysdata = pbm; 1026 pbus->sysdata = pbm;
1052 pbm->pci_bus = pbus; 1027 pbm->pci_bus = pbus;
1053 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1054 pci_record_assignments(pbm, pbus);
1055 pci_assign_unassigned(pbm, pbus);
1056 pci_fixup_irq(pbm, pbus);
1057 pci_determine_66mhz_disposition(pbm, pbus);
1058 pci_setup_busmastering(pbm, pbus);
1059 } 1028 }
1060 1029
1061 if (!sabres_scanned) { 1030 if (!sabres_scanned) {
@@ -1063,12 +1032,6 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1063 pbm = &p->pbm_A; 1032 pbm = &p->pbm_A;
1064 sabre_bus->sysdata = pbm; 1033 sabre_bus->sysdata = pbm;
1065 pbm->pci_bus = sabre_bus; 1034 pbm->pci_bus = sabre_bus;
1066 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1067 pci_record_assignments(pbm, sabre_bus);
1068 pci_assign_unassigned(pbm, sabre_bus);
1069 pci_fixup_irq(pbm, sabre_bus);
1070 pci_determine_66mhz_disposition(pbm, sabre_bus);
1071 pci_setup_busmastering(pbm, sabre_bus);
1072 } 1035 }
1073 1036
1074 sabre_register_error_handlers(p); 1037 sabre_register_error_handlers(p);
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 66911b126aed..48dea52ac522 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -1232,28 +1232,7 @@ static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1232static void pbm_scan_bus(struct pci_controller_info *p, 1232static void pbm_scan_bus(struct pci_controller_info *p,
1233 struct pci_pbm_info *pbm) 1233 struct pci_pbm_info *pbm)
1234{ 1234{
1235 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); 1235 pbm->pci_bus = pci_scan_one_pbm(pbm);
1236
1237 if (!cookie) {
1238 prom_printf("%s: Critical allocation failure.\n", pbm->name);
1239 prom_halt();
1240 }
1241
1242 /* All we care about is the PBM. */
1243 cookie->pbm = pbm;
1244
1245 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1246 p->pci_ops,
1247 pbm);
1248 pci_fixup_host_bridge_self(pbm->pci_bus);
1249 pbm->pci_bus->self->sysdata = cookie;
1250
1251 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1252 pci_record_assignments(pbm, pbm->pci_bus);
1253 pci_assign_unassigned(pbm, pbm->pci_bus);
1254 pci_fixup_irq(pbm, pbm->pci_bus);
1255 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1256 pci_setup_busmastering(pbm, pbm->pci_bus);
1257} 1236}
1258 1237
1259static void __schizo_scan_bus(struct pci_controller_info *p, 1238static void __schizo_scan_bus(struct pci_controller_info *p,
@@ -1297,8 +1276,7 @@ static void tomatillo_scan_bus(struct pci_controller_info *p)
1297 1276
1298static void schizo_base_address_update(struct pci_dev *pdev, int resource) 1277static void schizo_base_address_update(struct pci_dev *pdev, int resource)
1299{ 1278{
1300 struct pcidev_cookie *pcp = pdev->sysdata; 1279 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1301 struct pci_pbm_info *pbm = pcp->pbm;
1302 struct resource *res, *root; 1280 struct resource *res, *root;
1303 u32 reg; 1281 u32 reg;
1304 int where, size, is_64bit; 1282 int where, size, is_64bit;
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index bd74c155519e..eec7def379dc 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -53,8 +53,8 @@ static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long pro
53/* Interrupts must be disabled. */ 53/* Interrupts must be disabled. */
54static long pci_iommu_batch_flush(struct pci_iommu_batch *p) 54static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
55{ 55{
56 struct pcidev_cookie *pcp = p->pdev->sysdata; 56 struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
57 unsigned long devhandle = pcp->pbm->devhandle; 57 unsigned long devhandle = pbm->devhandle;
58 unsigned long prot = p->prot; 58 unsigned long prot = p->prot;
59 unsigned long entry = p->entry; 59 unsigned long entry = p->entry;
60 u64 *pglist = p->pglist; 60 u64 *pglist = p->pglist;
@@ -159,7 +159,6 @@ static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, un
159 159
160static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp) 160static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
161{ 161{
162 struct pcidev_cookie *pcp;
163 struct pci_iommu *iommu; 162 struct pci_iommu *iommu;
164 unsigned long flags, order, first_page, npages, n; 163 unsigned long flags, order, first_page, npages, n;
165 void *ret; 164 void *ret;
@@ -178,8 +177,7 @@ static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr
178 177
179 memset((char *)first_page, 0, PAGE_SIZE << order); 178 memset((char *)first_page, 0, PAGE_SIZE << order);
180 179
181 pcp = pdev->sysdata; 180 iommu = pdev->dev.archdata.iommu;
182 iommu = pcp->pbm->iommu;
183 181
184 spin_lock_irqsave(&iommu->lock, flags); 182 spin_lock_irqsave(&iommu->lock, flags);
185 entry = pci_arena_alloc(&iommu->arena, npages); 183 entry = pci_arena_alloc(&iommu->arena, npages);
@@ -226,15 +224,15 @@ arena_alloc_fail:
226 224
227static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma) 225static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
228{ 226{
229 struct pcidev_cookie *pcp; 227 struct pci_pbm_info *pbm;
230 struct pci_iommu *iommu; 228 struct pci_iommu *iommu;
231 unsigned long flags, order, npages, entry; 229 unsigned long flags, order, npages, entry;
232 u32 devhandle; 230 u32 devhandle;
233 231
234 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; 232 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
235 pcp = pdev->sysdata; 233 iommu = pdev->dev.archdata.iommu;
236 iommu = pcp->pbm->iommu; 234 pbm = pdev->dev.archdata.host_controller;
237 devhandle = pcp->pbm->devhandle; 235 devhandle = pbm->devhandle;
238 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); 236 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
239 237
240 spin_lock_irqsave(&iommu->lock, flags); 238 spin_lock_irqsave(&iommu->lock, flags);
@@ -259,7 +257,6 @@ static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu,
259 257
260static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction) 258static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
261{ 259{
262 struct pcidev_cookie *pcp;
263 struct pci_iommu *iommu; 260 struct pci_iommu *iommu;
264 unsigned long flags, npages, oaddr; 261 unsigned long flags, npages, oaddr;
265 unsigned long i, base_paddr; 262 unsigned long i, base_paddr;
@@ -267,8 +264,7 @@ static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz,
267 unsigned long prot; 264 unsigned long prot;
268 long entry; 265 long entry;
269 266
270 pcp = pdev->sysdata; 267 iommu = pdev->dev.archdata.iommu;
271 iommu = pcp->pbm->iommu;
272 268
273 if (unlikely(direction == PCI_DMA_NONE)) 269 if (unlikely(direction == PCI_DMA_NONE))
274 goto bad; 270 goto bad;
@@ -324,7 +320,7 @@ iommu_map_fail:
324 320
325static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) 321static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
326{ 322{
327 struct pcidev_cookie *pcp; 323 struct pci_pbm_info *pbm;
328 struct pci_iommu *iommu; 324 struct pci_iommu *iommu;
329 unsigned long flags, npages; 325 unsigned long flags, npages;
330 long entry; 326 long entry;
@@ -336,9 +332,9 @@ static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_
336 return; 332 return;
337 } 333 }
338 334
339 pcp = pdev->sysdata; 335 iommu = pdev->dev.archdata.iommu;
340 iommu = pcp->pbm->iommu; 336 pbm = pdev->dev.archdata.host_controller;
341 devhandle = pcp->pbm->devhandle; 337 devhandle = pbm->devhandle;
342 338
343 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); 339 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
344 npages >>= IO_PAGE_SHIFT; 340 npages >>= IO_PAGE_SHIFT;
@@ -460,7 +456,6 @@ iommu_map_failed:
460 456
461static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) 457static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
462{ 458{
463 struct pcidev_cookie *pcp;
464 struct pci_iommu *iommu; 459 struct pci_iommu *iommu;
465 unsigned long flags, npages, prot; 460 unsigned long flags, npages, prot;
466 u32 dma_base; 461 u32 dma_base;
@@ -480,8 +475,7 @@ static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int n
480 return 1; 475 return 1;
481 } 476 }
482 477
483 pcp = pdev->sysdata; 478 iommu = pdev->dev.archdata.iommu;
484 iommu = pcp->pbm->iommu;
485 479
486 if (unlikely(direction == PCI_DMA_NONE)) 480 if (unlikely(direction == PCI_DMA_NONE))
487 goto bad; 481 goto bad;
@@ -537,7 +531,7 @@ iommu_map_failed:
537 531
538static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) 532static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
539{ 533{
540 struct pcidev_cookie *pcp; 534 struct pci_pbm_info *pbm;
541 struct pci_iommu *iommu; 535 struct pci_iommu *iommu;
542 unsigned long flags, i, npages; 536 unsigned long flags, i, npages;
543 long entry; 537 long entry;
@@ -548,9 +542,9 @@ static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, in
548 WARN_ON(1); 542 WARN_ON(1);
549 } 543 }
550 544
551 pcp = pdev->sysdata; 545 iommu = pdev->dev.archdata.iommu;
552 iommu = pcp->pbm->iommu; 546 pbm = pdev->dev.archdata.host_controller;
553 devhandle = pcp->pbm->devhandle; 547 devhandle = pbm->devhandle;
554 548
555 bus_addr = sglist->dma_address & IO_PAGE_MASK; 549 bus_addr = sglist->dma_address & IO_PAGE_MASK;
556 550
@@ -600,132 +594,12 @@ struct pci_iommu_ops pci_sun4v_iommu_ops = {
600 .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu, 594 .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
601}; 595};
602 596
603/* SUN4V PCI configuration space accessors. */
604
605struct pdev_entry {
606 struct pdev_entry *next;
607 u32 devhandle;
608 unsigned int bus;
609 unsigned int device;
610 unsigned int func;
611};
612
613#define PDEV_HTAB_SIZE 16
614#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1)
615static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE];
616
617static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
618{
619 unsigned int val;
620
621 val = (devhandle ^ (devhandle >> 4));
622 val ^= bus;
623 val ^= device;
624 val ^= func;
625
626 return val & PDEV_HTAB_MASK;
627}
628
629static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
630{
631 struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL);
632 struct pdev_entry **slot;
633
634 if (!p)
635 return -ENOMEM;
636
637 slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
638 p->next = *slot;
639 *slot = p;
640
641 p->devhandle = devhandle;
642 p->bus = bus;
643 p->device = device;
644 p->func = func;
645
646 return 0;
647}
648
649/* Recursively descend into the OBP device tree, rooted at toplevel_node,
650 * looking for a PCI device matching bus and devfn.
651 */
652static int obp_find(struct device_node *toplevel_node, unsigned int bus, unsigned int devfn)
653{
654 toplevel_node = toplevel_node->child;
655
656 while (toplevel_node != NULL) {
657 struct linux_prom_pci_registers *regs;
658 struct property *prop;
659 int ret;
660
661 ret = obp_find(toplevel_node, bus, devfn);
662 if (ret != 0)
663 return ret;
664
665 prop = of_find_property(toplevel_node, "reg", NULL);
666 if (!prop)
667 goto next_sibling;
668
669 regs = prop->value;
670 if (((regs->phys_hi >> 16) & 0xff) == bus &&
671 ((regs->phys_hi >> 8) & 0xff) == devfn)
672 break;
673
674 next_sibling:
675 toplevel_node = toplevel_node->sibling;
676 }
677
678 return toplevel_node != NULL;
679}
680
681static int pdev_htab_populate(struct pci_pbm_info *pbm)
682{
683 u32 devhandle = pbm->devhandle;
684 unsigned int bus;
685
686 for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) {
687 unsigned int devfn;
688
689 for (devfn = 0; devfn < 256; devfn++) {
690 unsigned int device = PCI_SLOT(devfn);
691 unsigned int func = PCI_FUNC(devfn);
692
693 if (obp_find(pbm->prom_node, bus, devfn)) {
694 int err = pdev_htab_add(devhandle, bus,
695 device, func);
696 if (err)
697 return err;
698 }
699 }
700 }
701
702 return 0;
703}
704
705static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
706{
707 struct pdev_entry *p;
708
709 p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
710 while (p) {
711 if (p->devhandle == devhandle &&
712 p->bus == bus &&
713 p->device == device &&
714 p->func == func)
715 break;
716
717 p = p->next;
718 }
719
720 return p;
721}
722
723static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func) 597static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
724{ 598{
725 if (bus < pbm->pci_first_busno || 599 if (bus < pbm->pci_first_busno ||
726 bus > pbm->pci_last_busno) 600 bus > pbm->pci_last_busno)
727 return 1; 601 return 1;
728 return pdev_find(pbm->devhandle, bus, device, func) == NULL; 602 return 0;
729} 603}
730 604
731static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, 605static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
@@ -800,27 +674,7 @@ static struct pci_ops pci_sun4v_ops = {
800static void pbm_scan_bus(struct pci_controller_info *p, 674static void pbm_scan_bus(struct pci_controller_info *p,
801 struct pci_pbm_info *pbm) 675 struct pci_pbm_info *pbm)
802{ 676{
803 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); 677 pbm->pci_bus = pci_scan_one_pbm(pbm);
804
805 if (!cookie) {
806 prom_printf("%s: Critical allocation failure.\n", pbm->name);
807 prom_halt();
808 }
809
810 /* All we care about is the PBM. */
811 cookie->pbm = pbm;
812
813 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, p->pci_ops, pbm);
814#if 0
815 pci_fixup_host_bridge_self(pbm->pci_bus);
816 pbm->pci_bus->self->sysdata = cookie;
817#endif
818 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
819 pci_record_assignments(pbm, pbm->pci_bus);
820 pci_assign_unassigned(pbm, pbm->pci_bus);
821 pci_fixup_irq(pbm, pbm->pci_bus);
822 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
823 pci_setup_busmastering(pbm, pbm->pci_bus);
824} 678}
825 679
826static void pci_sun4v_scan_bus(struct pci_controller_info *p) 680static void pci_sun4v_scan_bus(struct pci_controller_info *p)
@@ -846,8 +700,7 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
846 700
847static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource) 701static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
848{ 702{
849 struct pcidev_cookie *pcp = pdev->sysdata; 703 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
850 struct pci_pbm_info *pbm = pcp->pbm;
851 struct resource *res, *root; 704 struct resource *res, *root;
852 u32 reg; 705 u32 reg;
853 int where, size, is_64bit; 706 int where, size, is_64bit;
@@ -1410,8 +1263,7 @@ static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
1410 struct pci_dev *pdev, 1263 struct pci_dev *pdev,
1411 struct msi_desc *entry) 1264 struct msi_desc *entry)
1412{ 1265{
1413 struct pcidev_cookie *pcp = pdev->sysdata; 1266 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1414 struct pci_pbm_info *pbm = pcp->pbm;
1415 unsigned long devino, msiqid; 1267 unsigned long devino, msiqid;
1416 struct msi_msg msg; 1268 struct msi_msg msg;
1417 int msi_num, err; 1269 int msi_num, err;
@@ -1455,7 +1307,7 @@ static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
1455 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID)) 1307 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
1456 goto out_err; 1308 goto out_err;
1457 1309
1458 pcp->msi_num = msi_num; 1310 pdev->dev.archdata.msi_num = msi_num;
1459 1311
1460 if (entry->msi_attrib.is_64) { 1312 if (entry->msi_attrib.is_64) {
1461 msg.address_hi = pbm->msi64_start >> 32; 1313 msg.address_hi = pbm->msi64_start >> 32;
@@ -1484,12 +1336,11 @@ out_err:
1484static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq, 1336static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
1485 struct pci_dev *pdev) 1337 struct pci_dev *pdev)
1486{ 1338{
1487 struct pcidev_cookie *pcp = pdev->sysdata; 1339 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1488 struct pci_pbm_info *pbm = pcp->pbm;
1489 unsigned long msiqid, err; 1340 unsigned long msiqid, err;
1490 unsigned int msi_num; 1341 unsigned int msi_num;
1491 1342
1492 msi_num = pcp->msi_num; 1343 msi_num = pdev->dev.archdata.msi_num;
1493 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid); 1344 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
1494 if (err) { 1345 if (err) {
1495 printk(KERN_ERR "%s: getmsiq gives error %lu\n", 1346 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
@@ -1559,8 +1410,6 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node
1559 pci_sun4v_get_bus_range(pbm); 1410 pci_sun4v_get_bus_range(pbm);
1560 pci_sun4v_iommu_init(pbm); 1411 pci_sun4v_iommu_init(pbm);
1561 pci_sun4v_msi_init(pbm); 1412 pci_sun4v_msi_init(pbm);
1562
1563 pdev_htab_populate(pbm);
1564} 1413}
1565 1414
1566void sun4v_pci_init(struct device_node *dp, char *model_name) 1415void sun4v_pci_init(struct device_node *dp, char *model_name)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 04:56:29 -0500