14 files changed, 330 insertions, 41 deletions

diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 17cf290dc2bc..9810fd881058 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -396,6 +396,7 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
                    , cpu_data(0).clock_tick
 #endif
                 );
+        cpucap_info(m);
 #ifdef CONFIG_SMP
         smp_bogo(m);
 #endif
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c
index dd1342c0a3be..490e5418740d 100644
--- a/arch/sparc/kernel/ds.c
+++ b/arch/sparc/kernel/ds.c
@@ -15,12 +15,15 @@
 #include <linux/reboot.h>
 #include <linux/cpu.h>
 
+#include <asm/hypervisor.h>
 #include <asm/ldc.h>
 #include <asm/vio.h>
 #include <asm/mdesc.h>
 #include <asm/head.h>
 #include <asm/irq.h>
 
+#include "kernel.h"
+
 #define DRV_MODULE_NAME         "ds"
 #define PFX DRV_MODULE_NAME     ": "
 #define DRV_MODULE_VERSION      "1.0"
@@ -828,18 +831,32 @@ void ldom_set_var(const char *var, const char *value)
         }
 }
 
+static char full_boot_str[256] __attribute__((aligned(32)));
+static int reboot_data_supported;
+
 void ldom_reboot(const char *boot_command)
 {
         /* Don't bother with any of this if the boot_command
          * is empty.
          */
         if (boot_command && strlen(boot_command)) {
-                char full_boot_str[256];
+                unsigned long len;
 
                 strcpy(full_boot_str, "boot ");
                 strcpy(full_boot_str + strlen("boot "), boot_command);
+                len = strlen(full_boot_str);
 
-                ldom_set_var("reboot-command", full_boot_str);
+                if (reboot_data_supported) {
+                        unsigned long ra = kimage_addr_to_ra(full_boot_str);
+                        unsigned long hv_ret;
+
+                        hv_ret = sun4v_reboot_data_set(ra, len);
+                        if (hv_ret != HV_EOK)
+                                pr_err("SUN4V: Unable to set reboot data "
+                                       "hv_ret=%lu\n", hv_ret);
+                } else {
+                        ldom_set_var("reboot-command", full_boot_str);
+                }
         }
         sun4v_mach_sir();
 }
@@ -1237,6 +1254,15 @@ static struct vio_driver ds_driver = {
 
 static int __init ds_init(void)
 {
+        unsigned long hv_ret, major, minor;
+
+        hv_ret = sun4v_get_version(HV_GRP_REBOOT_DATA, &major, &minor);
+        if (hv_ret == HV_EOK) {
+                pr_info("SUN4V: Reboot data supported (maj=%lu,min=%lu).\n",
+                        major, minor);
+                reboot_data_supported = 1;
+        }
+
         kthread_run(ds_thread, NULL, "kldomd");
 
         return vio_register_driver(&ds_driver);
diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h
index d1f1361c4167..e27f8ea8656e 100644
--- a/arch/sparc/kernel/entry.h
+++ b/arch/sparc/kernel/entry.h
@@ -42,6 +42,20 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
 extern void fpload(unsigned long *fpregs, unsigned long *fsr);
 
 #else /* CONFIG_SPARC32 */
+struct popc_3insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insns[3];
+};
+extern struct popc_3insn_patch_entry __popc_3insn_patch,
+        __popc_3insn_patch_end;
+
+struct popc_6insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insns[6];
+};
+extern struct popc_6insn_patch_entry __popc_6insn_patch,
+        __popc_6insn_patch_end;
+
 extern void __init per_cpu_patch(void);
 extern void __init sun4v_patch(void);
 extern void __init boot_cpu_id_too_large(int cpu);
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index c752603a7c0d..0eac1b2fc53d 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -559,7 +559,7 @@ niagara2_patch:
          nop
         call    niagara_patch_bzero
          nop
-        call    niagara2_patch_pageops
+        call    niagara_patch_pageops
          nop
 
         ba,a,pt %xcc, 80f
diff --git a/arch/sparc/kernel/hvapi.c b/arch/sparc/kernel/hvapi.c
index d306e648c33c..c2d055d8ba9e 100644
--- a/arch/sparc/kernel/hvapi.c
+++ b/arch/sparc/kernel/hvapi.c
@@ -28,11 +28,17 @@ static struct api_info api_table[] = {
         { .group = HV_GRP_CORE,         .flags = FLAG_PRE_API   },
         { .group = HV_GRP_INTR,                                 },
         { .group = HV_GRP_SOFT_STATE,                           },
+        { .group = HV_GRP_TM,                                   },
         { .group = HV_GRP_PCI,          .flags = FLAG_PRE_API   },
         { .group = HV_GRP_LDOM,                                 },
         { .group = HV_GRP_SVC_CHAN,     .flags = FLAG_PRE_API   },
         { .group = HV_GRP_NCS,          .flags = FLAG_PRE_API   },
         { .group = HV_GRP_RNG,                                  },
+        { .group = HV_GRP_PBOOT,                                },
+        { .group = HV_GRP_TPM,                                  },
+        { .group = HV_GRP_SDIO,                                 },
+        { .group = HV_GRP_SDIO_ERR,                             },
+        { .group = HV_GRP_REBOOT_DATA,                          },
         { .group = HV_GRP_NIAG_PERF,    .flags = FLAG_PRE_API   },
         { .group = HV_GRP_FIRE_PERF,                            },
         { .group = HV_GRP_N2_CPU,                               },
diff --git a/arch/sparc/kernel/hvcalls.S b/arch/sparc/kernel/hvcalls.S
index 8a5f35ffb15e..58d60de4d65b 100644
--- a/arch/sparc/kernel/hvcalls.S
+++ b/arch/sparc/kernel/hvcalls.S
@@ -798,3 +798,10 @@ ENTRY(sun4v_niagara2_setperf)
         retl
          nop
 ENDPROC(sun4v_niagara2_setperf)
+
+ENTRY(sun4v_reboot_data_set)
+        mov     HV_FAST_REBOOT_DATA_SET, %o5
+        ta      HV_FAST_TRAP
+        retl
+         nop
+ENDPROC(sun4v_reboot_data_set)
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 6f6544cfa0ef..fd6c36b1df74 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -4,12 +4,27 @@
 #include <linux/interrupt.h>
 
 #include <asm/traps.h>
+#include <asm/head.h>
+#include <asm/io.h>
 
 /* cpu.c */
 extern const char *sparc_pmu_type;
 extern unsigned int fsr_storage;
 extern int ncpus_probed;
 
+#ifdef CONFIG_SPARC64
+/* setup_64.c */
+struct seq_file;
+extern void cpucap_info(struct seq_file *);
+
+static inline unsigned long kimage_addr_to_ra(const char *p)
+{
+        unsigned long val = (unsigned long) p;
+
+        return kern_base + (val - KERNBASE);
+}
+#endif
+
 #ifdef CONFIG_SPARC32
 /* cpu.c */
 extern void cpu_probe(void);
diff --git a/arch/sparc/kernel/ktlb.S b/arch/sparc/kernel/ktlb.S
index 1d361477d7d6..79f310364849 100644
--- a/arch/sparc/kernel/ktlb.S
+++ b/arch/sparc/kernel/ktlb.S
@@ -47,16 +47,16 @@ kvmap_itlb_tsb_miss:
 kvmap_itlb_vmalloc_addr:
         KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
 
-        KTSB_LOCK_TAG(%g1, %g2, %g7)
+        TSB_LOCK_TAG(%g1, %g2, %g7)
 
         /* Load and check PTE.  */
         ldxa            [%g5] ASI_PHYS_USE_EC, %g5
         mov             1, %g7
         sllx            %g7, TSB_TAG_INVALID_BIT, %g7
         brgez,a,pn      %g5, kvmap_itlb_longpath
-         KTSB_STORE(%g1, %g7)
+         TSB_STORE(%g1, %g7)
 
-        KTSB_WRITE(%g1, %g5, %g6)
+        TSB_WRITE(%g1, %g5, %g6)
 
         /* fallthrough to TLB load */
 
@@ -102,9 +102,9 @@ kvmap_itlb_longpath:
 kvmap_itlb_obp:
         OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
 
-        KTSB_LOCK_TAG(%g1, %g2, %g7)
+        TSB_LOCK_TAG(%g1, %g2, %g7)
 
-        KTSB_WRITE(%g1, %g5, %g6)
+        TSB_WRITE(%g1, %g5, %g6)
 
         ba,pt           %xcc, kvmap_itlb_load
          nop
@@ -112,17 +112,17 @@ kvmap_itlb_obp:
 kvmap_dtlb_obp:
         OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
 
-        KTSB_LOCK_TAG(%g1, %g2, %g7)
+        TSB_LOCK_TAG(%g1, %g2, %g7)
 
-        KTSB_WRITE(%g1, %g5, %g6)
+        TSB_WRITE(%g1, %g5, %g6)
 
         ba,pt           %xcc, kvmap_dtlb_load
          nop
 
         .align          32
 kvmap_dtlb_tsb4m_load:
-        KTSB_LOCK_TAG(%g1, %g2, %g7)
-        KTSB_WRITE(%g1, %g5, %g6)
+        TSB_LOCK_TAG(%g1, %g2, %g7)
+        TSB_WRITE(%g1, %g5, %g6)
         ba,pt           %xcc, kvmap_dtlb_load
          nop
 
@@ -222,16 +222,16 @@ kvmap_linear_patch:
 kvmap_dtlb_vmalloc_addr:
         KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
 
-        KTSB_LOCK_TAG(%g1, %g2, %g7)
+        TSB_LOCK_TAG(%g1, %g2, %g7)
 
         /* Load and check PTE.  */
         ldxa            [%g5] ASI_PHYS_USE_EC, %g5
         mov             1, %g7
         sllx            %g7, TSB_TAG_INVALID_BIT, %g7
         brgez,a,pn      %g5, kvmap_dtlb_longpath
-         KTSB_STORE(%g1, %g7)
+         TSB_STORE(%g1, %g7)
 
-        KTSB_WRITE(%g1, %g5, %g6)
+        TSB_WRITE(%g1, %g5, %g6)
 
         /* fallthrough to TLB load */
 
diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c
index 42f28c7420e1..acaebb63c4fd 100644
--- a/arch/sparc/kernel/mdesc.c
+++ b/arch/sparc/kernel/mdesc.c
@@ -508,6 +508,8 @@ const char *mdesc_node_name(struct mdesc_handle *hp, u64 node)
 }
 EXPORT_SYMBOL(mdesc_node_name);
 
+static u64 max_cpus = 64;
+
 static void __init report_platform_properties(void)
 {
         struct mdesc_handle *hp = mdesc_grab();
@@ -543,8 +545,10 @@ static void __init report_platform_properties(void)
         if (v)
                 printk("PLATFORM: watchdog-max-timeout [%llu ms]\n", *v);
         v = mdesc_get_property(hp, pn, "max-cpus", NULL);
-        if (v)
-                printk("PLATFORM: max-cpus [%llu]\n", *v);
+        if (v) {
+                max_cpus = *v;
+                printk("PLATFORM: max-cpus [%llu]\n", max_cpus);
+        }
 
 #ifdef CONFIG_SMP
         {
@@ -715,7 +719,7 @@ static void __cpuinit set_proc_ids(struct mdesc_handle *hp)
 }
 
 static void __cpuinit get_one_mondo_bits(const u64 *p, unsigned int *mask,
-                                         unsigned char def)
+                                         unsigned long def, unsigned long max)
 {
         u64 val;
 
@@ -726,6 +730,9 @@ static void __cpuinit get_one_mondo_bits(const u64 *p, unsigned int *mask,
         if (!val || val >= 64)
                 goto use_default;
 
+        if (val > max)
+                val = max;
+
         *mask = ((1U << val) * 64U) - 1U;
         return;
 
@@ -736,19 +743,28 @@ use_default:
 static void __cpuinit get_mondo_data(struct mdesc_handle *hp, u64 mp,
                                      struct trap_per_cpu *tb)
 {
+        static int printed;
         const u64 *val;
 
         val = mdesc_get_property(hp, mp, "q-cpu-mondo-#bits", NULL);
-        get_one_mondo_bits(val, &tb->cpu_mondo_qmask, 7);
+        get_one_mondo_bits(val, &tb->cpu_mondo_qmask, 7, ilog2(max_cpus * 2));
 
         val = mdesc_get_property(hp, mp, "q-dev-mondo-#bits", NULL);
-        get_one_mondo_bits(val, &tb->dev_mondo_qmask, 7);
+        get_one_mondo_bits(val, &tb->dev_mondo_qmask, 7, 8);
 
         val = mdesc_get_property(hp, mp, "q-resumable-#bits", NULL);
-        get_one_mondo_bits(val, &tb->resum_qmask, 6);
+        get_one_mondo_bits(val, &tb->resum_qmask, 6, 7);
 
         val = mdesc_get_property(hp, mp, "q-nonresumable-#bits", NULL);
-        get_one_mondo_bits(val, &tb->nonresum_qmask, 2);
+        get_one_mondo_bits(val, &tb->nonresum_qmask, 2, 2);
+        if (!printed++) {
+                pr_info("SUN4V: Mondo queue sizes "
+                        "[cpu(%u) dev(%u) r(%u) nr(%u)]\n",
+                        tb->cpu_mondo_qmask + 1,
+                        tb->dev_mondo_qmask + 1,
+                        tb->resum_qmask + 1,
+                        tb->nonresum_qmask + 1);
+        }
 }
 
 static void * __cpuinit mdesc_iterate_over_cpus(void *(*func)(struct mdesc_handle *, u64, int, void *), void *arg, cpumask_t *mask)
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index c4dd0999da86..3e9daea1653d 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -29,6 +29,7 @@
 #include <linux/interrupt.h>
 #include <linux/cpu.h>
 #include <linux/initrd.h>
+#include <linux/module.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -46,6 +47,8 @@
 #include <asm/mmu.h>
 #include <asm/ns87303.h>
 #include <asm/btext.h>
+#include <asm/elf.h>
+#include <asm/mdesc.h>
 
 #ifdef CONFIG_IP_PNP
 #include <net/ipconfig.h>
@@ -269,6 +272,40 @@ void __init sun4v_patch(void)
         sun4v_hvapi_init();
 }
 
+static void __init popc_patch(void)
+{
+        struct popc_3insn_patch_entry *p3;
+        struct popc_6insn_patch_entry *p6;
+
+        p3 = &__popc_3insn_patch;
+        while (p3 < &__popc_3insn_patch_end) {
+                unsigned long i, addr = p3->addr;
+
+                for (i = 0; i < 3; i++) {
+                        *(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
+                        wmb();
+                        __asm__ __volatile__("flush     %0"
+                                             : : "r" (addr +  (i * 4)));
+                }
+
+                p3++;
+        }
+
+        p6 = &__popc_6insn_patch;
+        while (p6 < &__popc_6insn_patch_end) {
+                unsigned long i, addr = p6->addr;
+
+                for (i = 0; i < 6; i++) {
+                        *(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
+                        wmb();
+                        __asm__ __volatile__("flush     %0"
+                                             : : "r" (addr +  (i * 4)));
+                }
+
+                p6++;
+        }
+}
+
 #ifdef CONFIG_SMP
 void __init boot_cpu_id_too_large(int cpu)
 {
@@ -278,6 +315,154 @@ void __init boot_cpu_id_too_large(int cpu)
 }
 #endif
 
+/* On Ultra, we support all of the v8 capabilities. */
+unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
+                                   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
+                                   HWCAP_SPARC_V9);
+EXPORT_SYMBOL(sparc64_elf_hwcap);
+
+static const char *hwcaps[] = {
+        "flush", "stbar", "swap", "muldiv", "v9",
+        "ultra3", "blkinit", "n2",
+
+        /* These strings are as they appear in the machine description
+         * 'hwcap-list' property for cpu nodes.
+         */
+        "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
+        "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
+        "ima", "cspare",
+};
+
+void cpucap_info(struct seq_file *m)
+{
+        unsigned long caps = sparc64_elf_hwcap;
+        int i, printed = 0;
+
+        seq_puts(m, "cpucaps\t\t: ");
+        for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
+                unsigned long bit = 1UL << i;
+                if (caps & bit) {
+                        seq_printf(m, "%s%s",
+                                   printed ? "," : "", hwcaps[i]);
+                        printed++;
+                }
+        }
+        seq_putc(m, '\n');
+}
+
+static void __init report_hwcaps(unsigned long caps)
+{
+        int i, printed = 0;
+
+        printk(KERN_INFO "CPU CAPS: [");
+        for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
+                unsigned long bit = 1UL << i;
+                if (caps & bit) {
+                        printk(KERN_CONT "%s%s",
+                               printed ? "," : "", hwcaps[i]);
+                        if (++printed == 8) {
+                                printk(KERN_CONT "]\n");
+                                printk(KERN_INFO "CPU CAPS: [");
+                                printed = 0;
+                        }
+                }
+        }
+        printk(KERN_CONT "]\n");
+}
+
+static unsigned long __init mdesc_cpu_hwcap_list(void)
+{
+        struct mdesc_handle *hp;
+        unsigned long caps = 0;
+        const char *prop;
+        int len;
+        u64 pn;
+
+        hp = mdesc_grab();
+        if (!hp)
+                return 0;
+
+        pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
+        if (pn == MDESC_NODE_NULL)
+                goto out;
+
+        prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
+        if (!prop)
+                goto out;
+
+        while (len) {
+                int i, plen;
+
+                for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
+                        unsigned long bit = 1UL << i;
+
+                        if (!strcmp(prop, hwcaps[i])) {
+                                caps |= bit;
+                                break;
+                        }
+                }
+
+                plen = strlen(prop) + 1;
+                prop += plen;
+                len -= plen;
+        }
+
+out:
+        mdesc_release(hp);
+        return caps;
+}
+
+/* This yields a mask that user programs can use to figure out what
+ * instruction set this cpu supports.
+ */
+static void __init init_sparc64_elf_hwcap(void)
+{
+        unsigned long cap = sparc64_elf_hwcap;
+        unsigned long mdesc_caps;
+
+        if (tlb_type == cheetah || tlb_type == cheetah_plus)
+                cap |= HWCAP_SPARC_ULTRA3;
+        else if (tlb_type == hypervisor) {
+                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                        cap |= HWCAP_SPARC_BLKINIT;
+                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                        cap |= HWCAP_SPARC_N2;
+        }
+
+        cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
+
+        mdesc_caps = mdesc_cpu_hwcap_list();
+        if (!mdesc_caps) {
+                if (tlb_type == spitfire)
+                        cap |= AV_SPARC_VIS;
+                if (tlb_type == cheetah || tlb_type == cheetah_plus)
+                        cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
+                if (tlb_type == cheetah_plus)
+                        cap |= AV_SPARC_POPC;
+                if (tlb_type == hypervisor) {
+                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
+                                cap |= AV_SPARC_ASI_BLK_INIT;
+                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
+                            sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                                cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
+                                        AV_SPARC_ASI_BLK_INIT |
+                                        AV_SPARC_POPC);
+                        if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
+                                cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
+                                        AV_SPARC_FMAF);
+                }
+        }
+        sparc64_elf_hwcap = cap | mdesc_caps;
+
+        report_hwcaps(sparc64_elf_hwcap);
+
+        if (sparc64_elf_hwcap & AV_SPARC_POPC)
+                popc_patch();
+}
+
 void __init setup_arch(char **cmdline_p)
 {
         /* Initialize PROM console and command line. */
@@ -337,6 +522,7 @@ void __init setup_arch(char **cmdline_p)
         init_cur_cpu_trap(current_thread_info());
 
         paging_init();
+        init_sparc64_elf_hwcap();
 }
 
 extern int stop_a_enabled;
diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c
index 372ad59c4cba..83b47ab02d96 100644
--- a/arch/sparc/kernel/sparc_ksyms_64.c
+++ b/arch/sparc/kernel/sparc_ksyms_64.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/bitops.h>
 
 #include <asm/system.h>
 #include <asm/cpudata.h>
@@ -38,5 +39,15 @@ EXPORT_SYMBOL(sun4v_niagara_setperf);
 EXPORT_SYMBOL(sun4v_niagara2_getperf);
 EXPORT_SYMBOL(sun4v_niagara2_setperf);
 
+/* from hweight.S */
+EXPORT_SYMBOL(__arch_hweight8);
+EXPORT_SYMBOL(__arch_hweight16);
+EXPORT_SYMBOL(__arch_hweight32);
+EXPORT_SYMBOL(__arch_hweight64);
+
+/* from ffs_ffz.S */
+EXPORT_SYMBOL(ffs);
+EXPORT_SYMBOL(__ffs);
+
 /* Exporting a symbol from /init/main.c */
 EXPORT_SYMBOL(saved_command_line);
diff --git a/arch/sparc/kernel/sstate.c b/arch/sparc/kernel/sstate.c
index 8cdbe5946b43..c59af546f522 100644
--- a/arch/sparc/kernel/sstate.c
+++ b/arch/sparc/kernel/sstate.c
@@ -14,14 +14,9 @@
 #include <asm/head.h>
 #include <asm/io.h>
 
-static int hv_supports_soft_state;
-
-static unsigned long kimage_addr_to_ra(const char *p)
-{
-        unsigned long val = (unsigned long) p;
+#include "kernel.h"
 
-        return kern_base + (val - KERNBASE);
-}
+static int hv_supports_soft_state;
 
 static void do_set_sstate(unsigned long state, const char *msg)
 {
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index 35cff1673aa4..76e4ac1a13e1 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -22,6 +22,7 @@
 #include <linux/bitops.h>
 #include <linux/perf_event.h>
 #include <linux/ratelimit.h>
+#include <linux/bitops.h>
 #include <asm/fpumacro.h>
 
 enum direction {
@@ -373,16 +374,11 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
         }
 }
 
-static char popc_helper[] = {
-0, 1, 1, 2, 1, 2, 2, 3,
-1, 2, 2, 3, 2, 3, 3, 4, 
-};
-
 int handle_popc(u32 insn, struct pt_regs *regs)
 {
-        u64 value;
-        int ret, i, rd = ((insn >> 25) & 0x1f);
         int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
+        int ret, rd = ((insn >> 25) & 0x1f);
+        u64 value;
                                 
         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
         if (insn & 0x2000) {
@@ -392,10 +388,7 @@ int handle_popc(u32 insn, struct pt_regs *regs)
                 maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
                 value = fetch_reg(insn & 0x1f, regs);
         }
-        for (ret = 0, i = 0; i < 16; i++) {
-                ret += popc_helper[value & 0xf];
-                value >>= 4;
-        }
+        ret = hweight64(value);
         if (rd < 16) {
                 if (rd)
                         regs->u_regs[rd] = ret;
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index c0220759003e..0e1605697b49 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -107,7 +107,26 @@ SECTIONS
                 *(.sun4v_2insn_patch)
                 __sun4v_2insn_patch_end = .;
         }
-
+        .swapper_tsb_phys_patch : {
+                __swapper_tsb_phys_patch = .;
+                *(.swapper_tsb_phys_patch)
+                __swapper_tsb_phys_patch_end = .;
+        }
+        .swapper_4m_tsb_phys_patch : {
+                __swapper_4m_tsb_phys_patch = .;
+                *(.swapper_4m_tsb_phys_patch)
+                __swapper_4m_tsb_phys_patch_end = .;
+        }
+        .popc_3insn_patch : {
+                __popc_3insn_patch = .;
+                *(.popc_3insn_patch)
+                __popc_3insn_patch_end = .;
+        }
+        .popc_6insn_patch : {
+                __popc_6insn_patch = .;
+                *(.popc_6insn_patch)
+                __popc_6insn_patch_end = .;
+        }
         PERCPU_SECTION(SMP_CACHE_BYTES)
 
         . = ALIGN(PAGE_SIZE);