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-rw-r--r--arch/sparc/kernel/sun4c_irq.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c
index 009e891a4329..c6ac9fc52563 100644
--- a/arch/sparc/kernel/sun4c_irq.c
+++ b/arch/sparc/kernel/sun4c_irq.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include "irq.h"
21 22
22#include <asm/ptrace.h> 23#include <asm/ptrace.h>
23#include <asm/processor.h> 24#include <asm/processor.h>
@@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" };
40static struct resource sun4c_intr_eb = { "sun4c_intr" }; 41static struct resource sun4c_intr_eb = { "sun4c_intr" };
41#endif 42#endif
42 43
44/*
45 * Bit field defines for the interrupt registers on various
46 * Sparc machines.
47 */
48
49/* The sun4c interrupt register. */
50#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
51#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
52#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
53#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
54#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
55#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
56#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
57
43/* Pointer to the interrupt enable byte 58/* Pointer to the interrupt enable byte
44 * 59 *
45 * Dave Redman (djhr@tadpole.co.uk) 60 * Dave Redman (djhr@tadpole.co.uk)