1 files changed, 51 insertions, 1 deletions

diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index aa594c792d19..0d810c2f1d00 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -132,6 +132,8 @@ prom_sun4v_name:
         .asciz  "sun4v"
 prom_niagara_prefix:
         .asciz  "SUNW,UltraSPARC-T"
+prom_sparc_prefix:
+        .asciz  "SPARC-"
         .align  4
 prom_root_compatible:
         .skip   64
@@ -382,6 +384,22 @@ sun4v_chip_type:
 90:     ldub    [%g7], %g2
         ldub    [%g1], %g4
         cmp     %g2, %g4
+        bne,pn  %icc, 89f
+         add    %g7, 1, %g7
+        subcc   %g3, 1, %g3
+        bne,pt  %xcc, 90b
+         add    %g1, 1, %g1
+        ba,pt   %xcc, 91f
+         nop
+
+89:     sethi   %hi(prom_cpu_compatible), %g1
+        or      %g1, %lo(prom_cpu_compatible), %g1
+        sethi   %hi(prom_sparc_prefix), %g7
+        or      %g7, %lo(prom_sparc_prefix), %g7
+        mov     6, %g3
+90:     ldub    [%g7], %g2
+        ldub    [%g1], %g4
+        cmp     %g2, %g4
         bne,pn  %icc, 4f
          add    %g7, 1, %g7
         subcc   %g3, 1, %g3
@@ -390,6 +408,28 @@ sun4v_chip_type:
 
         sethi   %hi(prom_cpu_compatible), %g1
         or      %g1, %lo(prom_cpu_compatible), %g1
+        ldub    [%g1 + 6], %g2
+        cmp     %g2, 'T'
+        be,pt   %xcc, 70f
+         cmp    %g2, 'M'
+        bne,pn  %xcc, 4f
+         nop
+
+70:     ldub    [%g1 + 7], %g2
+        cmp     %g2, '3'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA3, %g4
+        cmp     %g2, '4'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA4, %g4
+        cmp     %g2, '5'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA5, %g4
+        ba,pt   %xcc, 4f
+         nop
+
+91:     sethi   %hi(prom_cpu_compatible), %g1
+        or      %g1, %lo(prom_cpu_compatible), %g1
         ldub    [%g1 + 17], %g2
         cmp     %g2, '1'
         be,pt   %xcc, 5f
@@ -397,6 +437,7 @@ sun4v_chip_type:
         cmp     %g2, '2'
         be,pt   %xcc, 5f
          mov    SUN4V_CHIP_NIAGARA2, %g4
+        
 4:
         mov     SUN4V_CHIP_UNKNOWN, %g4
 5:      sethi   %hi(sun4v_chip_type), %g2
@@ -514,6 +555,15 @@ niagara_tlb_fixup:
          cmp    %g1, SUN4V_CHIP_NIAGARA2
         be,pt   %xcc, niagara2_patch
          nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA3
+        be,pt   %xcc, niagara2_patch
+         nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA4
+        be,pt   %xcc, niagara2_patch
+         nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA5
+        be,pt   %xcc, niagara2_patch
+         nop
 
         call    generic_patch_copyops
          nop
@@ -528,7 +578,7 @@ niagara2_patch:
          nop
         call    niagara_patch_bzero
          nop
-        call    niagara2_patch_pageops
+        call    niagara_patch_pageops
          nop
 
         ba,a,pt %xcc, 80f