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-rw-r--r--arch/sparc/include/asm/system_32.h288
1 files changed, 288 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
new file mode 100644
index 000000000000..b4b024445fc9
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+++ b/arch/sparc/include/asm/system_32.h
@@ -0,0 +1,288 @@
1#ifndef __SPARC_SYSTEM_H
2#define __SPARC_SYSTEM_H
3
4#include <linux/kernel.h>
5#include <linux/threads.h> /* NR_CPUS */
6#include <linux/thread_info.h>
7
8#include <asm/page.h>
9#include <asm/psr.h>
10#include <asm/ptrace.h>
11#include <asm/btfixup.h>
12#include <asm/smp.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/irqflags.h>
17
18/*
19 * Sparc (general) CPU types
20 */
21enum sparc_cpu {
22 sun4 = 0x00,
23 sun4c = 0x01,
24 sun4m = 0x02,
25 sun4d = 0x03,
26 sun4e = 0x04,
27 sun4u = 0x05, /* V8 ploos ploos */
28 sun_unknown = 0x06,
29 ap1000 = 0x07, /* almost a sun4m */
30};
31
32/* Really, userland should not be looking at any of this... */
33#ifdef __KERNEL__
34
35extern enum sparc_cpu sparc_cpu_model;
36
37#ifndef CONFIG_SUN4
38#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
39#define ARCH_SUN4 0
40#else
41#define ARCH_SUN4C_SUN4 1
42#define ARCH_SUN4 1
43#endif
44
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46
47extern char reboot_command[];
48
49extern struct thread_info *current_set[NR_CPUS];
50
51extern unsigned long empty_bad_page;
52extern unsigned long empty_bad_page_table;
53extern unsigned long empty_zero_page;
54
55extern void sun_do_break(void);
56extern int serial_console;
57extern int stop_a_enabled;
58
59static inline int con_is_present(void)
60{
61 return serial_console ? 0 : 1;
62}
63
64/* When a context switch happens we must flush all user windows so that
65 * the windows of the current process are flushed onto its stack. This
66 * way the windows are all clean for the next process and the stack
67 * frames are up to date.
68 */
69extern void flush_user_windows(void);
70extern void kill_user_windows(void);
71extern void synchronize_user_stack(void);
72extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
73 void *fpqueue, unsigned long *fpqdepth);
74
75#ifdef CONFIG_SMP
76#define SWITCH_ENTER(prv) \
77 do { \
78 if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
79 put_psr(get_psr() | PSR_EF); \
80 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
81 &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
82 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
83 (prv)->thread.kregs->psr &= ~PSR_EF; \
84 } \
85 } while(0)
86
87#define SWITCH_DO_LAZY_FPU(next) /* */
88#else
89#define SWITCH_ENTER(prv) /* */
90#define SWITCH_DO_LAZY_FPU(nxt) \
91 do { \
92 if (last_task_used_math != (nxt)) \
93 (nxt)->thread.kregs->psr&=~PSR_EF; \
94 } while(0)
95#endif
96
97extern void flushw_all(void);
98
99/*
100 * Flush windows so that the VM switch which follows
101 * would not pull the stack from under us.
102 *
103 * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
104 * XXX WTF is the above comment? Found in late teen 2.4.x.
105 */
106#define prepare_arch_switch(next) do { \
107 __asm__ __volatile__( \
108 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
109 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
110 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
111 "save %sp, -0x40, %sp\n\t" \
112 "restore; restore; restore; restore; restore; restore; restore"); \
113} while(0)
114
115 /* Much care has gone into this code, do not touch it.
116 *
117 * We need to loadup regs l0/l1 for the newly forked child
118 * case because the trap return path relies on those registers
119 * holding certain values, gcc is told that they are clobbered.
120 * Gcc needs registers for 3 values in and 1 value out, so we
121 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
122 *
123 * Hey Dave, that do not touch sign is too much of an incentive
124 * - Anton & Pete
125 */
126#define switch_to(prev, next, last) do { \
127 SWITCH_ENTER(prev); \
128 SWITCH_DO_LAZY_FPU(next); \
129 cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
130 __asm__ __volatile__( \
131 "sethi %%hi(here - 0x8), %%o7\n\t" \
132 "mov %%g6, %%g3\n\t" \
133 "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
134 "rd %%psr, %%g4\n\t" \
135 "std %%sp, [%%g6 + %4]\n\t" \
136 "rd %%wim, %%g5\n\t" \
137 "wr %%g4, 0x20, %%psr\n\t" \
138 "nop\n\t" \
139 "std %%g4, [%%g6 + %3]\n\t" \
140 "ldd [%2 + %3], %%g4\n\t" \
141 "mov %2, %%g6\n\t" \
142 ".globl patchme_store_new_current\n" \
143"patchme_store_new_current:\n\t" \
144 "st %2, [%1]\n\t" \
145 "wr %%g4, 0x20, %%psr\n\t" \
146 "nop\n\t" \
147 "nop\n\t" \
148 "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
149 "ldd [%%g6 + %4], %%sp\n\t" \
150 "wr %%g5, 0x0, %%wim\n\t" \
151 "ldd [%%sp + 0x00], %%l0\n\t" \
152 "ldd [%%sp + 0x38], %%i6\n\t" \
153 "wr %%g4, 0x0, %%psr\n\t" \
154 "nop\n\t" \
155 "nop\n\t" \
156 "jmpl %%o7 + 0x8, %%g0\n\t" \
157 " ld [%%g3 + %5], %0\n\t" \
158 "here:\n" \
159 : "=&r" (last) \
160 : "r" (&(current_set[hard_smp_processor_id()])), \
161 "r" (task_thread_info(next)), \
162 "i" (TI_KPSR), \
163 "i" (TI_KSP), \
164 "i" (TI_TASK) \
165 : "g1", "g2", "g3", "g4", "g5", "g7", \
166 "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
167 "i0", "i1", "i2", "i3", "i4", "i5", \
168 "o0", "o1", "o2", "o3", "o7"); \
169 } while(0)
170
171/* XXX Change this if we ever use a PSO mode kernel. */
172#define mb() __asm__ __volatile__ ("" : : : "memory")
173#define rmb() mb()
174#define wmb() mb()
175#define read_barrier_depends() do { } while(0)
176#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
177#define smp_mb() __asm__ __volatile__("":::"memory")
178#define smp_rmb() __asm__ __volatile__("":::"memory")
179#define smp_wmb() __asm__ __volatile__("":::"memory")
180#define smp_read_barrier_depends() do { } while(0)
181
182#define nop() __asm__ __volatile__ ("nop")
183
184/* This has special calling conventions */
185#ifndef CONFIG_SMP
186BTFIXUPDEF_CALL(void, ___xchg32, void)
187#endif
188
189static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
190{
191#ifdef CONFIG_SMP
192 __asm__ __volatile__("swap [%2], %0"
193 : "=&r" (val)
194 : "0" (val), "r" (m)
195 : "memory");
196 return val;
197#else
198 register unsigned long *ptr asm("g1");
199 register unsigned long ret asm("g2");
200
201 ptr = (unsigned long *) m;
202 ret = val;
203
204 /* Note: this is magic and the nop there is
205 really needed. */
206 __asm__ __volatile__(
207 "mov %%o7, %%g4\n\t"
208 "call ___f____xchg32\n\t"
209 " nop\n\t"
210 : "=&r" (ret)
211 : "0" (ret), "r" (ptr)
212 : "g3", "g4", "g7", "memory", "cc");
213
214 return ret;
215#endif
216}
217
218#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
219
220extern void __xchg_called_with_bad_pointer(void);
221
222static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
223{
224 switch (size) {
225 case 4:
226 return xchg_u32(ptr, x);
227 };
228 __xchg_called_with_bad_pointer();
229 return x;
230}
231
232/* Emulate cmpxchg() the same way we emulate atomics,
233 * by hashing the object address and indexing into an array
234 * of spinlocks to get a bit of performance...
235 *
236 * See arch/sparc/lib/atomic32.c for implementation.
237 *
238 * Cribbed from <asm-parisc/atomic.h>
239 */
240#define __HAVE_ARCH_CMPXCHG 1
241
242/* bug catcher for when unsupported size is used - won't link */
243extern void __cmpxchg_called_with_bad_pointer(void);
244/* we only need to support cmpxchg of a u32 on sparc */
245extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
246
247/* don't worry...optimizer will get rid of most of this */
248static inline unsigned long
249__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
250{
251 switch (size) {
252 case 4:
253 return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
254 default:
255 __cmpxchg_called_with_bad_pointer();
256 break;
257 }
258 return old;
259}
260
261#define cmpxchg(ptr, o, n) \
262({ \
263 __typeof__(*(ptr)) _o_ = (o); \
264 __typeof__(*(ptr)) _n_ = (n); \
265 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
266 (unsigned long)_n_, sizeof(*(ptr))); \
267})
268
269#include <asm-generic/cmpxchg-local.h>
270
271/*
272 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
273 * them available.
274 */
275#define cmpxchg_local(ptr, o, n) \
276 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
277 (unsigned long)(n), sizeof(*(ptr))))
278#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
279
280extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
281
282#endif /* __KERNEL__ */
283
284#endif /* __ASSEMBLY__ */
285
286#define arch_align_stack(x) (x)
287
288#endif /* !(__SPARC_SYSTEM_H) */
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