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-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c255
-rw-r--r--arch/sh/mm/Kconfig2
2 files changed, 223 insertions, 34 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index cf047562e43f..c49fcb0800cc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -72,46 +72,235 @@ static int __init sh7785_devices_setup(void)
72} 72}
73__initcall(sh7785_devices_setup); 73__initcall(sh7785_devices_setup);
74 74
75static struct intc2_data intc2_irq_table[] = { 75enum {
76 { 28, 0, 24, 0, 0, 2 }, /* TMU0 */ 76 UNUSED = 0,
77 77
78 { 40, 8, 24, 0, 2, 3 }, /* SCIF0 ERI */ 78 /* interrupt sources */
79 { 41, 8, 24, 0, 2, 3 }, /* SCIF0 RXI */ 79
80 { 42, 8, 24, 0, 2, 3 }, /* SCIF0 BRI */ 80 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
81 { 43, 8, 24, 0, 2, 3 }, /* SCIF0 TXI */ 81 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
82 82 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
83 { 44, 8, 16, 0, 3, 3 }, /* SCIF1 ERI */ 83 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
84 { 45, 8, 16, 0, 3, 3 }, /* SCIF1 RXI */ 84
85 { 46, 8, 16, 0, 3, 3 }, /* SCIF1 BRI */ 85 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
86 { 47, 8, 16, 0, 3, 3 }, /* SCIF1 TXI */ 86 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
87 87 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
88 { 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */ 88 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
89 { 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */ 89
90 { 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */ 90 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
91 { 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */ 91 WDT,
92 { 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */ 92 TMU0, TMU1, TMU2, TMU2_TICPI,
93 93 HUDI,
94 { 60, 8, 8, 0, 4, 3 }, /* SCIF2 ERI, RXI, BRI, TXI */ 94 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
95 { 60, 8, 0, 0, 5, 3 }, /* SCIF3 ERI, RXI, BRI, TXI */ 95 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
96 { 60, 12, 24, 0, 6, 3 }, /* SCIF4 ERI, RXI, BRI, TXI */ 96 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
97 { 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */ 97 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
98 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
99 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
100 HSPI,
101 SCIF2, SCIF3, SCIF4, SCIF5,
102 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
103 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
104 SIOF,
105 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
106 DU,
107 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
108 TMU3, TMU4, TMU5,
109 SSI0, SSI1,
110 HAC0, HAC1,
111 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
112 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
113
114 /* interrupt groups */
115
116 TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
117 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
98}; 118};
99 119
100static struct intc2_desc intc2_irq_desc __read_mostly = { 120static struct intc_vect vectors[] = {
101 .prio_base = 0xffd40000, 121 INTC_VECT(WDT, 0x560),
102 .msk_base = 0xffd40038, 122 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
103 .mskclr_base = 0xffd4003c, 123 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
124 INTC_VECT(HUDI, 0x600),
125 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
126 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
127 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
128 INTC_VECT(DMAC0_DMAE, 0x6e0),
129 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
130 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
131 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
132 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
133 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
134 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
135 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
136 INTC_VECT(DMAC1_DMAE, 0x940),
137 INTC_VECT(HSPI, 0x960),
138 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
139 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
140 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
141 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
142 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
143 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
144 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
145 INTC_VECT(SIOF, 0xc00),
146 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
147 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
148 INTC_VECT(DU, 0xd80),
149 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
150 INTC_VECT(GDTA_GAERI, 0xde0),
151 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
152 INTC_VECT(TMU5, 0xe40),
153 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
154 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
155 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
156 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
157 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
158 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
159};
104 160
105 .intc2_data = intc2_irq_table, 161static struct intc_group groups[] = {
106 .nr_irqs = ARRAY_SIZE(intc2_irq_table), 162 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
163 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
164 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
165 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
166 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
167 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
168 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
169 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
170 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
171 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
172 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
173 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
174 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
175 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
176};
107 177
108 .chip = { 178static struct intc_prio priorities[] = {
109 .name = "INTC2-sh7785", 179 INTC_PRIO(SCIF0, 3),
110 }, 180 INTC_PRIO(SCIF1, 3),
181 INTC_PRIO(SCIF2, 3),
182 INTC_PRIO(SCIF3, 3),
183 INTC_PRIO(SCIF4, 3),
184 INTC_PRIO(SCIF5, 3),
185};
186
187static struct intc_mask_reg mask_registers[] = {
188 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
189 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
190
191 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
192 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
193 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
194 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
195 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
196 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
197 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
198 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
199 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
200
201 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
202 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
203 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
204 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
205 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
206};
207
208static struct intc_prio_reg prio_registers[] = {
209 { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
210 IRQ4, IRQ5, IRQ6, IRQ7 } },
211 { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
212 { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
213 { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
214 { 0xffd4000c, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
215 { 0xffd40010, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
216 { 0xffd40014, 32, 8, /* INT2PRI5 */ { HAC0, HAC1, PCISERR, PCIINTA } },
217 { 0xffd40018, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
218 PCIINTD, PCIC5 } },
219 { 0xffd4001c, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
220 { 0xffd40020, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
221 { 0xffd40024, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
222};
223
224static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
225 mask_registers, prio_registers, NULL);
226
227
228/* Support for external interrupt pins in IRQ mode */
229
230static struct intc_vect vectors_irq0123[] = {
231 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
232 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
233};
234
235static struct intc_vect vectors_irq4567[] = {
236 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
237 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
238};
239
240static struct intc_sense_reg sense_registers[] = {
241 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
242 IRQ4, IRQ5, IRQ6, IRQ7 } },
243};
244
245static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
246 NULL, NULL, mask_registers, prio_registers,
247 sense_registers);
248
249static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
250 NULL, NULL, mask_registers, prio_registers,
251 sense_registers);
252
253/* External interrupt pins in IRL mode */
254
255static struct intc_vect vectors_irl0123[] = {
256 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
257 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
258 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
259 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
260 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
261 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
262 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
263 INTC_VECT(IRL0_HHHL, 0x3c0),
111}; 264};
112 265
266static struct intc_vect vectors_irl4567[] = {
267 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
268 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
269 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
270 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
271 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
272 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
273 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
274 INTC_VECT(IRL4_HHHL, 0xcc0),
275};
276
277static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
278 NULL, NULL, mask_registers, NULL, NULL);
279
280static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
281 NULL, NULL, mask_registers, NULL, NULL);
282
113void __init plat_irq_setup(void) 283void __init plat_irq_setup(void)
114{ 284{
115 register_intc2_controller(&intc2_irq_desc); 285 register_intc_controller(&intc_desc);
116} 286}
117 287
288void __init plat_irq_setup_pins(int mode)
289{
290 switch (mode) {
291 case IRQ_MODE_IRQ7654:
292 register_intc_controller(&intc_desc_irq4567);
293 break;
294 case IRQ_MODE_IRQ3210:
295 register_intc_controller(&intc_desc_irq0123);
296 break;
297 case IRQ_MODE_IRL7654:
298 register_intc_controller(&intc_desc_irl4567);
299 break;
300 case IRQ_MODE_IRL3210:
301 register_intc_controller(&intc_desc_irl0123);
302 break;
303 default:
304 BUG();
305 }
306}
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index c2777555003e..99aebecc5701 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -192,7 +192,7 @@ config CPU_SUBTYPE_SH7785
192 bool "Support SH7785 processor" 192 bool "Support SH7785 processor"
193 select CPU_SH4A 193 select CPU_SH4A
194 select CPU_SHX2 194 select CPU_SHX2
195 select CPU_HAS_INTC2_IRQ 195 select CPU_HAS_INTC_IRQ
196 196
197config CPU_SUBTYPE_SHX3 197config CPU_SUBTYPE_SHX3
198 bool "Support SH-X3 processor" 198 bool "Support SH-X3 processor"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 10:10:50 -0500