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-rw-r--r--arch/sh/kernel/Makefile16
-rw-r--r--arch/sh/kernel/clkdev.c169
-rw-r--r--arch/sh/kernel/cpu/Makefile4
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c4
-rw-r--r--arch/sh/kernel/cpu/clock.c16
-rw-r--r--arch/sh/kernel/cpu/init.c2
-rw-r--r--arch/sh/kernel/cpu/irq/imask.c18
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c51
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c35
-rw-r--r--arch/sh/kernel/cpu/proc.c148
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c22
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c20
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c21
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c20
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c16
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c5
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c7
-rw-r--r--arch/sh/kernel/cpu/sh4/perf_event.c4
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c8
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c41
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c8
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c1
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c52
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c206
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c227
-rw-r--r--arch/sh/kernel/cpu/sh4a/intc-shx3.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c1582
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-shx3.c587
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c33
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c26
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c16
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c122
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c844
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c175
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c48
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c7
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c39
-rw-r--r--arch/sh/kernel/crash_dump.c22
-rw-r--r--arch/sh/kernel/dumpstack.c15
-rw-r--r--arch/sh/kernel/head_32.S2
-rw-r--r--arch/sh/kernel/io_generic.c180
-rw-r--r--arch/sh/kernel/io_trapped.c2
-rw-r--r--arch/sh/kernel/iomap.c165
-rw-r--r--arch/sh/kernel/ioport.c43
-rw-r--r--arch/sh/kernel/irq.c98
-rw-r--r--arch/sh/kernel/irq_32.c12
-rw-r--r--arch/sh/kernel/irq_64.c16
-rw-r--r--arch/sh/kernel/kdebugfs.c16
-rw-r--r--arch/sh/kernel/kprobes.c100
-rw-r--r--arch/sh/kernel/machvec.c22
-rw-r--r--arch/sh/kernel/module.c2
-rw-r--r--arch/sh/kernel/perf_callchain.c62
-rw-r--r--arch/sh/kernel/perf_event.c159
-rw-r--r--arch/sh/kernel/process.c18
-rw-r--r--arch/sh/kernel/process_32.c3
-rw-r--r--arch/sh/kernel/ptrace.c33
-rw-r--r--arch/sh/kernel/ptrace_32.c84
-rw-r--r--arch/sh/kernel/ptrace_64.c119
-rw-r--r--arch/sh/kernel/reboot.c4
-rw-r--r--arch/sh/kernel/setup.c168
-rw-r--r--arch/sh/kernel/smp.c2
-rw-r--r--arch/sh/kernel/stacktrace.c13
-rw-r--r--arch/sh/kernel/sys_sh.c2
-rw-r--r--arch/sh/kernel/syscalls_32.S29
-rw-r--r--arch/sh/kernel/syscalls_64.S9
-rw-r--r--arch/sh/kernel/topology.c1
-rw-r--r--arch/sh/kernel/traps_32.c30
-rw-r--r--arch/sh/kernel/traps_64.c11
-rw-r--r--arch/sh/kernel/vmlinux.lds.S2
-rw-r--r--arch/sh/kernel/vsyscall/vsyscall-trapa.S2
-rw-r--r--arch/sh/kernel/vsyscall/vsyscall.c6
96 files changed, 4151 insertions, 2088 deletions
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index e25f3c69525d..77f7ae1d4647 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -11,15 +11,20 @@ endif
11 11
12CFLAGS_REMOVE_return_address.o = -pg 12CFLAGS_REMOVE_return_address.o = -pg
13 13
14obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ 14obj-y := debugtraps.o dma-nommu.o dumpstack.o \
15 idle.o io.o irq.o \ 15 idle.o io.o irq.o irq_$(BITS).o kdebugfs.o \
16 irq_$(BITS).o machvec.o nmi_debug.o process.o \ 16 machvec.o nmi_debug.o process.o \
17 process_$(BITS).o ptrace_$(BITS).o \ 17 process_$(BITS).o ptrace.o ptrace_$(BITS).o \
18 reboot.o return_address.o \ 18 reboot.o return_address.o \
19 setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \ 19 setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \
20 syscalls_$(BITS).o time.o topology.o traps.o \ 20 syscalls_$(BITS).o time.o topology.o traps.o \
21 traps_$(BITS).o unwinder.o 21 traps_$(BITS).o unwinder.o
22 22
23ifndef CONFIG_GENERIC_IOMAP
24obj-y += iomap.o
25obj-$(CONFIG_HAS_IOPORT) += ioport.o
26endif
27
23obj-y += cpu/ 28obj-y += cpu/
24obj-$(CONFIG_VSYSCALL) += vsyscall/ 29obj-$(CONFIG_VSYSCALL) += vsyscall/
25obj-$(CONFIG_SMP) += smp.o 30obj-$(CONFIG_SMP) += smp.o
@@ -39,9 +44,8 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
39obj-$(CONFIG_HIBERNATION) += swsusp.o 44obj-$(CONFIG_HIBERNATION) += swsusp.o
40obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o 45obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
41obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o 46obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
42obj-$(CONFIG_HAS_IOPORT) += io_generic.o
43 47
44obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o 48obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
45obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o 49obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
46 50
47EXTRA_CFLAGS += -Werror 51ccflags-y := -Werror
diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c
deleted file mode 100644
index befc255830a4..000000000000
--- a/arch/sh/kernel/clkdev.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * arch/sh/kernel/clkdev.c
3 *
4 * Cloned from arch/arm/common/clkdev.c:
5 *
6 * Copyright (C) 2008 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Helper for the clk API to assist looking up a struct clk.
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/device.h>
17#include <linux/list.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/string.h>
21#include <linux/mutex.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/bootmem.h>
25#include <linux/mm.h>
26#include <asm/clock.h>
27#include <asm/clkdev.h>
28
29static LIST_HEAD(clocks);
30static DEFINE_MUTEX(clocks_mutex);
31
32/*
33 * Find the correct struct clk for the device and connection ID.
34 * We do slightly fuzzy matching here:
35 * An entry with a NULL ID is assumed to be a wildcard.
36 * If an entry has a device ID, it must match
37 * If an entry has a connection ID, it must match
38 * Then we take the most specific entry - with the following
39 * order of precedence: dev+con > dev only > con only.
40 */
41static struct clk *clk_find(const char *dev_id, const char *con_id)
42{
43 struct clk_lookup *p;
44 struct clk *clk = NULL;
45 int match, best = 0;
46
47 list_for_each_entry(p, &clocks, node) {
48 match = 0;
49 if (p->dev_id) {
50 if (!dev_id || strcmp(p->dev_id, dev_id))
51 continue;
52 match += 2;
53 }
54 if (p->con_id) {
55 if (!con_id || strcmp(p->con_id, con_id))
56 continue;
57 match += 1;
58 }
59 if (match == 0)
60 continue;
61
62 if (match > best) {
63 clk = p->clk;
64 best = match;
65 }
66 }
67 return clk;
68}
69
70struct clk *clk_get_sys(const char *dev_id, const char *con_id)
71{
72 struct clk *clk;
73
74 mutex_lock(&clocks_mutex);
75 clk = clk_find(dev_id, con_id);
76 mutex_unlock(&clocks_mutex);
77
78 return clk ? clk : ERR_PTR(-ENOENT);
79}
80EXPORT_SYMBOL(clk_get_sys);
81
82void clkdev_add(struct clk_lookup *cl)
83{
84 mutex_lock(&clocks_mutex);
85 list_add_tail(&cl->node, &clocks);
86 mutex_unlock(&clocks_mutex);
87}
88EXPORT_SYMBOL(clkdev_add);
89
90void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
91{
92 mutex_lock(&clocks_mutex);
93 while (num--) {
94 list_add_tail(&cl->node, &clocks);
95 cl++;
96 }
97 mutex_unlock(&clocks_mutex);
98}
99
100#define MAX_DEV_ID 20
101#define MAX_CON_ID 16
102
103struct clk_lookup_alloc {
104 struct clk_lookup cl;
105 char dev_id[MAX_DEV_ID];
106 char con_id[MAX_CON_ID];
107};
108
109struct clk_lookup * __init_refok
110clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
111{
112 struct clk_lookup_alloc *cla;
113
114 if (!slab_is_available())
115 cla = alloc_bootmem_low_pages(sizeof(*cla));
116 else
117 cla = kzalloc(sizeof(*cla), GFP_KERNEL);
118
119 if (!cla)
120 return NULL;
121
122 cla->cl.clk = clk;
123 if (con_id) {
124 strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
125 cla->cl.con_id = cla->con_id;
126 }
127
128 if (dev_fmt) {
129 va_list ap;
130
131 va_start(ap, dev_fmt);
132 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
133 cla->cl.dev_id = cla->dev_id;
134 va_end(ap);
135 }
136
137 return &cla->cl;
138}
139EXPORT_SYMBOL(clkdev_alloc);
140
141int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
142 struct device *dev)
143{
144 struct clk *r = clk_get(dev, id);
145 struct clk_lookup *l;
146
147 if (IS_ERR(r))
148 return PTR_ERR(r);
149
150 l = clkdev_alloc(r, alias, alias_dev_name);
151 clk_put(r);
152 if (!l)
153 return -ENODEV;
154 clkdev_add(l);
155 return 0;
156}
157EXPORT_SYMBOL(clk_add_alias);
158
159/*
160 * clkdev_drop - remove a clock dynamically allocated
161 */
162void clkdev_drop(struct clk_lookup *cl)
163{
164 mutex_lock(&clocks_mutex);
165 list_del(&cl->node);
166 mutex_unlock(&clocks_mutex);
167 kfree(cl);
168}
169EXPORT_SYMBOL(clkdev_drop);
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 4edcb60a1355..ae95935d93cd 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,7 +17,5 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
17 17
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20obj-$(CONFIG_SH_FPU) += fpu.o
21obj-$(CONFIG_SH_FPU_EMU) += fpu.o
22 20
23obj-y += irq/ init.o clock.o hwblk.o 21obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index e2f63d68da51..8f63a264a842 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -2,7 +2,7 @@
2#include <linux/compiler.h> 2#include <linux/compiler.h>
3#include <linux/slab.h> 3#include <linux/slab.h>
4#include <linux/io.h> 4#include <linux/io.h>
5#include <asm/clkdev.h> 5#include <linux/clkdev.h>
6#include <asm/clock.h> 6#include <asm/clock.h>
7 7
8static struct clk master_clk = { 8static struct clk master_clk = {
@@ -67,7 +67,7 @@ int __init __deprecated cpg_clk_init(void)
67} 67}
68 68
69/* 69/*
70 * Placeholder for compatability, until the lazy CPUs do this 70 * Placeholder for compatibility, until the lazy CPUs do this
71 * on their own. 71 * on their own.
72 */ 72 */
73int __init __weak arch_clk_init(void) 73int __init __weak arch_clk_init(void)
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 50f887dda565..4187cf4fe185 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -48,20 +48,4 @@ int __init clk_init(void)
48 return ret; 48 return ret;
49} 49}
50 50
51/*
52 * Returns a clock. Note that we first try to use device id on the bus
53 * and clock name. If this fails, we try to use clock name only.
54 */
55struct clk *clk_get(struct device *dev, const char *con_id)
56{
57 const char *dev_id = dev ? dev_name(dev) : NULL;
58
59 return clk_get_sys(dev_id, con_id);
60}
61EXPORT_SYMBOL_GPL(clk_get);
62
63void clk_put(struct clk *clk)
64{
65}
66EXPORT_SYMBOL_GPL(clk_put);
67 51
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 97661061ff20..fac742e514ee 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -340,6 +340,8 @@ asmlinkage void __cpuinit cpu_init(void)
340 */ 340 */
341 current_cpu_data.asid_cache = NO_CONTEXT; 341 current_cpu_data.asid_cache = NO_CONTEXT;
342 342
343 current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
344
343 speculative_execution_init(); 345 speculative_execution_init();
344 expmask_init(); 346 expmask_init();
345 347
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index a351ed84eec5..39b6a24c159d 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,16 +51,20 @@ static inline void set_interrupt_registers(int ip)
51 : "t"); 51 : "t");
52} 52}
53 53
54static void mask_imask_irq(unsigned int irq) 54static void mask_imask_irq(struct irq_data *data)
55{ 55{
56 unsigned int irq = data->irq;
57
56 clear_bit(irq, imask_mask); 58 clear_bit(irq, imask_mask);
57 if (interrupt_priority < IMASK_PRIORITY - irq) 59 if (interrupt_priority < IMASK_PRIORITY - irq)
58 interrupt_priority = IMASK_PRIORITY - irq; 60 interrupt_priority = IMASK_PRIORITY - irq;
59 set_interrupt_registers(interrupt_priority); 61 set_interrupt_registers(interrupt_priority);
60} 62}
61 63
62static void unmask_imask_irq(unsigned int irq) 64static void unmask_imask_irq(struct irq_data *data)
63{ 65{
66 unsigned int irq = data->irq;
67
64 set_bit(irq, imask_mask); 68 set_bit(irq, imask_mask);
65 interrupt_priority = IMASK_PRIORITY - 69 interrupt_priority = IMASK_PRIORITY -
66 find_first_zero_bit(imask_mask, IMASK_PRIORITY); 70 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
@@ -69,13 +73,13 @@ static void unmask_imask_irq(unsigned int irq)
69 73
70static struct irq_chip imask_irq_chip = { 74static struct irq_chip imask_irq_chip = {
71 .name = "SR.IMASK", 75 .name = "SR.IMASK",
72 .mask = mask_imask_irq, 76 .irq_mask = mask_imask_irq,
73 .unmask = unmask_imask_irq, 77 .irq_unmask = unmask_imask_irq,
74 .mask_ack = mask_imask_irq, 78 .irq_mask_ack = mask_imask_irq,
75}; 79};
76 80
77void make_imask_irq(unsigned int irq) 81void make_imask_irq(unsigned int irq)
78{ 82{
79 set_irq_chip_and_handler_name(irq, &imask_irq_chip, 83 irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
80 handle_level_irq, "level"); 84 "level");
81} 85}
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 96a239583948..9e056a3a0c73 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -76,39 +76,11 @@ int intc_evt_to_irq[(0xE20/0x20)+1] = {
76}; 76};
77 77
78static unsigned long intc_virt; 78static unsigned long intc_virt;
79
80static unsigned int startup_intc_irq(unsigned int irq);
81static void shutdown_intc_irq(unsigned int irq);
82static void enable_intc_irq(unsigned int irq);
83static void disable_intc_irq(unsigned int irq);
84static void mask_and_ack_intc(unsigned int);
85static void end_intc_irq(unsigned int irq);
86
87static struct irq_chip intc_irq_type = {
88 .name = "INTC",
89 .startup = startup_intc_irq,
90 .shutdown = shutdown_intc_irq,
91 .enable = enable_intc_irq,
92 .disable = disable_intc_irq,
93 .ack = mask_and_ack_intc,
94 .end = end_intc_irq
95};
96
97static int irlm; /* IRL mode */ 79static int irlm; /* IRL mode */
98 80
99static unsigned int startup_intc_irq(unsigned int irq) 81static void enable_intc_irq(struct irq_data *data)
100{
101 enable_intc_irq(irq);
102 return 0; /* never anything pending */
103}
104
105static void shutdown_intc_irq(unsigned int irq)
106{
107 disable_intc_irq(irq);
108}
109
110static void enable_intc_irq(unsigned int irq)
111{ 82{
83 unsigned int irq = data->irq;
112 unsigned long reg; 84 unsigned long reg;
113 unsigned long bitmask; 85 unsigned long bitmask;
114 86
@@ -126,8 +98,9 @@ static void enable_intc_irq(unsigned int irq)
126 __raw_writel(bitmask, reg); 98 __raw_writel(bitmask, reg);
127} 99}
128 100
129static void disable_intc_irq(unsigned int irq) 101static void disable_intc_irq(struct irq_data *data)
130{ 102{
103 unsigned int irq = data->irq;
131 unsigned long reg; 104 unsigned long reg;
132 unsigned long bitmask; 105 unsigned long bitmask;
133 106
@@ -142,15 +115,11 @@ static void disable_intc_irq(unsigned int irq)
142 __raw_writel(bitmask, reg); 115 __raw_writel(bitmask, reg);
143} 116}
144 117
145static void mask_and_ack_intc(unsigned int irq) 118static struct irq_chip intc_irq_type = {
146{ 119 .name = "INTC",
147 disable_intc_irq(irq); 120 .irq_enable = enable_intc_irq,
148} 121 .irq_disable = disable_intc_irq,
149 122};
150static void end_intc_irq(unsigned int irq)
151{
152 enable_intc_irq(irq);
153}
154 123
155void __init plat_irq_setup(void) 124void __init plat_irq_setup(void)
156{ 125{
@@ -166,7 +135,7 @@ void __init plat_irq_setup(void)
166 135
167 /* Set default: per-line enable/disable, priority driven ack/eoi */ 136 /* Set default: per-line enable/disable, priority driven ack/eoi */
168 for (i = 0; i < NR_INTC_IRQS; i++) 137 for (i = 0; i < NR_INTC_IRQS; i++)
169 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); 138 irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
170 139
171 140
172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 141 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 9282d965a1b6..5de6dff5c21b 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -24,25 +24,25 @@
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/topology.h> 25#include <linux/topology.h>
26 26
27static inline struct ipr_desc *get_ipr_desc(unsigned int irq) 27static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
28{ 28{
29 struct irq_chip *chip = get_irq_chip(irq); 29 struct irq_chip *chip = irq_data_get_irq_chip(data);
30 return container_of(chip, struct ipr_desc, chip); 30 return container_of(chip, struct ipr_desc, chip);
31} 31}
32 32
33static void disable_ipr_irq(unsigned int irq) 33static void disable_ipr_irq(struct irq_data *data)
34{ 34{
35 struct ipr_data *p = get_irq_chip_data(irq); 35 struct ipr_data *p = irq_data_get_irq_chip_data(data);
36 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; 36 unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
37 /* Set the priority in IPR to 0 */ 37 /* Set the priority in IPR to 0 */
38 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr); 38 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
39 (void)__raw_readw(addr); /* Read back to flush write posting */ 39 (void)__raw_readw(addr); /* Read back to flush write posting */
40} 40}
41 41
42static void enable_ipr_irq(unsigned int irq) 42static void enable_ipr_irq(struct irq_data *data)
43{ 43{
44 struct ipr_data *p = get_irq_chip_data(irq); 44 struct ipr_data *p = irq_data_get_irq_chip_data(data);
45 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; 45 unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
46 /* Set priority in IPR back to original value */ 46 /* Set priority in IPR back to original value */
47 __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr); 47 __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
48} 48}
@@ -56,29 +56,28 @@ void register_ipr_controller(struct ipr_desc *desc)
56{ 56{
57 int i; 57 int i;
58 58
59 desc->chip.mask = disable_ipr_irq; 59 desc->chip.irq_mask = disable_ipr_irq;
60 desc->chip.unmask = enable_ipr_irq; 60 desc->chip.irq_unmask = enable_ipr_irq;
61 desc->chip.mask_ack = disable_ipr_irq;
62 61
63 for (i = 0; i < desc->nr_irqs; i++) { 62 for (i = 0; i < desc->nr_irqs; i++) {
64 struct ipr_data *p = desc->ipr_data + i; 63 struct ipr_data *p = desc->ipr_data + i;
65 struct irq_desc *irq_desc; 64 int res;
66 65
67 BUG_ON(p->ipr_idx >= desc->nr_offsets); 66 BUG_ON(p->ipr_idx >= desc->nr_offsets);
68 BUG_ON(!desc->ipr_offsets[p->ipr_idx]); 67 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
69 68
70 irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id()); 69 res = irq_alloc_desc_at(p->irq, numa_node_id());
71 if (unlikely(!irq_desc)) { 70 if (unlikely(res != p->irq && res != -EEXIST)) {
72 printk(KERN_INFO "can not get irq_desc for %d\n", 71 printk(KERN_INFO "can not get irq_desc for %d\n",
73 p->irq); 72 p->irq);
74 continue; 73 continue;
75 } 74 }
76 75
77 disable_irq_nosync(p->irq); 76 disable_irq_nosync(p->irq);
78 set_irq_chip_and_handler_name(p->irq, &desc->chip, 77 irq_set_chip_and_handler_name(p->irq, &desc->chip,
79 handle_level_irq, "level"); 78 handle_level_irq, "level");
80 set_irq_chip_data(p->irq, p); 79 irq_set_chip_data(p->irq, p);
81 disable_ipr_irq(p->irq); 80 disable_ipr_irq(irq_get_irq_data(p->irq));
82 } 81 }
83} 82}
84EXPORT_SYMBOL(register_ipr_controller); 83EXPORT_SYMBOL(register_ipr_controller);
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..f47be8727b3b
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
1#include <linux/seq_file.h>
2#include <linux/kernel.h>
3#include <linux/module.h>
4#include <asm/machvec.h>
5#include <asm/processor.h>
6
7static const char *cpu_name[] = {
8 [CPU_SH7201] = "SH7201",
9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
10 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
11 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
12 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
13 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
14 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
15 [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
16 [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
17 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
18 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
19 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
20 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
21 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
22 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
23 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
24 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
28 [CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown"
29};
30
31const char *get_cpu_subtype(struct sh_cpuinfo *c)
32{
33 return cpu_name[c->type];
34}
35EXPORT_SYMBOL(get_cpu_subtype);
36
37#ifdef CONFIG_PROC_FS
38/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
39static const char *cpu_flags[] = {
40 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
41 "ptea", "llsc", "l2", "op32", "pteaex", NULL
42};
43
44static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
45{
46 unsigned long i;
47
48 seq_printf(m, "cpu flags\t:");
49
50 if (!c->flags) {
51 seq_printf(m, " %s\n", cpu_flags[0]);
52 return;
53 }
54
55 for (i = 0; cpu_flags[i]; i++)
56 if ((c->flags & (1 << i)))
57 seq_printf(m, " %s", cpu_flags[i+1]);
58
59 seq_printf(m, "\n");
60}
61
62static void show_cacheinfo(struct seq_file *m, const char *type,
63 struct cache_info info)
64{
65 unsigned int cache_size;
66
67 cache_size = info.ways * info.sets * info.linesz;
68
69 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
70 type, cache_size >> 10, info.ways);
71}
72
73/*
74 * Get CPU information for use by the procfs.
75 */
76static int show_cpuinfo(struct seq_file *m, void *v)
77{
78 struct sh_cpuinfo *c = v;
79 unsigned int cpu = c - cpu_data;
80
81 if (!cpu_online(cpu))
82 return 0;
83
84 if (cpu == 0)
85 seq_printf(m, "machine\t\t: %s\n", get_system_type());
86 else
87 seq_printf(m, "\n");
88
89 seq_printf(m, "processor\t: %d\n", cpu);
90 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
91 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
92 if (c->cut_major == -1)
93 seq_printf(m, "cut\t\t: unknown\n");
94 else if (c->cut_minor == -1)
95 seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
96 else
97 seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
98
99 show_cpuflags(m, c);
100
101 seq_printf(m, "cache type\t: ");
102
103 /*
104 * Check for what type of cache we have, we support both the
105 * unified cache on the SH-2 and SH-3, as well as the harvard
106 * style cache on the SH-4.
107 */
108 if (c->icache.flags & SH_CACHE_COMBINED) {
109 seq_printf(m, "unified\n");
110 show_cacheinfo(m, "cache", c->icache);
111 } else {
112 seq_printf(m, "split (harvard)\n");
113 show_cacheinfo(m, "icache", c->icache);
114 show_cacheinfo(m, "dcache", c->dcache);
115 }
116
117 /* Optional secondary cache */
118 if (c->flags & CPU_HAS_L2_CACHE)
119 show_cacheinfo(m, "scache", c->scache);
120
121 seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
122
123 seq_printf(m, "bogomips\t: %lu.%02lu\n",
124 c->loops_per_jiffy/(500000/HZ),
125 (c->loops_per_jiffy/(5000/HZ)) % 100);
126
127 return 0;
128}
129
130static void *c_start(struct seq_file *m, loff_t *pos)
131{
132 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
133}
134static void *c_next(struct seq_file *m, void *v, loff_t *pos)
135{
136 ++*pos;
137 return c_start(m, pos);
138}
139static void c_stop(struct seq_file *m, void *v)
140{
141}
142const struct seq_operations cpuinfo_op = {
143 .start = c_start,
144 .next = c_next,
145 .stop = c_stop,
146 .show = show_cpuinfo,
147};
148#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 0c9f24d7a02f..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
14 */ 14 */
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/io.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <asm/io.h> 20#include <asm/processor.h>
20 21
21static const int pll1rate[] = {1,2}; 22static const int pll1rate[] = {1,2};
22static const int pfc_divisors[] = {1,2,0,4}; 23static const int pfc_divisors[] = {1,2,0,4};
23 24static unsigned int pll2_mult;
24#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
25#define PLL2 (4)
26#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
27#define PLL2 (2)
28#else
29#error "Illigal Clock Mode!"
30#endif
31 25
32static void master_clk_init(struct clk *clk) 26static void master_clk_init(struct clk *clk)
33{ 27{
34 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; 28 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
35} 29}
36 30
37static struct clk_ops sh7619_master_clk_ops = { 31static struct clk_ops sh7619_master_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
70 64
71void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 65void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
72{ 66{
67 if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
68 test_mode_pin(MODE_PIN2 | MODE_PIN1))
69 pll2_mult = 2;
70 else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
71 pll2_mult = 4;
72
73 BUG_ON(!pll2_mult);
74
73 if (idx < ARRAY_SIZE(sh7619_clk_ops)) 75 if (idx < ARRAY_SIZE(sh7619_clk_ops))
74 *ops = sh7619_clk_ops[idx]; 76 *ops = sh7619_clk_ops[idx];
75} 77}
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index c3638516bffc..0f8befccf9fa 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -62,6 +62,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
62static struct plat_sci_port scif0_platform_data = { 62static struct plat_sci_port scif0_platform_data = {
63 .mapbase = 0xf8400000, 63 .mapbase = 0xf8400000,
64 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
66 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 67 .type = PORT_SCIF,
66 .irqs = { 88, 88, 88, 88 }, 68 .irqs = { 88, 88, 88, 88 },
67}; 69};
@@ -77,6 +79,8 @@ static struct platform_device scif0_device = {
77static struct plat_sci_port scif1_platform_data = { 79static struct plat_sci_port scif1_platform_data = {
78 .mapbase = 0xf8410000, 80 .mapbase = 0xf8410000,
79 .flags = UPF_BOOT_AUTOCONF, 81 .flags = UPF_BOOT_AUTOCONF,
82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
83 .scbrr_algo_id = SCBRR_ALGO_2,
80 .type = PORT_SCIF, 84 .type = PORT_SCIF,
81 .irqs = { 92, 92, 92, 92 }, 85 .irqs = { 92, 92, 92, 92 },
82}; 86};
@@ -92,6 +96,8 @@ static struct platform_device scif1_device = {
92static struct plat_sci_port scif2_platform_data = { 96static struct plat_sci_port scif2_platform_data = {
93 .mapbase = 0xf8420000, 97 .mapbase = 0xf8420000,
94 .flags = UPF_BOOT_AUTOCONF, 98 .flags = UPF_BOOT_AUTOCONF,
99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
100 .scbrr_algo_id = SCBRR_ALGO_2,
95 .type = PORT_SCIF, 101 .type = PORT_SCIF,
96 .irqs = { 96, 96, 96, 96 }, 102 .irqs = { 96, 96, 96, 96 },
97}; 103};
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index b26264dc2aef..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12}; 22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors 23#define ifc_divisors pfc_divisors
24 24
25#if (CONFIG_SH_CLK_MD == 0) 25static unsigned int pll2_mult;
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 2)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 3)
30#define PLL2 (1)
31#else
32#error "Illegal Clock Mode!"
33#endif
34 26
35static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
36{ 28{
37 return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 29 clk->rate = 10000000 * pll2_mult *
30 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 31}
39 32
40static struct clk_ops sh7201_master_clk_ops = { 33static struct clk_ops sh7201_master_clk_ops = {
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
80 73
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 74void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
82{ 75{
76 if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
77 pll2_mult = 1;
78 else if (test_mode_pin(MODE_PIN1))
79 pll2_mult = 2;
80 else
81 pll2_mult = 4;
82
83 if (idx < ARRAY_SIZE(sh7201_clk_ops)) 83 if (idx < ARRAY_SIZE(sh7201_clk_ops))
84 *ops = sh7201_clk_ops[idx]; 84 *ops = sh7201_clk_ops[idx];
85} 85}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 7e75d8f79502..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
25static const int pfc_divisors[]={1,2,3,4,6,8,12}; 25static const int pfc_divisors[]={1,2,3,4,6,8,12};
26#define ifc_divisors pfc_divisors 26#define ifc_divisors pfc_divisors
27 27
28#if (CONFIG_SH_CLK_MD == 0) 28static unsigned int pll2_mult;
29#define PLL2 (1)
30#elif (CONFIG_SH_CLK_MD == 1)
31#define PLL2 (2)
32#elif (CONFIG_SH_CLK_MD == 2)
33#define PLL2 (4)
34#elif (CONFIG_SH_CLK_MD == 3)
35#define PLL2 (4)
36#else
37#error "Illegal Clock Mode!"
38#endif
39 29
40static void master_clk_init(struct clk *clk) 30static void master_clk_init(struct clk *clk)
41{ 31{
42 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ; 32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
43} 33}
44 34
45static struct clk_ops sh7203_master_clk_ops = { 35static struct clk_ops sh7203_master_clk_ops = {
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
79 69
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 70void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
81{ 71{
72 if (test_mode_pin(MODE_PIN1))
73 pll2_mult = 4;
74 else if (test_mode_pin(MODE_PIN0))
75 pll2_mult = 2;
76 else
77 pll2_mult = 1;
78
82 if (idx < ARRAY_SIZE(sh7203_clk_ops)) 79 if (idx < ARRAY_SIZE(sh7203_clk_ops))
83 *ops = sh7203_clk_ops[idx]; 80 *ops = sh7203_clk_ops[idx];
84} 81}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index b27a5e2687ab..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12}; 22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors 23#define ifc_divisors pfc_divisors
24 24
25#if (CONFIG_SH_CLK_MD == 2) 25static unsigned int pll2_mult;
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 6)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 7)
30#define PLL2 (1)
31#else
32#error "Illigal Clock Mode!"
33#endif
34 26
35static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
36{ 28{
37 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 30}
39 31
40static struct clk_ops sh7206_master_clk_ops = { 32static struct clk_ops sh7206_master_clk_ops = {
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
79 71
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 72void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
81{ 73{
74 if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
75 pll2_mult = 1;
76 else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
77 pll2_mult = 2;
78 else if (test_mode_pin(MODE_PIN1))
79 pll2_mult = 4;
80
82 if (idx < ARRAY_SIZE(sh7206_clk_ops)) 81 if (idx < ARRAY_SIZE(sh7206_clk_ops))
83 *ops = sh7206_clk_ops[idx]; 82 *ops = sh7206_clk_ops[idx];
84} 83}
85
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 6c96ea02bf8d..949bf2bac28c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -201,6 +201,8 @@ static struct platform_device mtu2_2_device = {
201static struct plat_sci_port scif0_platform_data = { 201static struct plat_sci_port scif0_platform_data = {
202 .mapbase = 0xff804000, 202 .mapbase = 0xff804000,
203 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2,
204 .type = PORT_SCIF, 206 .type = PORT_SCIF,
205 .irqs = { 220, 220, 220, 220 }, 207 .irqs = { 220, 220, 220, 220 },
206}; 208};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index d08bf4c07d60..9df558dcdb86 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -180,6 +180,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
180static struct plat_sci_port scif0_platform_data = { 180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xfffe8000, 181 .mapbase = 0xfffe8000,
182 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
183 .type = PORT_SCIF, 185 .type = PORT_SCIF,
184 .irqs = { 180, 180, 180, 180 } 186 .irqs = { 180, 180, 180, 180 }
185}; 187};
@@ -195,6 +197,8 @@ static struct platform_device scif0_device = {
195static struct plat_sci_port scif1_platform_data = { 197static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800, 198 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF, 199 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCIF, 202 .type = PORT_SCIF,
199 .irqs = { 184, 184, 184, 184 } 203 .irqs = { 184, 184, 184, 184 }
200}; 204};
@@ -210,6 +214,8 @@ static struct platform_device scif1_device = {
210static struct plat_sci_port scif2_platform_data = { 214static struct plat_sci_port scif2_platform_data = {
211 .mapbase = 0xfffe9000, 215 .mapbase = 0xfffe9000,
212 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2,
213 .type = PORT_SCIF, 219 .type = PORT_SCIF,
214 .irqs = { 188, 188, 188, 188 } 220 .irqs = { 188, 188, 188, 188 }
215}; 221};
@@ -225,6 +231,8 @@ static struct platform_device scif2_device = {
225static struct plat_sci_port scif3_platform_data = { 231static struct plat_sci_port scif3_platform_data = {
226 .mapbase = 0xfffe9800, 232 .mapbase = 0xfffe9800,
227 .flags = UPF_BOOT_AUTOCONF, 233 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2,
228 .type = PORT_SCIF, 236 .type = PORT_SCIF,
229 .irqs = { 192, 192, 192, 192 } 237 .irqs = { 192, 192, 192, 192 }
230}; 238};
@@ -240,6 +248,8 @@ static struct platform_device scif3_device = {
240static struct plat_sci_port scif4_platform_data = { 248static struct plat_sci_port scif4_platform_data = {
241 .mapbase = 0xfffea000, 249 .mapbase = 0xfffea000,
242 .flags = UPF_BOOT_AUTOCONF, 250 .flags = UPF_BOOT_AUTOCONF,
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
243 .type = PORT_SCIF, 253 .type = PORT_SCIF,
244 .irqs = { 196, 196, 196, 196 } 254 .irqs = { 196, 196, 196, 196 }
245}; 255};
@@ -255,6 +265,8 @@ static struct platform_device scif4_device = {
255static struct plat_sci_port scif5_platform_data = { 265static struct plat_sci_port scif5_platform_data = {
256 .mapbase = 0xfffea800, 266 .mapbase = 0xfffea800,
257 .flags = UPF_BOOT_AUTOCONF, 267 .flags = UPF_BOOT_AUTOCONF,
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2,
258 .type = PORT_SCIF, 270 .type = PORT_SCIF,
259 .irqs = { 200, 200, 200, 200 } 271 .irqs = { 200, 200, 200, 200 }
260}; 272};
@@ -270,6 +282,8 @@ static struct platform_device scif5_device = {
270static struct plat_sci_port scif6_platform_data = { 282static struct plat_sci_port scif6_platform_data = {
271 .mapbase = 0xfffeb000, 283 .mapbase = 0xfffeb000,
272 .flags = UPF_BOOT_AUTOCONF, 284 .flags = UPF_BOOT_AUTOCONF,
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2,
273 .type = PORT_SCIF, 287 .type = PORT_SCIF,
274 .irqs = { 204, 204, 204, 204 } 288 .irqs = { 204, 204, 204, 204 }
275}; 289};
@@ -285,6 +299,8 @@ static struct platform_device scif6_device = {
285static struct plat_sci_port scif7_platform_data = { 299static struct plat_sci_port scif7_platform_data = {
286 .mapbase = 0xfffeb800, 300 .mapbase = 0xfffeb800,
287 .flags = UPF_BOOT_AUTOCONF, 301 .flags = UPF_BOOT_AUTOCONF,
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2,
288 .type = PORT_SCIF, 304 .type = PORT_SCIF,
289 .irqs = { 208, 208, 208, 208 } 305 .irqs = { 208, 208, 208, 208 }
290}; 306};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 832f401b5860..a43124e608c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -176,6 +176,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
176static struct plat_sci_port scif0_platform_data = { 176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000, 177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF, 178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
180 .scbrr_algo_id = SCBRR_ALGO_2,
179 .type = PORT_SCIF, 181 .type = PORT_SCIF,
180 .irqs = { 192, 192, 192, 192 }, 182 .irqs = { 192, 192, 192, 192 },
181}; 183};
@@ -191,6 +193,8 @@ static struct platform_device scif0_device = {
191static struct plat_sci_port scif1_platform_data = { 193static struct plat_sci_port scif1_platform_data = {
192 .mapbase = 0xfffe8800, 194 .mapbase = 0xfffe8800,
193 .flags = UPF_BOOT_AUTOCONF, 195 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
194 .type = PORT_SCIF, 198 .type = PORT_SCIF,
195 .irqs = { 196, 196, 196, 196 }, 199 .irqs = { 196, 196, 196, 196 },
196}; 200};
@@ -206,6 +210,8 @@ static struct platform_device scif1_device = {
206static struct plat_sci_port scif2_platform_data = { 210static struct plat_sci_port scif2_platform_data = {
207 .mapbase = 0xfffe9000, 211 .mapbase = 0xfffe9000,
208 .flags = UPF_BOOT_AUTOCONF, 212 .flags = UPF_BOOT_AUTOCONF,
213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
214 .scbrr_algo_id = SCBRR_ALGO_2,
209 .type = PORT_SCIF, 215 .type = PORT_SCIF,
210 .irqs = { 200, 200, 200, 200 }, 216 .irqs = { 200, 200, 200, 200 },
211}; 217};
@@ -221,6 +227,8 @@ static struct platform_device scif2_device = {
221static struct plat_sci_port scif3_platform_data = { 227static struct plat_sci_port scif3_platform_data = {
222 .mapbase = 0xfffe9800, 228 .mapbase = 0xfffe9800,
223 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
231 .scbrr_algo_id = SCBRR_ALGO_2,
224 .type = PORT_SCIF, 232 .type = PORT_SCIF,
225 .irqs = { 204, 204, 204, 204 }, 233 .irqs = { 204, 204, 204, 204 },
226}; 234};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index dc47b04e1049..5d14f849aea3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -136,6 +136,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
136static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000, 137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
139 .type = PORT_SCIF, 141 .type = PORT_SCIF,
140 .irqs = { 240, 240, 240, 240 }, 142 .irqs = { 240, 240, 240, 240 },
141}; 143};
@@ -151,6 +153,8 @@ static struct platform_device scif0_device = {
151static struct plat_sci_port scif1_platform_data = { 153static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfffe8800, 154 .mapbase = 0xfffe8800,
153 .flags = UPF_BOOT_AUTOCONF, 155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
154 .type = PORT_SCIF, 158 .type = PORT_SCIF,
155 .irqs = { 244, 244, 244, 244 }, 159 .irqs = { 244, 244, 244, 244 },
156}; 160};
@@ -166,6 +170,8 @@ static struct platform_device scif1_device = {
166static struct plat_sci_port scif2_platform_data = { 170static struct plat_sci_port scif2_platform_data = {
167 .mapbase = 0xfffe9000, 171 .mapbase = 0xfffe9000,
168 .flags = UPF_BOOT_AUTOCONF, 172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
169 .type = PORT_SCIF, 175 .type = PORT_SCIF,
170 .irqs = { 248, 248, 248, 248 }, 176 .irqs = { 248, 248, 248, 248 },
171}; 177};
@@ -181,6 +187,8 @@ static struct platform_device scif2_device = {
181static struct plat_sci_port scif3_platform_data = { 187static struct plat_sci_port scif3_platform_data = {
182 .mapbase = 0xfffe9800, 188 .mapbase = 0xfffe9800,
183 .flags = UPF_BOOT_AUTOCONF, 189 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 192 .type = PORT_SCIF,
185 .irqs = { 252, 252, 252, 252 }, 193 .irqs = { 252, 252, 252, 252 },
186}; 194};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index baadd7f54d94..cd2e702feb7e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,6 +70,9 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
70static struct plat_sci_port scif0_platform_data = { 70static struct plat_sci_port scif0_platform_data = {
71 .mapbase = 0xa4410000, 71 .mapbase = 0xa4410000,
72 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
74 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
75 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 76 .type = PORT_SCIF,
74 .irqs = { 56, 56, 56 }, 77 .irqs = { 56, 56, 56 },
75}; 78};
@@ -85,6 +88,8 @@ static struct platform_device scif0_device = {
85static struct plat_sci_port scif1_platform_data = { 88static struct plat_sci_port scif1_platform_data = {
86 .mapbase = 0xa4400000, 89 .mapbase = 0xa4400000,
87 .flags = UPF_BOOT_AUTOCONF, 90 .flags = UPF_BOOT_AUTOCONF,
91 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
92 .scbrr_algo_id = SCBRR_ALGO_4,
88 .type = PORT_SCIF, 93 .type = PORT_SCIF,
89 .irqs = { 52, 52, 52 }, 94 .irqs = { 52, 52, 52 },
90}; 95};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 3cf8c8ef7b32..4551ad647c2c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,6 +109,8 @@ static struct platform_device rtc_device = {
109static struct plat_sci_port scif0_platform_data = { 109static struct plat_sci_port scif0_platform_data = {
110 .mapbase = 0xfffffe80, 110 .mapbase = 0xfffffe80,
111 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_TE | SCSCR_RE,
113 .scbrr_algo_id = SCBRR_ALGO_2,
112 .type = PORT_SCI, 114 .type = PORT_SCI,
113 .irqs = { 23, 23, 23, 0 }, 115 .irqs = { 23, 23, 23, 0 },
114}; 116};
@@ -126,6 +128,8 @@ static struct platform_device scif0_device = {
126static struct plat_sci_port scif1_platform_data = { 128static struct plat_sci_port scif1_platform_data = {
127 .mapbase = 0xa4000150, 129 .mapbase = 0xa4000150,
128 .flags = UPF_BOOT_AUTOCONF, 130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_TE | SCSCR_RE,
132 .scbrr_algo_id = SCBRR_ALGO_2,
129 .type = PORT_SCIF, 133 .type = PORT_SCIF,
130 .irqs = { 56, 56, 56, 56 }, 134 .irqs = { 56, 56, 56, 56 },
131}; 135};
@@ -143,6 +147,8 @@ static struct platform_device scif1_device = {
143static struct plat_sci_port scif2_platform_data = { 147static struct plat_sci_port scif2_platform_data = {
144 .mapbase = 0xa4000140, 148 .mapbase = 0xa4000140,
145 .flags = UPF_BOOT_AUTOCONF, 149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_TE | SCSCR_RE,
151 .scbrr_algo_id = SCBRR_ALGO_2,
146 .type = PORT_IRDA, 152 .type = PORT_IRDA,
147 .irqs = { 52, 52, 52, 52 }, 153 .irqs = { 52, 52, 52, 52 },
148}; 154};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index b0c2fb4ab479..78f6b01d42c3 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -99,6 +99,9 @@ static struct platform_device rtc_device = {
99static struct plat_sci_port scif0_platform_data = { 99static struct plat_sci_port scif0_platform_data = {
100 .mapbase = 0xa4400000, 100 .mapbase = 0xa4400000,
101 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
103 SCSCR_CKE1 | SCSCR_CKE0,
104 .scbrr_algo_id = SCBRR_ALGO_2,
102 .type = PORT_SCIF, 105 .type = PORT_SCIF,
103 .irqs = { 52, 52, 52, 52 }, 106 .irqs = { 52, 52, 52, 52 },
104}; 107};
@@ -114,6 +117,9 @@ static struct platform_device scif0_device = {
114static struct plat_sci_port scif1_platform_data = { 117static struct plat_sci_port scif1_platform_data = {
115 .mapbase = 0xa4410000, 118 .mapbase = 0xa4410000,
116 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
121 SCSCR_CKE1 | SCSCR_CKE0,
122 .scbrr_algo_id = SCBRR_ALGO_2,
117 .type = PORT_SCIF, 123 .type = PORT_SCIF,
118 .irqs = { 56, 56, 56, 56 }, 124 .irqs = { 56, 56, 56, 56 },
119}; 125};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 24b17135d5d2..365b94a6fcb7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * SH7720 Setup 2 * Setup code for SH7720, SH7721.
3 * 3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt 5 * Copyright (C) 2009 Paul Mundt
@@ -51,6 +51,8 @@ static struct platform_device rtc_device = {
51static struct plat_sci_port scif0_platform_data = { 51static struct plat_sci_port scif0_platform_data = {
52 .mapbase = 0xa4430000, 52 .mapbase = 0xa4430000,
53 .flags = UPF_BOOT_AUTOCONF, 53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE,
55 .scbrr_algo_id = SCBRR_ALGO_4,
54 .type = PORT_SCIF, 56 .type = PORT_SCIF,
55 .irqs = { 80, 80, 80, 80 }, 57 .irqs = { 80, 80, 80, 80 },
56}; 58};
@@ -66,6 +68,8 @@ static struct platform_device scif0_device = {
66static struct plat_sci_port scif1_platform_data = { 68static struct plat_sci_port scif1_platform_data = {
67 .mapbase = 0xa4438000, 69 .mapbase = 0xa4438000,
68 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
69 .type = PORT_SCIF, 73 .type = PORT_SCIF,
70 .irqs = { 81, 81, 81, 81 }, 74 .irqs = { 81, 81, 81, 81 },
71}; 75};
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 4eabc68cd753..3f6f8e98635c 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -13,7 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/clkdev.h> 16#include <linux/clkdev.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/freq.h> 18#include <asm/freq.h>
19 19
@@ -81,8 +81,7 @@ static void shoc_clk_init(struct clk *clk)
81 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) { 81 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
82 int divisor = frqcr3_divisors[i]; 82 int divisor = frqcr3_divisors[i];
83 83
84 if (clk->ops->set_rate(clk, clk->parent->rate / 84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
85 divisor, 0) == 0)
86 break; 85 break;
87 } 86 }
88 87
@@ -110,7 +109,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
110 return 0; 109 return 0;
111} 110}
112 111
113static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) 112static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
114{ 113{
115 unsigned long frqcr3; 114 unsigned long frqcr3;
116 unsigned int tmp; 115 unsigned int tmp;
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index 7f9ecc9c2d02..748955df018d 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -225,7 +225,7 @@ static void sh7750_pmu_enable_all(void)
225} 225}
226 226
227static struct sh_pmu sh7750_pmu = { 227static struct sh_pmu sh7750_pmu = {
228 .name = "SH7750", 228 .name = "sh7750",
229 .num_events = 2, 229 .num_events = 2,
230 .event_map = sh7750_event_map, 230 .event_map = sh7750_event_map,
231 .max_events = ARRAY_SIZE(sh7750_general_events), 231 .max_events = ARRAY_SIZE(sh7750_general_events),
@@ -250,4 +250,4 @@ static int __init sh7750_pmu_init(void)
250 250
251 return register_sh_pmu(&sh7750_pmu); 251 return register_sh_pmu(&sh7750_pmu);
252} 252}
253arch_initcall(sh7750_pmu_init); 253early_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index d180f16281ed..971cf0fce4f5 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -150,9 +150,15 @@ void __cpuinit cpu_probe(void)
150 boot_cpu_data.type = CPU_SH7724; 150 boot_cpu_data.type = CPU_SH7724;
151 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 151 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
152 break; 152 break;
153 case 0x50: 153 case 0x10:
154 case 0x11:
154 boot_cpu_data.type = CPU_SH7757; 155 boot_cpu_data.type = CPU_SH7757;
155 break; 156 break;
157 case 0xd0:
158 case 0x40: /* yon-ten-go */
159 boot_cpu_data.type = CPU_SH7372;
160 break;
161
156 } 162 }
157 break; 163 break;
158 case 0x4000: /* 1st cut */ 164 case 0x4000: /* 1st cut */
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index e916b18e1f7c..5b2833159b7d 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -18,6 +18,8 @@
18static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
19 .mapbase = 0xffe80000, 19 .mapbase = 0xffe80000,
20 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22 .scbrr_algo_id = SCBRR_ALGO_2,
21 .type = PORT_SCIF, 23 .type = PORT_SCIF,
22 .irqs = { 40, 41, 43, 42 }, 24 .irqs = { 40, 41, 43, 42 },
23}; 25};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 911d196e86b5..e53b4b38bd11 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/serial_sci.h> 16#include <linux/serial_sci.h>
17#include <generated/machtypes.h>
17 18
18static struct resource rtc_resources[] = { 19static struct resource rtc_resources[] = {
19 [0] = { 20 [0] = {
@@ -35,33 +36,37 @@ static struct platform_device rtc_device = {
35 .resource = rtc_resources, 36 .resource = rtc_resources,
36}; 37};
37 38
38static struct plat_sci_port scif0_platform_data = { 39static struct plat_sci_port sci_platform_data = {
39 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
40 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_TE | SCSCR_RE,
43 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCI, 44 .type = PORT_SCI,
42 .irqs = { 23, 23, 23, 0 }, 45 .irqs = { 23, 23, 23, 0 },
43}; 46};
44 47
45static struct platform_device scif0_device = { 48static struct platform_device sci_device = {
46 .name = "sh-sci", 49 .name = "sh-sci",
47 .id = 0, 50 .id = 0,
48 .dev = { 51 .dev = {
49 .platform_data = &scif0_platform_data, 52 .platform_data = &sci_platform_data,
50 }, 53 },
51}; 54};
52 55
53static struct plat_sci_port scif1_platform_data = { 56static struct plat_sci_port scif_platform_data = {
54 .mapbase = 0xffe80000, 57 .mapbase = 0xffe80000,
55 .flags = UPF_BOOT_AUTOCONF, 58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
60 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF, 61 .type = PORT_SCIF,
57 .irqs = { 40, 40, 40, 40 }, 62 .irqs = { 40, 40, 40, 40 },
58}; 63};
59 64
60static struct platform_device scif1_device = { 65static struct platform_device scif_device = {
61 .name = "sh-sci", 66 .name = "sh-sci",
62 .id = 1, 67 .id = 1,
63 .dev = { 68 .dev = {
64 .platform_data = &scif1_platform_data, 69 .platform_data = &scif_platform_data,
65 }, 70 },
66}; 71};
67 72
@@ -210,8 +215,6 @@ static struct platform_device tmu4_device = {
210#endif 215#endif
211 216
212static struct platform_device *sh7750_devices[] __initdata = { 217static struct platform_device *sh7750_devices[] __initdata = {
213 &scif0_device,
214 &scif1_device,
215 &rtc_device, 218 &rtc_device,
216 &tmu0_device, 219 &tmu0_device,
217 &tmu1_device, 220 &tmu1_device,
@@ -226,14 +229,19 @@ static struct platform_device *sh7750_devices[] __initdata = {
226 229
227static int __init sh7750_devices_setup(void) 230static int __init sh7750_devices_setup(void)
228{ 231{
232 if (mach_is_rts7751r2d()) {
233 platform_device_register(&scif_device);
234 } else {
235 platform_device_register(&sci_device);
236 platform_device_register(&scif_device);
237 }
238
229 return platform_add_devices(sh7750_devices, 239 return platform_add_devices(sh7750_devices,
230 ARRAY_SIZE(sh7750_devices)); 240 ARRAY_SIZE(sh7750_devices));
231} 241}
232arch_initcall(sh7750_devices_setup); 242arch_initcall(sh7750_devices_setup);
233 243
234static struct platform_device *sh7750_early_devices[] __initdata = { 244static struct platform_device *sh7750_early_devices[] __initdata = {
235 &scif0_device,
236 &scif1_device,
237 &tmu0_device, 245 &tmu0_device,
238 &tmu1_device, 246 &tmu1_device,
239 &tmu2_device, 247 &tmu2_device,
@@ -247,6 +255,19 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
247 255
248void __init plat_early_device_setup(void) 256void __init plat_early_device_setup(void)
249{ 257{
258 struct platform_device *dev[1];
259
260 if (mach_is_rts7751r2d()) {
261 scif_platform_data.scscr |= SCSCR_CKE1;
262 dev[0] = &scif_device;
263 early_platform_add_devices(dev, 1);
264 } else {
265 dev[0] = &sci_device;
266 early_platform_add_devices(dev, 1);
267 dev[0] = &scif_device;
268 early_platform_add_devices(dev, 1);
269 }
270
250 early_platform_add_devices(sh7750_early_devices, 271 early_platform_add_devices(sh7750_early_devices,
251 ARRAY_SIZE(sh7750_early_devices)); 272 ARRAY_SIZE(sh7750_early_devices));
252} 273}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 48ea8fe85dc5..78bbf232e391 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -129,6 +129,8 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
129static struct plat_sci_port scif0_platform_data = { 129static struct plat_sci_port scif0_platform_data = {
130 .mapbase = 0xfe600000, 130 .mapbase = 0xfe600000,
131 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
133 .scbrr_algo_id = SCBRR_ALGO_2,
132 .type = PORT_SCIF, 134 .type = PORT_SCIF,
133 .irqs = { 52, 53, 55, 54 }, 135 .irqs = { 52, 53, 55, 54 },
134}; 136};
@@ -145,6 +147,8 @@ static struct plat_sci_port scif1_platform_data = {
145 .mapbase = 0xfe610000, 147 .mapbase = 0xfe610000,
146 .flags = UPF_BOOT_AUTOCONF, 148 .flags = UPF_BOOT_AUTOCONF,
147 .type = PORT_SCIF, 149 .type = PORT_SCIF,
150 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
151 .scbrr_algo_id = SCBRR_ALGO_2,
148 .irqs = { 72, 73, 75, 74 }, 152 .irqs = { 72, 73, 75, 74 },
149}; 153};
150 154
@@ -159,6 +163,8 @@ static struct platform_device scif1_device = {
159static struct plat_sci_port scif2_platform_data = { 163static struct plat_sci_port scif2_platform_data = {
160 .mapbase = 0xfe620000, 164 .mapbase = 0xfe620000,
161 .flags = UPF_BOOT_AUTOCONF, 165 .flags = UPF_BOOT_AUTOCONF,
166 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
167 .scbrr_algo_id = SCBRR_ALGO_2,
162 .type = PORT_SCIF, 168 .type = PORT_SCIF,
163 .irqs = { 76, 77, 79, 78 }, 169 .irqs = { 76, 77, 79, 78 },
164}; 170};
@@ -174,6 +180,8 @@ static struct platform_device scif2_device = {
174static struct plat_sci_port scif3_platform_data = { 180static struct plat_sci_port scif3_platform_data = {
175 .mapbase = 0xfe480000, 181 .mapbase = 0xfe480000,
176 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
177 .type = PORT_SCI, 185 .type = PORT_SCI,
178 .irqs = { 80, 81, 82, 0 }, 186 .irqs = { 80, 81, 82, 0 },
179}; 187};
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 14726eef1ce0..f0907995b4c9 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -20,6 +20,7 @@
20#include <linux/vmalloc.h> 20#include <linux/vmalloc.h>
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/prefetch.h>
23#include <asm/page.h> 24#include <asm/page.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25#include <cpu/sq.h> 26#include <cpu/sq.h>
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index b144e8af89dc..cc122b1d3035 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -8,13 +8,13 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
18 18
19# SMP setup 19# SMP setup
20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o 20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
@@ -40,6 +40,7 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o 40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
43pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o
43 44
44obj-y += $(clock-y) 45obj-y += $(clock-y)
45obj-$(CONFIG_SMP) += $(smp-y) 46obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 71291ae201b9..93c646072c1b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,7 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h> 24#include <linux/clkdev.h>
25#include <asm/clock.h> 25#include <asm/clock.h>
26 26
27/* SH7343 registers */ 27/* SH7343 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 7ce5bbcd4084..049dc0628ccc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,7 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h> 24#include <linux/clkdev.h>
25#include <asm/clock.h> 25#include <asm/clock.h>
26 26
27/* SH7366 registers */ 27/* SH7366 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 2030f3d9fac7..9d23a36f0647 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,7 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h> 24#include <linux/clkdev.h>
25#include <asm/clock.h> 25#include <asm/clock.h>
26#include <asm/hwblk.h> 26#include <asm/hwblk.h>
27#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index d3938f0d3702..55493cd5bd8f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -22,7 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <asm/clkdev.h> 25#include <linux/clkdev.h>
26#include <asm/clock.h> 26#include <asm/clock.h>
27#include <asm/hwblk.h> 27#include <asm/hwblk.h>
28#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 2d9700c6b53a..d08fa953c88b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -22,7 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <asm/clkdev.h> 25#include <linux/clkdev.h>
26#include <asm/clock.h> 26#include <asm/clock.h>
27#include <asm/hwblk.h> 27#include <asm/hwblk.h>
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
@@ -48,7 +48,7 @@ static struct clk r_clk = {
48 * Default rate for the root input clock, reset this with clk_set_rate() 48 * Default rate for the root input clock, reset this with clk_set_rate()
49 * from the platform code. 49 * from the platform code.
50 */ 50 */
51struct clk extal_clk = { 51static struct clk extal_clk = {
52 .rate = 33333333, 52 .rate = 33333333,
53}; 53};
54 54
@@ -111,12 +111,21 @@ static struct clk div3_clk = {
111 .parent = &pll_clk, 111 .parent = &pll_clk,
112}; 112};
113 113
114struct clk *main_clks[] = { 114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
115struct clk sh7724_fsimcka_clk = {
116};
117
118struct clk sh7724_fsimckb_clk = {
119};
120
121static struct clk *main_clks[] = {
115 &r_clk, 122 &r_clk,
116 &extal_clk, 123 &extal_clk,
117 &fll_clk, 124 &fll_clk,
118 &pll_clk, 125 &pll_clk,
119 &div3_clk, 126 &div3_clk,
127 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk,
120}; 129};
121 130
122static void div4_kick(struct clk *clk) 131static void div4_kick(struct clk *clk)
@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
155}; 164};
156 165
157enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
158 167
159struct clk div6_clks[DIV6_NR] = { 168static struct clk div6_clks[DIV6_NR] = {
160 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
161 [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
162 [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
163 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
164 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
165}; 172};
166 173
174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
175
176/* Indices are important - they are the actual src selecting values */
177static struct clk *fclkacr_parent[] = {
178 [0] = &div3_clk,
179 [1] = NULL,
180 [2] = &sh7724_fsimcka_clk,
181 [3] = NULL,
182};
183
184static struct clk *fclkbcr_parent[] = {
185 [0] = &div3_clk,
186 [1] = NULL,
187 [2] = &sh7724_fsimckb_clk,
188 [3] = NULL,
189};
190
191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
196};
197
167static struct clk mstp_clks[HWBLK_NR] = { 198static struct clk mstp_clks[HWBLK_NR] = {
168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
240 271
241 /* DIV6 clocks */ 272 /* DIV6 clocks */
242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 273 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 274 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
244 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), 275 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
245 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 276 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
246 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 277 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
247 278
@@ -376,6 +407,9 @@ int __init arch_clk_init(void)
376 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 407 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
377 408
378 if (!ret) 409 if (!ret)
410 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
411
412 if (!ret)
379 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 413 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
380 414
381 return ret; 415 return ret;
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 0a752bd324ac..eedddad13835 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7757 support for the clock framework 4 * SH7757 support for the clock framework
5 * 5 *
6 * Copyright (C) 2009 Renesas Solutions Corp. 6 * Copyright (C) 2009-2010 Renesas Solutions Corp.
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -12,128 +12,156 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/clkdev.h> 15#include <linux/clkdev.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17#include <asm/freq.h> 17#include <asm/freq.h>
18 18
19static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 19/*
20 16, 1, 1, 32, 1, 1, 1, 1 }; 20 * Default rate for the root input clock, reset this with clk_set_rate()
21static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 21 * from the platform code.
22 16, 1, 1, 32, 1, 1, 1, 1 }; 22 */
23static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 23static struct clk extal_clk = {
24 16, 1, 1, 32, 1, 1, 1, 1 }; 24 .rate = 48000000,
25static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 25};
26 16, 1, 1, 32, 1, 1, 1, 1 };
27 26
28static void master_clk_init(struct clk *clk) 27static unsigned long pll_recalc(struct clk *clk)
29{ 28{
30 clk->rate = CONFIG_SH_PCLK_FREQ * 16; 29 int multiplier;
31}
32 30
33static struct clk_ops sh7757_master_clk_ops = { 31 multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
34 .init = master_clk_init,
35};
36 32
37static void module_clk_recalc(struct clk *clk) 33 return clk->parent->rate * multiplier;
38{
39 int idx = __raw_readl(FRQCR) & 0x0000000f;
40 clk->rate = clk->parent->rate / p1fc_divisors[idx];
41} 34}
42 35
43static struct clk_ops sh7757_module_clk_ops = { 36static struct clk_ops pll_clk_ops = {
44 .recalc = module_clk_recalc, 37 .recalc = pll_recalc,
45}; 38};
46 39
47static void bus_clk_recalc(struct clk *clk) 40static struct clk pll_clk = {
48{ 41 .ops = &pll_clk_ops,
49 int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f; 42 .parent = &extal_clk,
50 clk->rate = clk->parent->rate / bfc_divisors[idx]; 43 .flags = CLK_ENABLE_ON_INIT,
51} 44};
52 45
53static struct clk_ops sh7757_bus_clk_ops = { 46static struct clk *clks[] = {
54 .recalc = bus_clk_recalc, 47 &extal_clk,
48 &pll_clk,
55}; 49};
56 50
57static void cpu_clk_recalc(struct clk *clk) 51static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
58{ 52 1, 1, 1, 16, 1, 24, 1, 1 };
59 int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
60 clk->rate = clk->parent->rate / ifc_divisors[idx];
61}
62 53
63static struct clk_ops sh7757_cpu_clk_ops = { 54static struct clk_div_mult_table div4_div_mult_table = {
64 .recalc = cpu_clk_recalc, 55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
65}; 57};
66 58
67static struct clk_ops *sh7757_clk_ops[] = { 59static struct clk_div4_table div4_table = {
68 &sh7757_master_clk_ops, 60 .div_mult_table = &div4_div_mult_table,
69 &sh7757_module_clk_ops,
70 &sh7757_bus_clk_ops,
71 &sh7757_cpu_clk_ops,
72}; 61};
73 62
74void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 63enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
75{
76 if (idx < ARRAY_SIZE(sh7757_clk_ops))
77 *ops = sh7757_clk_ops[idx];
78}
79 64
80static void shyway_clk_recalc(struct clk *clk) 65#define DIV4(_bit, _mask, _flags) \
81{ 66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
82 int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
83 clk->rate = clk->parent->rate / sfc_divisors[idx];
84}
85
86static struct clk_ops sh7757_shyway_clk_ops = {
87 .recalc = shyway_clk_recalc,
88};
89 67
90static struct clk sh7757_shyway_clk = { 68struct clk div4_clks[DIV4_NR] = {
91 .flags = CLK_ENABLE_ON_INIT, 69 /*
92 .ops = &sh7757_shyway_clk_ops, 70 * P clock is always enable, because some P clock modules is used
71 * by Host PC.
72 */
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
93}; 76};
94 77
95/* 78#define MSTPCR0 0xffc80030
96 * Additional sh7757-specific on-chip clocks that aren't already part of the 79#define MSTPCR1 0xffc80034
97 * clock framework 80#define MSTPCR2 0xffc10028
98 */ 81
99static struct clk *sh7757_onchip_clocks[] = { 82enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
100 &sh7757_shyway_clk, 83 MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
84 MSTP_NR };
85
86static struct clk mstp_clks[MSTP_NR] = {
87 /* MSTPCR0 */
88 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
89 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
90
91 /* MSTPCR1 */
92 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
93 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
94 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
95 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
96 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
97 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
98 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
99
100 /* MSTPCR2 */
101 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
101}; 102};
102 103
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 104#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104 105
105static struct clk_lookup lookups[] = { 106static struct clk_lookup lookups[] = {
106 /* main clocks */ 107 /* main clocks */
107 CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk), 108 CLKDEV_CON_ID("extal", &extal_clk),
109 CLKDEV_CON_ID("pll_clk", &pll_clk),
110
111 /* DIV4 clocks */
112 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
113 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
115
116 /* MSTP32 clocks */
117 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
118 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
119 {
120 /* TMU0 */
121 .dev_id = "sh_tmu.0",
122 .con_id = "tmu_fck",
123 .clk = &mstp_clks[MSTP113],
124 }, {
125 /* TMU1 */
126 .dev_id = "sh_tmu.1",
127 .con_id = "tmu_fck",
128 .clk = &mstp_clks[MSTP114],
129 },
130 {
131 /* SCIF4 (But, ID is 2) */
132 .dev_id = "sh-sci.2",
133 .con_id = "sci_fck",
134 .clk = &mstp_clks[MSTP112],
135 }, {
136 /* SCIF3 */
137 .dev_id = "sh-sci.1",
138 .con_id = "sci_fck",
139 .clk = &mstp_clks[MSTP111],
140 }, {
141 /* SCIF2 */
142 .dev_id = "sh-sci.0",
143 .con_id = "sci_fck",
144 .clk = &mstp_clks[MSTP110],
145 },
146 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
147 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
108}; 148};
109 149
110static int __init sh7757_clk_init(void) 150int __init arch_clk_init(void)
111{ 151{
112 struct clk *clk = clk_get(NULL, "master_clk"); 152 int i, ret = 0;
113 int i;
114
115 for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
116 struct clk *clkp = sh7757_onchip_clocks[i];
117 153
118 clkp->parent = clk; 154 for (i = 0; i < ARRAY_SIZE(clks); i++)
119 clk_register(clkp); 155 ret |= clk_register(clks[i]);
120 clk_enable(clkp); 156 for (i = 0; i < ARRAY_SIZE(lookups); i++)
121 } 157 clkdev_add(&lookups[i]);
122 158
123 /* 159 if (!ret)
124 * Now that we have the rest of the clocks registered, we need to 160 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
125 * force the parent clock to propagate so that these clocks will 161 &div4_table);
126 * automatically figure out their rate. We cheat by handing the 162 if (!ret)
127 * parent clock its current rate and forcing child propagation. 163 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
128 */
129 clk_set_rate(clk, clk_get_rate(clk));
130 164
131 clk_put(clk); 165 return ret;
132
133 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
134
135 return 0;
136} 166}
137 167
138arch_initcall(sh7757_clk_init);
139
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 1f1df48008cd..599630fc4d3b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -13,7 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/clkdev.h> 16#include <linux/clkdev.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/freq.h> 18#include <asm/freq.h>
19#include <asm/io.h> 19#include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 62d706350060..8894926479a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -12,7 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/clkdev.h> 15#include <linux/clkdev.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17#include <asm/freq.h> 17#include <asm/freq.h>
18#include <asm/io.h> 18#include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index c3e458aaa2b7..2d960247f3eb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -14,7 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/cpufreq.h> 16#include <linux/cpufreq.h>
17#include <asm/clkdev.h> 17#include <linux/clkdev.h>
18#include <asm/clock.h> 18#include <asm/clock.h>
19#include <asm/freq.h> 19#include <asm/freq.h>
20#include <cpu/sh7785.h> 20#include <cpu/sh7785.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 597c9fbe49c6..42e403be9076 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,7 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/clkdev.h> 16#include <linux/clkdev.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/freq.h> 18#include <asm/freq.h>
19 19
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 236a6282d778..1afdb93b8ccb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2006-2007 Renesas Technology Corp. 6 * Copyright (C) 2006-2007 Renesas Technology Corp.
7 * Copyright (C) 2006-2007 Renesas Solutions Corp. 7 * Copyright (C) 2006-2007 Renesas Solutions Corp.
8 * Copyright (C) 2006-2007 Paul Mundt 8 * Copyright (C) 2006-2010 Paul Mundt
9 * 9 *
10 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
@@ -14,124 +14,183 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <asm/clkdev.h> 17#include <linux/clkdev.h>
18#include <asm/clock.h> 18#include <asm/clock.h>
19#include <asm/freq.h> 19#include <asm/freq.h>
20 20
21static int ifc_divisors[] = { 1, 2, 4 ,6 }; 21/*
22static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; 22 * Default rate for the root input clock, reset this with clk_set_rate()
23static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; 23 * from the platform code.
24static int cfc_divisors[] = { 1, 1, 4, 6 }; 24 */
25 25static struct clk extal_clk = {
26#define IFC_POS 28 26 .rate = 16666666,
27#define IFC_MSK 0x0003
28#define BFC_MSK 0x000f
29#define PFC_MSK 0x000f
30#define CFC_MSK 0x0003
31#define BFC_POS 16
32#define PFC_POS 0
33#define CFC_POS 20
34
35static void master_clk_init(struct clk *clk)
36{
37 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
38}
39
40static struct clk_ops shx3_master_clk_ops = {
41 .init = master_clk_init,
42}; 27};
43 28
44static unsigned long module_clk_recalc(struct clk *clk) 29static unsigned long pll_recalc(struct clk *clk)
45{ 30{
46 int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK); 31 /* PLL1 has a fixed x72 multiplier. */
47 return clk->parent->rate / pfc_divisors[idx]; 32 return clk->parent->rate * 72;
48} 33}
49 34
50static struct clk_ops shx3_module_clk_ops = { 35static struct clk_ops pll_clk_ops = {
51 .recalc = module_clk_recalc, 36 .recalc = pll_recalc,
52}; 37};
53 38
54static unsigned long bus_clk_recalc(struct clk *clk) 39static struct clk pll_clk = {
55{ 40 .ops = &pll_clk_ops,
56 int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK); 41 .parent = &extal_clk,
57 return clk->parent->rate / bfc_divisors[idx]; 42 .flags = CLK_ENABLE_ON_INIT,
58} 43};
59 44
60static struct clk_ops shx3_bus_clk_ops = { 45static struct clk *clks[] = {
61 .recalc = bus_clk_recalc, 46 &extal_clk,
47 &pll_clk,
62}; 48};
63 49
64static unsigned long cpu_clk_recalc(struct clk *clk) 50static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
65{ 51 24, 32, 36, 48 };
66 int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
67 return clk->parent->rate / ifc_divisors[idx];
68}
69 52
70static struct clk_ops shx3_cpu_clk_ops = { 53static struct clk_div_mult_table div4_div_mult_table = {
71 .recalc = cpu_clk_recalc, 54 .divisors = div2,
55 .nr_divisors = ARRAY_SIZE(div2),
72}; 56};
73 57
74static struct clk_ops *shx3_clk_ops[] = { 58static struct clk_div4_table div4_table = {
75 &shx3_master_clk_ops, 59 .div_mult_table = &div4_div_mult_table,
76 &shx3_module_clk_ops,
77 &shx3_bus_clk_ops,
78 &shx3_cpu_clk_ops,
79}; 60};
80 61
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 62enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
82{
83 if (idx < ARRAY_SIZE(shx3_clk_ops))
84 *ops = shx3_clk_ops[idx];
85}
86 63
87static unsigned long shyway_clk_recalc(struct clk *clk) 64#define DIV4(_bit, _mask, _flags) \
88{ 65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
89 int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
90 return clk->parent->rate / cfc_divisors[idx];
91}
92 66
93static struct clk_ops shx3_shyway_clk_ops = { 67struct clk div4_clks[DIV4_NR] = {
94 .recalc = shyway_clk_recalc, 68 [DIV4_P] = DIV4(0, 0x0f80, 0),
69 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
95}; 74};
96 75
97static struct clk shx3_shyway_clk = { 76#define MSTPCR0 0xffc00030
98 .flags = CLK_ENABLE_ON_INIT, 77#define MSTPCR1 0xffc00034
99 .ops = &shx3_shyway_clk_ops, 78
100}; 79enum { MSTP027, MSTP026, MSTP025, MSTP024,
101 80 MSTP009, MSTP008, MSTP003, MSTP002,
102/* 81 MSTP001, MSTP000, MSTP119, MSTP105,
103 * Additional SHx3-specific on-chip clocks that aren't already part of the 82 MSTP104, MSTP_NR };
104 * clock framework 83
105 */ 84static struct clk mstp_clks[MSTP_NR] = {
106static struct clk *shx3_onchip_clocks[] = { 85 /* MSTPCR0 */
107 &shx3_shyway_clk, 86 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
87 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
88 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
89 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
90 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
91 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
92 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
93 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
94 [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
95 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
96
97 /* MSTPCR1 */
98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
108}; 101};
109 102
110#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
111 104
112static struct clk_lookup lookups[] = { 105static struct clk_lookup lookups[] = {
113 /* main clocks */ 106 /* main clocks */
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk), 107 CLKDEV_CON_ID("extal", &extal_clk),
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
109
110 /* DIV4 clocks */
111 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
112 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
113 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
114 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
115 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
116 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
117
118 /* MSTP32 clocks */
119 {
120 /* SCIF3 */
121 .dev_id = "sh-sci.3",
122 .con_id = "sci_fck",
123 .clk = &mstp_clks[MSTP027],
124 }, {
125 /* SCIF2 */
126 .dev_id = "sh-sci.2",
127 .con_id = "sci_fck",
128 .clk = &mstp_clks[MSTP026],
129 }, {
130 /* SCIF1 */
131 .dev_id = "sh-sci.1",
132 .con_id = "sci_fck",
133 .clk = &mstp_clks[MSTP025],
134 }, {
135 /* SCIF0 */
136 .dev_id = "sh-sci.0",
137 .con_id = "sci_fck",
138 .clk = &mstp_clks[MSTP024],
139 },
140 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
141 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
142 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
143 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
144 {
145 /* TMU0 */
146 .dev_id = "sh_tmu.0",
147 .con_id = "tmu_fck",
148 .clk = &mstp_clks[MSTP008],
149 }, {
150 /* TMU1 */
151 .dev_id = "sh_tmu.1",
152 .con_id = "tmu_fck",
153 .clk = &mstp_clks[MSTP008],
154 }, {
155 /* TMU2 */
156 .dev_id = "sh_tmu.2",
157 .con_id = "tmu_fck",
158 .clk = &mstp_clks[MSTP008],
159 }, {
160 /* TMU3 */
161 .dev_id = "sh_tmu.3",
162 .con_id = "tmu_fck",
163 .clk = &mstp_clks[MSTP009],
164 }, {
165 /* TMU4 */
166 .dev_id = "sh_tmu.4",
167 .con_id = "tmu_fck",
168 .clk = &mstp_clks[MSTP009],
169 }, {
170 /* TMU5 */
171 .dev_id = "sh_tmu.5",
172 .con_id = "tmu_fck",
173 .clk = &mstp_clks[MSTP009],
174 },
175 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
176 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
177 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
115}; 178};
116 179
117int __init arch_clk_init(void) 180int __init arch_clk_init(void)
118{ 181{
119 struct clk *clk;
120 int i, ret = 0; 182 int i, ret = 0;
121 183
122 cpg_clk_init(); 184 for (i = 0; i < ARRAY_SIZE(clks); i++)
123 185 ret |= clk_register(clks[i]);
124 clk = clk_get(NULL, "master_clk"); 186 for (i = 0; i < ARRAY_SIZE(lookups); i++)
125 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { 187 clkdev_add(&lookups[i]);
126 struct clk *clkp = shx3_onchip_clocks[i];
127
128 clkp->parent = clk;
129 ret |= clk_register(clkp);
130 }
131
132 clk_put(clk);
133 188
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 189 if (!ret)
190 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
191 &div4_table);
192 if (!ret)
193 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
135 194
136 return ret; 195 return ret;
137} 196}
diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
new file mode 100644
index 000000000000..78c971486b4e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
@@ -0,0 +1,34 @@
1/*
2 * Shared support for SH-X3 interrupt controllers.
3 *
4 * Copyright (C) 2009 - 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/irq.h>
11#include <linux/io.h>
12#include <linux/init.h>
13
14#define INTACK 0xfe4100b8
15#define INTACKCLR 0xfe4100bc
16#define INTC_USERIMASK 0xfe411000
17
18#ifdef CONFIG_INTC_BALANCING
19unsigned int irq_lookup(unsigned int irq)
20{
21 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
22}
23
24void irq_finish(unsigned int irq)
25{
26 __raw_writel(irq2evt(irq), INTACKCLR);
27}
28#endif
29
30static int __init shx3_irq_setup(void)
31{
32 return register_intc_userimask(INTC_USERIMASK);
33}
34arch_initcall(shx3_irq_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index eddc21973fa1..17e6bebfede0 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Performance events support for SH-4A performance counters 2 * Performance events support for SH-4A performance counters
3 * 3 *
4 * Copyright (C) 2009 Paul Mundt 4 * Copyright (C) 2009, 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -22,7 +22,25 @@
22#define CCBR_CMDS (1 << 1) 22#define CCBR_CMDS (1 << 1)
23#define CCBR_PPCE (1 << 0) 23#define CCBR_PPCE (1 << 0)
24 24
25#ifdef CONFIG_CPU_SHX3
26/*
27 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * and PMCTR locations remains tentatively constant. This change remains
29 * wholly undocumented, and was simply found through trial and error.
30 *
31 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
32 * it's unclear when this ceased to be the case. For now we always use
33 * the new location (if future parts keep up with this trend then
34 * scanning for them at runtime also remains a viable option.)
35 *
36 * The gap in the register space also suggests that there are other
37 * undocumented counters, so this will need to be revisited at a later
38 * point in time.
39 */
40#define PPC_PMCAT 0xfc100240
41#else
25#define PPC_PMCAT 0xfc100080 42#define PPC_PMCAT 0xfc100080
43#endif
26 44
27#define PMCAT_OVF3 (1 << 27) 45#define PMCAT_OVF3 (1 << 27)
28#define PMCAT_CNN3 (1 << 26) 46#define PMCAT_CNN3 (1 << 26)
@@ -241,7 +259,7 @@ static void sh4a_pmu_enable_all(void)
241} 259}
242 260
243static struct sh_pmu sh4a_pmu = { 261static struct sh_pmu sh4a_pmu = {
244 .name = "SH-4A", 262 .name = "sh4a",
245 .num_events = 2, 263 .num_events = 2,
246 .event_map = sh4a_event_map, 264 .event_map = sh4a_event_map,
247 .max_events = ARRAY_SIZE(sh4a_general_events), 265 .max_events = ARRAY_SIZE(sh4a_general_events),
@@ -266,4 +284,4 @@ static int __init sh4a_pmu_init(void)
266 284
267 return register_sh_pmu(&sh4a_pmu); 285 return register_sh_pmu(&sh4a_pmu);
268} 286}
269arch_initcall(sh4a_pmu_init); 287early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index ed23b155c097..4c74bd04bba4 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -1,11 +1,11 @@
1/* 1/*
2 * SH7757 (A0 step) Pinmux 2 * SH7757 (B0 step) Pinmux
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009-2010 Renesas Solutions Corp.
5 * 5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 * 7 *
8 * Based on SH7757 Pinmux 8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm 9 * Copyright (C) 2008 Magnus Damm
10 * 10 *
11 * This file is subject to the terms and conditions of the GNU General Public 11 * This file is subject to the terms and conditions of the GNU General Public
@@ -40,27 +40,27 @@ enum {
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, 40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, 41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA, 42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
43 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 43 PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, 44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, 45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, 46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
47 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 47 PTL6_DATA, PTL5_DATA, PTL4_DATA,
48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, 48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
49 PTM6_DATA, PTM5_DATA, PTM4_DATA, 49 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, 50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
51 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 51 PTN6_DATA, PTN5_DATA, PTN4_DATA,
52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, 52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, 53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA, 54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
55 PTP6_DATA, PTP5_DATA, PTP4_DATA, 55 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, 56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, 57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, 58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, 60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, 61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, 62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
63 PTT5_DATA, PTT4_DATA, 63 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, 64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, 65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, 66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
@@ -95,27 +95,27 @@ enum {
95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, 95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN, 96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN, 97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
98 PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN, 98 PTJ6_IN, PTJ5_IN, PTJ4_IN,
99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, 99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, 100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, 101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
102 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, 102 PTL6_IN, PTL5_IN, PTL4_IN,
103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, 103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
104 PTM6_IN, PTM5_IN, PTM4_IN, 104 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, 105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
106 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, 106 PTN6_IN, PTN5_IN, PTN4_IN,
107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, 107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN, 108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN, 109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
110 PTP6_IN, PTP5_IN, PTP4_IN, 110 PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, 111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
112 PTQ6_IN, PTQ5_IN, PTQ4_IN, 112 PTQ6_IN, PTQ5_IN, PTQ4_IN,
113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, 113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, 114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, 115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, 116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, 117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
118 PTT5_IN, PTT4_IN, 118 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, 119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, 120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, 121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
@@ -132,16 +132,43 @@ enum {
132 PINMUX_INPUT_END, 132 PINMUX_INPUT_END,
133 133
134 PINMUX_INPUT_PULLUP_BEGIN, 134 PINMUX_INPUT_PULLUP_BEGIN,
135 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
136 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
137 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
138 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
139 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
140 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
141 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
142 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
143 PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU,
144 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
145 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
146 PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU,
147 PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
148 PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
149 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
150 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
151 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
152 PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
153 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
154 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
155 PTN4_IN_PU,
156 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
157 PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
158 PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
159 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
160 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
135 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, 161 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
136 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, 162 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
137 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, 163 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
138 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, 164 PTV3_IN_PU, PTV2_IN_PU,
139 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, 165 PTW1_IN_PU, PTW0_IN_PU,
140 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
141 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, 166 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
142 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, 167 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
143 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, 168 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
144 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, 169 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
170 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
171 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
145 PINMUX_INPUT_PULLUP_END, 172 PINMUX_INPUT_PULLUP_END,
146 173
147 PINMUX_OUTPUT_BEGIN, 174 PINMUX_OUTPUT_BEGIN,
@@ -163,27 +190,27 @@ enum {
163 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, 190 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
164 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT, 191 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
165 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT, 192 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
166 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, 193 PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
167 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, 194 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
168 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, 195 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
169 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, 196 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
170 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, 197 PTL6_OUT, PTL5_OUT, PTL4_OUT,
171 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, 198 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
172 PTM6_OUT, PTM5_OUT, PTM4_OUT, 199 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
173 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, 200 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
174 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, 201 PTN6_OUT, PTN5_OUT, PTN4_OUT,
175 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, 202 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
176 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT, 203 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
177 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT, 204 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
178 PTP6_OUT, PTP5_OUT, PTP4_OUT, 205 PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
179 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, 206 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
180 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, 207 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
181 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, 208 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
182 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, 209 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
183 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, 210 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
184 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, 211 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
185 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, 212 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
186 PTT5_OUT, PTT4_OUT, 213 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
187 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, 214 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
188 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, 215 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
189 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, 216 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
@@ -218,27 +245,27 @@ enum {
218 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, 245 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
219 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN, 246 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
220 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN, 247 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
221 PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN, 248 PTJ6_FN, PTJ5_FN, PTJ4_FN,
222 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, 249 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
223 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, 250 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
224 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, 251 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
225 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, 252 PTL6_FN, PTL5_FN, PTL4_FN,
226 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, 253 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
227 PTM6_FN, PTM5_FN, PTM4_FN, 254 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
228 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, 255 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
229 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, 256 PTN6_FN, PTN5_FN, PTN4_FN,
230 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, 257 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
231 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN, 258 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
232 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN, 259 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
233 PTP6_FN, PTP5_FN, PTP4_FN, 260 PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
234 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, 261 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
235 PTQ6_FN, PTQ5_FN, PTQ4_FN, 262 PTQ6_FN, PTQ5_FN, PTQ4_FN,
236 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, 263 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
237 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, 264 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
238 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, 265 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
239 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, 266 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
240 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, 267 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
241 PTT5_FN, PTT4_FN, 268 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
242 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, 269 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
243 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, 270 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
244 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, 271 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
@@ -253,181 +280,248 @@ enum {
253 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, 280 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
254 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, 281 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
255 282
256 PS0_15_FN1, PS0_15_FN3, 283 PS0_15_FN1, PS0_15_FN2,
257 PS0_14_FN1, PS0_14_FN3, 284 PS0_14_FN1, PS0_14_FN2,
258 PS0_13_FN1, PS0_13_FN3, 285 PS0_13_FN1, PS0_13_FN2,
259 PS0_12_FN1, PS0_12_FN3, 286 PS0_12_FN1, PS0_12_FN2,
287 PS0_11_FN1, PS0_11_FN2,
288 PS0_10_FN1, PS0_10_FN2,
289 PS0_9_FN1, PS0_9_FN2,
290 PS0_8_FN1, PS0_8_FN2,
260 PS0_7_FN1, PS0_7_FN2, 291 PS0_7_FN1, PS0_7_FN2,
261 PS0_6_FN1, PS0_6_FN2, 292 PS0_6_FN1, PS0_6_FN2,
262 PS0_5_FN1, PS0_5_FN2, 293 PS0_5_FN1, PS0_5_FN2,
263 PS0_4_FN1, PS0_4_FN2, 294 PS0_4_FN1, PS0_4_FN2,
264 PS0_3_FN1, PS0_3_FN2, 295 PS0_3_FN1, PS0_3_FN2,
265 PS0_2_FN1, PS0_2_FN2, 296 PS0_2_FN1, PS0_2_FN2,
266 PS0_1_FN1, PS0_1_FN2,
267 297
268 PS1_7_FN1, PS1_7_FN3, 298 PS1_10_FN1, PS1_10_FN2,
269 PS1_6_FN1, PS1_6_FN3, 299 PS1_9_FN1, PS1_9_FN2,
300 PS1_8_FN1, PS1_8_FN2,
301 PS1_2_FN1, PS1_2_FN2,
302
303 PS2_13_FN1, PS2_13_FN2,
304 PS2_12_FN1, PS2_12_FN2,
305 PS2_7_FN1, PS2_7_FN2,
306 PS2_6_FN1, PS2_6_FN2,
307 PS2_5_FN1, PS2_5_FN2,
308 PS2_4_FN1, PS2_4_FN2,
309 PS2_2_FN1, PS2_2_FN2,
310
311 PS3_15_FN1, PS3_15_FN2,
312 PS3_14_FN1, PS3_14_FN2,
313 PS3_13_FN1, PS3_13_FN2,
314 PS3_12_FN1, PS3_12_FN2,
315 PS3_11_FN1, PS3_11_FN2,
316 PS3_10_FN1, PS3_10_FN2,
317 PS3_9_FN1, PS3_9_FN2,
318 PS3_8_FN1, PS3_8_FN2,
319 PS3_7_FN1, PS3_7_FN2,
320 PS3_2_FN1, PS3_2_FN2,
321 PS3_1_FN1, PS3_1_FN2,
270 322
271 PS2_13_FN1, PS2_13_FN3,
272 PS2_12_FN1, PS2_12_FN3,
273 PS2_1_FN1, PS2_1_FN2,
274 PS2_0_FN1, PS2_0_FN2,
275
276 PS4_15_FN1, PS4_15_FN2,
277 PS4_14_FN1, PS4_14_FN2, 323 PS4_14_FN1, PS4_14_FN2,
278 PS4_13_FN1, PS4_13_FN2, 324 PS4_13_FN1, PS4_13_FN2,
279 PS4_12_FN1, PS4_12_FN2, 325 PS4_12_FN1, PS4_12_FN2,
280 PS4_11_FN1, PS4_11_FN2,
281 PS4_10_FN1, PS4_10_FN2, 326 PS4_10_FN1, PS4_10_FN2,
282 PS4_9_FN1, PS4_9_FN2, 327 PS4_9_FN1, PS4_9_FN2,
328 PS4_8_FN1, PS4_8_FN2,
329 PS4_4_FN1, PS4_4_FN2,
283 PS4_3_FN1, PS4_3_FN2, 330 PS4_3_FN1, PS4_3_FN2,
284 PS4_2_FN1, PS4_2_FN2, 331 PS4_2_FN1, PS4_2_FN2,
285 PS4_1_FN1, PS4_1_FN2, 332 PS4_1_FN1, PS4_1_FN2,
286 PS4_0_FN1, PS4_0_FN2, 333 PS4_0_FN1, PS4_0_FN2,
287 334
335 PS5_11_FN1, PS5_11_FN2,
336 PS5_10_FN1, PS5_10_FN2,
288 PS5_9_FN1, PS5_9_FN2, 337 PS5_9_FN1, PS5_9_FN2,
289 PS5_8_FN1, PS5_8_FN2, 338 PS5_8_FN1, PS5_8_FN2,
290 PS5_7_FN1, PS5_7_FN2, 339 PS5_7_FN1, PS5_7_FN2,
291 PS5_6_FN1, PS5_6_FN2, 340 PS5_6_FN1, PS5_6_FN2,
292 PS5_5_FN1, PS5_5_FN2, 341 PS5_5_FN1, PS5_5_FN2,
293 PS5_4_FN1, PS5_4_FN2, 342 PS5_4_FN1, PS5_4_FN2,
294 343 PS5_3_FN1, PS5_3_FN2,
295 /* AN15 to 8 : EVENT15 to 8 */ 344 PS5_2_FN1, PS5_2_FN2,
296 PS6_7_FN_AN, PS6_7_FN_EV, 345
297 PS6_6_FN_AN, PS6_6_FN_EV, 346 PS6_15_FN1, PS6_15_FN2,
298 PS6_5_FN_AN, PS6_5_FN_EV, 347 PS6_14_FN1, PS6_14_FN2,
299 PS6_4_FN_AN, PS6_4_FN_EV, 348 PS6_13_FN1, PS6_13_FN2,
300 PS6_3_FN_AN, PS6_3_FN_EV, 349 PS6_12_FN1, PS6_12_FN2,
301 PS6_2_FN_AN, PS6_2_FN_EV, 350 PS6_11_FN1, PS6_11_FN2,
302 PS6_1_FN_AN, PS6_1_FN_EV, 351 PS6_10_FN1, PS6_10_FN2,
303 PS6_0_FN_AN, PS6_0_FN_EV, 352 PS6_9_FN1, PS6_9_FN2,
304 353 PS6_8_FN1, PS6_8_FN2,
354 PS6_7_FN1, PS6_7_FN2,
355 PS6_6_FN1, PS6_6_FN2,
356 PS6_5_FN1, PS6_5_FN2,
357 PS6_4_FN1, PS6_4_FN2,
358 PS6_3_FN1, PS6_3_FN2,
359 PS6_2_FN1, PS6_2_FN2,
360 PS6_1_FN1, PS6_1_FN2,
361 PS6_0_FN1, PS6_0_FN2,
362
363 PS7_15_FN1, PS7_15_FN2,
364 PS7_14_FN1, PS7_14_FN2,
365 PS7_13_FN1, PS7_13_FN2,
366 PS7_12_FN1, PS7_12_FN2,
367 PS7_11_FN1, PS7_11_FN2,
368 PS7_10_FN1, PS7_10_FN2,
369 PS7_9_FN1, PS7_9_FN2,
370 PS7_8_FN1, PS7_8_FN2,
371 PS7_7_FN1, PS7_7_FN2,
372 PS7_6_FN1, PS7_6_FN2,
373 PS7_5_FN1, PS7_5_FN2,
374 PS7_4_FN1, PS7_4_FN2,
375
376 PS8_15_FN1, PS8_15_FN2,
377 PS8_14_FN1, PS8_14_FN2,
378 PS8_13_FN1, PS8_13_FN2,
379 PS8_12_FN1, PS8_12_FN2,
380 PS8_11_FN1, PS8_11_FN2,
381 PS8_10_FN1, PS8_10_FN2,
382 PS8_9_FN1, PS8_9_FN2,
383 PS8_8_FN1, PS8_8_FN2,
305 PINMUX_FUNCTION_END, 384 PINMUX_FUNCTION_END,
306 385
307 PINMUX_MARK_BEGIN, 386 PINMUX_MARK_BEGIN,
308 /* PTA (mobule: LBSC, CPG, LPC) */ 387 /* PTA (mobule: LBSC, RGMII) */
309 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK, 388 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK,
310 MD10_MARK, MD9_MARK, MD8_MARK,
311 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
312 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
313
314 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
315 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
316 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
317 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK, 389 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK,
318 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
319 WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK,
320 LPC_SPIEN_MARK, BASEL_MARK,
321 390
322 /* PTC (mobule: SD) */ 391 /* PTB (mobule: INTC, ONFI, TMU) */
323 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, 392 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK,
324 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, 393 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK,
394 ON_NRE_MARK, ON_NWE_MARK, ON_NWP_MARK, ON_NCE0_MARK,
395 ON_R_B0_MARK, ON_ALE_MARK, ON_CLE_MARK, TCLK_MARK,
325 396
326 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ 397 /* PTC (mobule: IRQ, PWMU) */
327 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK, 398 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK,
328 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, 399 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
329 MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK, 400 PWMU0_MARK, PWMU1_MARK, PWMU2_MARK, PWMU3_MARK,
330 MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK, 401 PWMU4_MARK, PWMU5_MARK,
331 402
332 /* PTE (mobule: EtherC) */ 403 /* PTD (mobule: SPI0, DMAC) */
333 ET0_CRS_DV_MARK, ET0_TXD1_MARK, 404 SP0_MOSI_MARK, SP0_MISO_MARK, SP0_SCK_MARK, SP0_SCK_FB_MARK,
334 ET0_TXD0_MARK, ET0_TX_EN_MARK, 405 SP0_SS0_MARK, SP0_SS1_MARK, SP0_SS2_MARK, SP0_SS3_MARK,
335 ET0_REF_CLK_MARK, ET0_RXD1_MARK, 406 DREQ0_MARK, DACK0_MARK, TEND0_MARK,
336 ET0_RXD0_MARK, ET0_RX_ER_MARK, 407
337 408 /* PTE (mobule: RMII) */
338 /* PTF (mobule: EtherC) */ 409 RMII0_CRS_DV_MARK, RMII0_TXD1_MARK,
339 ET1_CRS_DV_MARK, ET1_TXD1_MARK, 410 RMII0_TXD0_MARK, RMII0_TXEN_MARK,
340 ET1_TXD0_MARK, ET1_TX_EN_MARK, 411 RMII0_REFCLK_MARK, RMII0_RXD1_MARK,
341 ET1_REF_CLK_MARK, ET1_RXD1_MARK, 412 RMII0_RXD0_MARK, RMII0_RX_ER_MARK,
342 ET1_RXD0_MARK, ET1_RX_ER_MARK, 413
343 414 /* PTF (mobule: RMII, SerMux) */
344 /* PTG (mobule: SYSTEM, PWMX, LPC) */ 415 RMII1_CRS_DV_MARK, RMII1_TXD1_MARK,
345 STATUS0_MARK, STATUS1_MARK, 416 RMII1_TXD0_MARK, RMII1_TXEN_MARK,
346 PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK, 417 RMII1_REFCLK_MARK, RMII1_RXD1_MARK,
347 SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK, 418 RMII1_RXD0_MARK, RMII1_RX_ER_MARK,
348 419 RAC_RI_MARK,
349 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ 420
350 TCLK_MARK, RXD4_MARK, TXD4_MARK, 421 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
422 BOOTFMS_MARK, BOOTWP_MARK, A25_MARK, A24_MARK,
423 SERIRQ_MARK, WDTOVF_MARK, LPCPD_MARK, LDRQ_MARK,
424 MMCCLK_MARK, MMCCMD_MARK,
425
426 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
351 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK, 427 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK,
352 SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK, 428 SP1_SS0_MARK, SP1_SS1_MARK, WP_MARK, FMS0_MARK,
429 TEND1_MARK, DREQ1_MARK, DACK1_MARK, ADTRG1_MARK,
430 ADTRG0_MARK,
353 431
354 /* PTI (mobule: INTC) */ 432 /* PTI (mobule: LBSC, SDHI) */
355 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, 433 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
356 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, 434 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
435 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK,
436 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK,
357 437
358 /* PTJ (mobule: SCIF234, SERMUX) */ 438 /* PTJ (mobule: SCIF234) */
359 RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK, 439 RTS3_MARK, CTS3_MARK, TXD3_MARK, RXD3_MARK,
360 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, 440 RTS4_MARK, RXD4_MARK, TXD4_MARK,
361 441
362 /* PTK (mobule: SERMUX) */ 442 /* PTK (mobule: SERMUX, LBSC, SCIF) */
363 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK, 443 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK,
364 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK, 444 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, CLKOUT_MARK,
445 SCK2_MARK, SCK4_MARK, SCK3_MARK,
365 446
366 /* PTL (mobule: SERMUX) */ 447 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
367 RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, 448 RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, RAC_DTR_MARK,
368 RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK, 449 RAC_DSR_MARK, RAC_DCD_MARK, RAC_TXD_MARK, RXD2_MARK,
450 CS5_MARK, CS6_MARK, AUDSYNC_MARK, AUDCK_MARK,
451 TXD2_MARK,
369 452
370 /* PTM (mobule: IIC, LPC) */ 453 /* PTM (mobule: LBSC, IIC) */
454 CS4_MARK, RD_MARK, WE0_MARK, CS0_MARK,
371 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK, 455 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK,
372 WP_MARK, FMS0_MARK, FMS1_MARK,
373 456
374 /* PTN (mobule: SCIF234, EVC) */ 457 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
375 SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK, 458 VBUS_EN_MARK, VBUS_OC_MARK, JMCTCK_MARK, JMCTMS_MARK,
376 CTS4_MARK, CTS3_MARK, CTS2_MARK, 459 JMCTDO_MARK, JMCTDI_MARK, JMCTRST_MARK,
377 EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK, 460 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, SGPIO1_DI_MARK,
378 EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK, 461 SGPIO1_DO_MARK, SUB_CLKIN_MARK,
379 462
380 /* PTO (mobule: SGPIO) */ 463 /* PTO (mobule: SGPIO, SerMux) */
381 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, 464 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, SGPIO0_DI_MARK,
382 SGPIO0_DI_MARK, SGPIO0_DO_MARK, 465 SGPIO0_DO_MARK, SGPIO2_CLK_MARK, SGPIO2_LOAD_MARK,
383 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, 466 SGPIO2_DI_MARK, SGPIO2_DO_MARK,
384 SGPIO1_DI_MARK, SGPIO1_DO_MARK, 467 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK,
385
386 /* PTP (mobule: JMC, SCIF234) */
387 JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK,
388 JMCRST_MARK, SCK4_MARK, SCK3_MARK,
389 468
390 /* PTQ (mobule: LPC) */ 469 /* PTQ (mobule: LPC) */
391 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK, 470 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK,
392 LFRAME_MARK, LRESET_MARK, LCLK_MARK, 471 LFRAME_MARK, LRESET_MARK, LCLK_MARK,
393 472
394 /* PTR (mobule: GRA, IIC) */ 473 /* PTR (mobule: GRA, IIC) */
395 DDC3_MARK, DDC2_MARK, 474 DDC3_MARK, DDC2_MARK, SDA2_MARK, SCL2_MARK,
396 SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK,
397 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK, 475 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK,
476 SDA8_MARK, SCL8_MARK,
398 477
399 /* PTS (mobule: GRA, IIC) */ 478 /* PTS (mobule: GRA, IIC) */
400 DDC1_MARK, DDC0_MARK, 479 DDC1_MARK, DDC0_MARK, SDA5_MARK, SCL5_MARK,
401 SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK,
402 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK, 480 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK,
481 SDA9_MARK, SCL9_MARK,
403 482
404 /* PTT (mobule: SYSTEM, PWMX) */ 483 /* PTT (mobule: PWMX, AUD) */
405 AUDSYNC_MARK, AUDCK_MARK, 484 PWMX7_MARK, PWMX6_MARK, PWMX5_MARK, PWMX4_MARK,
406 AUDATA3_MARK, AUDATA2_MARK, 485 PWMX3_MARK, PWMX2_MARK, PWMX1_MARK, PWMX0_MARK,
407 AUDATA1_MARK, AUDATA0_MARK, 486 AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
408 PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK, 487 STATUS1_MARK, STATUS0_MARK,
409 488
410 /* PTU (mobule: LBSC, DMAC) */ 489 /* PTU (mobule: LPC, APM) */
411 CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK, 490 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
412 RD_MARK, WE0_MARK, A25_MARK, A24_MARK, 491 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
413 DREQ0_MARK, DACK0_MARK, 492 APMONCTL_O_MARK, APMPWBTOUT_O_MARK, APMSCI_O_MARK,
493 APMVDDON_MARK, APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK,
494 APMS3N_MARK,
414 495
415 /* PTV (mobule: LBSC, DMAC) */ 496 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
416 A23_MARK, A22_MARK, A21_MARK, A20_MARK, 497 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
417 A19_MARK, A18_MARK, A17_MARK, A16_MARK, 498 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
418 TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK, 499 COM2_RI_MARK, R_SPI_MOSI_MARK, R_SPI_MISO_MARK,
500 R_SPI_RSPCK_MARK, R_SPI_SSL0_MARK, R_SPI_SSL1_MARK,
501 EVENT7_MARK, EVENT6_MARK, VBIOS_DI_MARK, VBIOS_DO_MARK,
502 VBIOS_CLK_MARK, VBIOS_CS_MARK,
419 503
420 /* PTW (mobule: LBSC) */ 504 /* PTW (mobule: LBSC, EVC, SCIF) */
421 A15_MARK, A14_MARK, A13_MARK, A12_MARK, 505 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
422 A11_MARK, A10_MARK, A9_MARK, A8_MARK, 506 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
507 EVENT5_MARK, EVENT4_MARK, EVENT3_MARK, EVENT2_MARK,
508 EVENT1_MARK, EVENT0_MARK, CTS4_MARK, CTS2_MARK,
423 509
424 /* PTX (mobule: LBSC) */ 510 /* PTX (mobule: LBSC, SCIF, SIM) */
425 A7_MARK, A6_MARK, A5_MARK, A4_MARK, 511 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
426 A3_MARK, A2_MARK, A1_MARK, A0_MARK, 512 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
513 RTS2_MARK, SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
427 514
428 /* PTY (mobule: LBSC) */ 515 /* PTY (mobule: LBSC) */
429 D7_MARK, D6_MARK, D5_MARK, D4_MARK, 516 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
430 D3_MARK, D2_MARK, D1_MARK, D0_MARK, 517 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
518
519 /* PTZ (mobule: eMMC, ONFI) */
520 MMCDAT7_MARK, MMCDAT6_MARK, MMCDAT5_MARK, MMCDAT4_MARK,
521 MMCDAT3_MARK, MMCDAT2_MARK, MMCDAT1_MARK, MMCDAT0_MARK,
522 ON_DQ7_MARK, ON_DQ6_MARK, ON_DQ5_MARK, ON_DQ4_MARK,
523 ON_DQ3_MARK, ON_DQ2_MARK, ON_DQ1_MARK, ON_DQ0_MARK,
524
431 PINMUX_MARK_END, 525 PINMUX_MARK_END,
432}; 526};
433 527
@@ -473,6 +567,8 @@ static pinmux_enum_t pinmux_data[] = {
473 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), 567 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
474 568
475 /* PTE GPIO */ 569 /* PTE GPIO */
570 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
571 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
476 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), 572 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
477 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), 573 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
478 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), 574 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
@@ -521,7 +617,6 @@ static pinmux_enum_t pinmux_data[] = {
521 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT), 617 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
522 618
523 /* PTJ GPIO */ 619 /* PTJ GPIO */
524 PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
525 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), 620 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
526 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), 621 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
527 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), 622 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
@@ -541,7 +636,6 @@ static pinmux_enum_t pinmux_data[] = {
541 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), 636 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
542 637
543 /* PTL GPIO */ 638 /* PTL GPIO */
544 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
545 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), 639 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
546 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), 640 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
547 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), 641 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
@@ -560,7 +654,6 @@ static pinmux_enum_t pinmux_data[] = {
560 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), 654 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
561 655
562 /* PTN GPIO */ 656 /* PTN GPIO */
563 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
564 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), 657 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
565 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), 658 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
566 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), 659 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
@@ -609,6 +702,8 @@ static pinmux_enum_t pinmux_data[] = {
609 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), 702 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
610 703
611 /* PTT GPIO */ 704 /* PTT GPIO */
705 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
706 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
612 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), 707 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
613 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), 708 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
614 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), 709 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
@@ -677,186 +772,204 @@ static pinmux_enum_t pinmux_data[] = {
677 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), 772 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
678 773
679 /* PTA FN */ 774 /* PTA FN */
680 PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN), 775 PINMUX_DATA(BS_MARK, PTA7_FN),
681 PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN), 776 PINMUX_DATA(RDWR_MARK, PTA6_FN),
682 PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN), 777 PINMUX_DATA(WE1_MARK, PTA5_FN),
683 PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN), 778 PINMUX_DATA(RDY_MARK, PTA4_FN),
684 PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN), 779 PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
685 PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN), 780 PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
686 PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN), 781 PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
687 PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN), 782 PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
688 PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
689 PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
690 PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
691 PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
692 783
693 /* PTB FN */ 784 /* PTB FN */
694 PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN), 785 PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
695 PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN), 786 PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
696 PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN), 787 PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
697 PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN), 788 PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
698 PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN), 789 PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
699 PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN), 790 PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
700 PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN), 791 PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
701 PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN), 792 PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
702 PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN), 793 PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
703 PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN), 794 PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
704 PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN), 795 PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
705 PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN), 796 PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
706 PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN), 797 PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
707 PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN), 798 PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
708 PINMUX_DATA(D8_MARK, PTB0_FN), 799 PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
800 PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
709 801
710 /* PTC FN */ 802 /* PTC FN */
711 PINMUX_DATA(SD_WP_MARK, PTC7_FN), 803 PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
712 PINMUX_DATA(SD_CD_MARK, PTC6_FN), 804 PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
713 PINMUX_DATA(SD_CLK_MARK, PTC5_FN), 805 PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
714 PINMUX_DATA(SD_CMD_MARK, PTC4_FN), 806 PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
715 PINMUX_DATA(SD_D3_MARK, PTC3_FN), 807 PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
716 PINMUX_DATA(SD_D2_MARK, PTC2_FN), 808 PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
717 PINMUX_DATA(SD_D1_MARK, PTC1_FN), 809 PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
718 PINMUX_DATA(SD_D0_MARK, PTC0_FN), 810 PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
811 PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
812 PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
813 PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
814 PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
815 PINMUX_DATA(IRQ1_MARK, PTC1_FN),
816 PINMUX_DATA(IRQ0_MARK, PTC0_FN),
719 817
720 /* PTD FN */ 818 /* PTD FN */
721 PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN), 819 PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
722 PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN), 820 PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
723 PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN), 821 PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
724 PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN), 822 PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
725 PINMUX_DATA(IRQ5_MARK, PTD5_FN), 823 PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
726 PINMUX_DATA(IRQ4_MARK, PTD4_FN), 824 PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
727 PINMUX_DATA(IRQ3_MARK, PTD3_FN), 825 PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
728 PINMUX_DATA(IRQ2_MARK, PTD2_FN), 826 PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
729 PINMUX_DATA(IRQ1_MARK, PTD1_FN), 827 PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
730 PINMUX_DATA(IRQ0_MARK, PTD0_FN), 828 PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
829 PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
731 830
732 /* PTE FN */ 831 /* PTE FN */
733 PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN), 832 PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
734 PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN), 833 PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
735 PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN), 834 PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
736 PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN), 835 PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
737 PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN), 836 PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
738 PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN), 837 PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
739 PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN), 838 PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
740 PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN), 839 PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
741 840
742 /* PTF FN */ 841 /* PTF FN */
743 PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN), 842 PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
744 PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN), 843 PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
745 PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN), 844 PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
746 PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN), 845 PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
747 PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN), 846 PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
748 PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN), 847 PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
749 PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN), 848 PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
750 PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN), 849 PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
850 PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
751 851
752 /* PTG FN */ 852 /* PTG FN */
753 PINMUX_DATA(PWX0_MARK, PTG7_FN), 853 PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
754 PINMUX_DATA(PWX1_MARK, PTG6_FN), 854 PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
755 PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN), 855 PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
756 PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN), 856 PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
757 PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN), 857 PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
758 PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN), 858 PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
759 PINMUX_DATA(SERIRQ_MARK, PTG3_FN), 859 PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
760 PINMUX_DATA(CLKRUN_MARK, PTG2_FN), 860 PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
761 PINMUX_DATA(LPCPD_MARK, PTG1_FN), 861 PINMUX_DATA(LPCPD_MARK, PTG1_FN),
762 PINMUX_DATA(LDRQ_MARK, PTG0_FN), 862 PINMUX_DATA(LDRQ_MARK, PTG0_FN),
763 863
764 /* PTH FN */ 864 /* PTH FN */
765 PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN), 865 PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
766 PINMUX_DATA(SP1_MISO_MARK, PTH6_FN), 866 PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
767 PINMUX_DATA(SP1_SCK_MARK, PTH5_FN), 867 PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
768 PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN), 868 PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
869 PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
870 PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
871 PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
872 PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
769 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN), 873 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
770 PINMUX_DATA(TCLK_MARK, PTH2_FN), 874 PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
771 PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN), 875 PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
772 PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN), 876 PINMUX_DATA(WP_MARK, PTH1_FN),
773 PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN), 877 PINMUX_DATA(FMS0_MARK, PTH0_FN),
774 PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
775 878
776 /* PTI FN */ 879 /* PTI FN */
777 PINMUX_DATA(IRQ15_MARK, PTI7_FN), 880 PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
778 PINMUX_DATA(IRQ14_MARK, PTI6_FN), 881 PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
779 PINMUX_DATA(IRQ13_MARK, PTI5_FN), 882 PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
780 PINMUX_DATA(IRQ12_MARK, PTI4_FN), 883 PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
781 PINMUX_DATA(IRQ11_MARK, PTI3_FN), 884 PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
782 PINMUX_DATA(IRQ10_MARK, PTI2_FN), 885 PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
783 PINMUX_DATA(IRQ9_MARK, PTI1_FN), 886 PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
784 PINMUX_DATA(IRQ8_MARK, PTI0_FN), 887 PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
888 PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
889 PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
890 PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
891 PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
892 PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
893 PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
894 PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
895 PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
785 896
786 /* PTJ FN */ 897 /* PTJ FN */
787 PINMUX_DATA(RXD3_MARK, PTJ7_FN), 898 PINMUX_DATA(RTS3_MARK, PTJ6_FN),
788 PINMUX_DATA(TXD3_MARK, PTJ6_FN), 899 PINMUX_DATA(CTS3_MARK, PTJ5_FN),
789 PINMUX_DATA(RXD2_MARK, PTJ5_FN), 900 PINMUX_DATA(TXD3_MARK, PTJ4_FN),
790 PINMUX_DATA(TXD2_MARK, PTJ4_FN), 901 PINMUX_DATA(RXD3_MARK, PTJ3_FN),
791 PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN), 902 PINMUX_DATA(RTS4_MARK, PTJ2_FN),
792 PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN), 903 PINMUX_DATA(RXD4_MARK, PTJ1_FN),
793 PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN), 904 PINMUX_DATA(TXD4_MARK, PTJ0_FN),
794 PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
795 905
796 /* PTK FN */ 906 /* PTK FN */
797 PINMUX_DATA(COM2_TXD_MARK, PTK7_FN), 907 PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
908 PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
798 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN), 909 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
799 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN), 910 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
800 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN), 911 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
801 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN), 912 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
802 PINMUX_DATA(COM2_DSR_MARK, PTK2_FN), 913 PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
803 PINMUX_DATA(COM2_DCD_MARK, PTK1_FN), 914 PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
804 PINMUX_DATA(COM2_RI_MARK, PTK0_FN), 915 PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
916 PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
917 PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
805 918
806 /* PTL FN */ 919 /* PTL FN */
807 PINMUX_DATA(RAC_TXD_MARK, PTL7_FN), 920 PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
808 PINMUX_DATA(RAC_RXD_MARK, PTL6_FN), 921 PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
809 PINMUX_DATA(RAC_RTS_MARK, PTL5_FN), 922 PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
810 PINMUX_DATA(RAC_CTS_MARK, PTL4_FN), 923 PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
924 PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
925 PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
811 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN), 926 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
812 PINMUX_DATA(RAC_DSR_MARK, PTL2_FN), 927 PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
813 PINMUX_DATA(RAC_DCD_MARK, PTL1_FN), 928 PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
814 PINMUX_DATA(RAC_RI_MARK, PTL0_FN), 929 PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
930 PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
931 PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
932 PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
815 933
816 /* PTM FN */ 934 /* PTM FN */
817 PINMUX_DATA(WP_MARK, PTM6_FN), 935 PINMUX_DATA(CS4_MARK, PTM7_FN),
818 PINMUX_DATA(FMS0_MARK, PTM5_FN), 936 PINMUX_DATA(RD_MARK, PTM6_FN),
819 PINMUX_DATA(FMS1_MARK, PTM4_FN), 937 PINMUX_DATA(WE0_MARK, PTM7_FN),
938 PINMUX_DATA(CS0_MARK, PTM4_FN),
820 PINMUX_DATA(SDA6_MARK, PTM3_FN), 939 PINMUX_DATA(SDA6_MARK, PTM3_FN),
821 PINMUX_DATA(SCL6_MARK, PTM2_FN), 940 PINMUX_DATA(SCL6_MARK, PTM2_FN),
822 PINMUX_DATA(SDA7_MARK, PTM1_FN), 941 PINMUX_DATA(SDA7_MARK, PTM1_FN),
823 PINMUX_DATA(SCL7_MARK, PTM0_FN), 942 PINMUX_DATA(SCL7_MARK, PTM0_FN),
824 943
825 /* PTN FN */ 944 /* PTN FN */
826 PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN), 945 PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
827 PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN), 946 PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
828 PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN), 947 PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
829 PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN), 948 PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
830 PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN), 949 PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
831 PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN), 950 PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
832 PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN), 951 PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
833 PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN), 952 PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
834 PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN), 953 PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
835 PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN), 954 PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
836 PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN), 955 PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
837 PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN), 956 PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
838 PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
839 PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
840 PINMUX_DATA(EVENT0_MARK, PTN0_FN),
841 957
842 /* PTO FN */ 958 /* PTO FN */
843 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN), 959 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
844 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN), 960 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
845 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN), 961 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
846 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN), 962 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
847 PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN), 963 PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
848 PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN), 964 PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
849 PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN), 965 PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
850 PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN), 966 PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
967 PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
968 PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
969 PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
970 PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
851 971
852 /* PTP FN */ 972 /* PTP FN */
853 PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
854 PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
855 PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
856 PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
857 PINMUX_DATA(JMCRST_MARK, PTP2_FN),
858 PINMUX_DATA(SCK4_MARK, PTP1_FN),
859 PINMUX_DATA(SCK3_MARK, PTP0_FN),
860 973
861 /* PTQ FN */ 974 /* PTQ FN */
862 PINMUX_DATA(LAD3_MARK, PTQ6_FN), 975 PINMUX_DATA(LAD3_MARK, PTQ6_FN),
@@ -864,8 +977,8 @@ static pinmux_enum_t pinmux_data[] = {
864 PINMUX_DATA(LAD1_MARK, PTQ4_FN), 977 PINMUX_DATA(LAD1_MARK, PTQ4_FN),
865 PINMUX_DATA(LAD0_MARK, PTQ3_FN), 978 PINMUX_DATA(LAD0_MARK, PTQ3_FN),
866 PINMUX_DATA(LFRAME_MARK, PTQ2_FN), 979 PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
867 PINMUX_DATA(SCK4_MARK, PTQ1_FN), 980 PINMUX_DATA(LRESET_MARK, PTQ1_FN),
868 PINMUX_DATA(SCK3_MARK, PTQ0_FN), 981 PINMUX_DATA(LCLK_MARK, PTQ0_FN),
869 982
870 /* PTR FN */ 983 /* PTR FN */
871 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */ 984 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */
@@ -888,58 +1001,84 @@ static pinmux_enum_t pinmux_data[] = {
888 PINMUX_DATA(SCL3_MARK, PTS0_FN), 1001 PINMUX_DATA(SCL3_MARK, PTS0_FN),
889 1002
890 /* PTT FN */ 1003 /* PTT FN */
891 PINMUX_DATA(AUDSYNC_MARK, PTS5_FN), 1004 PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
892 PINMUX_DATA(AUDCK_MARK, PTS4_FN), 1005 PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
893 PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN), 1006 PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
894 PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN), 1007 PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
895 PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN), 1008 PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
896 PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN), 1009 PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
897 PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN), 1010 PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
898 PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN), 1011 PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
899 PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN), 1012 PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
900 PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN), 1013 PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
1014 PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
1015 PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
1016 PINMUX_DATA(PWMX1_MARK, PTT1_FN),
1017 PINMUX_DATA(PWMX0_MARK, PTT0_FN),
901 1018
902 /* PTU FN */ 1019 /* PTU FN */
903 PINMUX_DATA(CS6_MARK, PTU7_FN), 1020 PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
904 PINMUX_DATA(CS5_MARK, PTU6_FN), 1021 PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
905 PINMUX_DATA(CS4_MARK, PTU5_FN), 1022 PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
906 PINMUX_DATA(CS0_MARK, PTU4_FN), 1023 PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
907 PINMUX_DATA(RD_MARK, PTU3_FN), 1024 PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
908 PINMUX_DATA(WE0_MARK, PTU2_FN), 1025 PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
909 PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN), 1026 PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
910 PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN), 1027 PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
911 PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN), 1028 PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
912 PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN), 1029 PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
1030 PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
1031 PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
1032 PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
1033 PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
1034 PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
1035 PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
913 1036
914 /* PTV FN */ 1037 /* PTV FN */
915 PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN), 1038 PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
916 PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN), 1039 PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
917 PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN), 1040 PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
918 PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN), 1041 PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
919 PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN), 1042 PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
920 PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN), 1043 PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
921 PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN), 1044 PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
922 PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN), 1045 PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
923 PINMUX_DATA(A19_MARK, PTV3_FN), 1046 PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
924 PINMUX_DATA(A18_MARK, PTV2_FN), 1047 PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
925 PINMUX_DATA(A17_MARK, PTV1_FN), 1048 PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
926 PINMUX_DATA(A16_MARK, PTV0_FN), 1049 PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
1050 PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
1051 PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
1052 PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
1053 PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
927 1054
928 /* PTW FN */ 1055 /* PTW FN */
929 PINMUX_DATA(A15_MARK, PTW7_FN), 1056 PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
930 PINMUX_DATA(A14_MARK, PTW6_FN), 1057 PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
931 PINMUX_DATA(A13_MARK, PTW5_FN), 1058 PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
932 PINMUX_DATA(A12_MARK, PTW4_FN), 1059 PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
933 PINMUX_DATA(A11_MARK, PTW3_FN), 1060 PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
934 PINMUX_DATA(A10_MARK, PTW2_FN), 1061 PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
935 PINMUX_DATA(A9_MARK, PTW1_FN), 1062 PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
936 PINMUX_DATA(A8_MARK, PTW0_FN), 1063 PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
1064 PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
1065 PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
1066 PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
1067 PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
1068 PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
1069 PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
1070 PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
1071 PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
937 1072
938 /* PTX FN */ 1073 /* PTX FN */
939 PINMUX_DATA(A7_MARK, PTX7_FN), 1074 PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
940 PINMUX_DATA(A6_MARK, PTX6_FN), 1075 PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
941 PINMUX_DATA(A5_MARK, PTX5_FN), 1076 PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
942 PINMUX_DATA(A4_MARK, PTX4_FN), 1077 PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
1078 PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
1079 PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
1080 PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
1081 PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
943 PINMUX_DATA(A3_MARK, PTX3_FN), 1082 PINMUX_DATA(A3_MARK, PTX3_FN),
944 PINMUX_DATA(A2_MARK, PTX2_FN), 1083 PINMUX_DATA(A2_MARK, PTX2_FN),
945 PINMUX_DATA(A1_MARK, PTX1_FN), 1084 PINMUX_DATA(A1_MARK, PTX1_FN),
@@ -954,6 +1093,24 @@ static pinmux_enum_t pinmux_data[] = {
954 PINMUX_DATA(D2_MARK, PTY2_FN), 1093 PINMUX_DATA(D2_MARK, PTY2_FN),
955 PINMUX_DATA(D1_MARK, PTY1_FN), 1094 PINMUX_DATA(D1_MARK, PTY1_FN),
956 PINMUX_DATA(D0_MARK, PTY0_FN), 1095 PINMUX_DATA(D0_MARK, PTY0_FN),
1096
1097 /* PTZ FN */
1098 PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
1099 PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
1100 PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
1101 PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
1102 PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
1103 PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
1104 PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
1105 PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
1106 PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
1107 PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
1108 PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
1109 PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
1110 PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
1111 PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
1112 PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
1113 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
957}; 1114};
958 1115
959static struct pinmux_gpio pinmux_gpios[] = { 1116static struct pinmux_gpio pinmux_gpios[] = {
@@ -1048,7 +1205,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1048 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), 1205 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
1049 1206
1050 /* PTJ */ 1207 /* PTJ */
1051 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1052 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), 1208 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1053 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), 1209 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1054 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), 1210 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
@@ -1068,7 +1224,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1068 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), 1224 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1069 1225
1070 /* PTL */ 1226 /* PTL */
1071 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1072 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), 1227 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1073 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), 1228 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1074 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), 1229 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
@@ -1078,6 +1233,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1078 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), 1233 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1079 1234
1080 /* PTM */ 1235 /* PTM */
1236 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1081 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), 1237 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1082 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), 1238 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1083 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), 1239 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
@@ -1087,7 +1243,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1087 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), 1243 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1088 1244
1089 /* PTN */ 1245 /* PTN */
1090 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1091 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), 1246 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1092 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), 1247 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1093 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), 1248 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
@@ -1107,6 +1262,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1107 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), 1262 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
1108 1263
1109 /* PTP */ 1264 /* PTP */
1265 PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
1110 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), 1266 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
1111 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), 1267 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
1112 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), 1268 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
@@ -1145,6 +1301,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
1145 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), 1301 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1146 1302
1147 /* PTT */ 1303 /* PTT */
1304 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1305 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1148 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), 1306 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1149 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), 1307 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1150 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), 1308 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
@@ -1212,54 +1370,35 @@ static struct pinmux_gpio pinmux_gpios[] = {
1212 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1370 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1213 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1371 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1214 1372
1215 /* PTA (mobule: LBSC, CPG, LPC) */ 1373 /* PTA (mobule: LBSC, RGMII) */
1216 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1374 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1217 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1375 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1218 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), 1376 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
1219 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), 1377 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
1220 PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
1221 PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
1222 PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
1223 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1224 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1225 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1226 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1227 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1228 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1229 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1230 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1231
1232 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
1233 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1234 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1235 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1236 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1237 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1238 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1239 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1240 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1241 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), 1378 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
1242 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), 1379 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK),
1243 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), 1380 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
1244 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), 1381 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK),
1245 PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
1246 PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
1247 PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
1248 PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
1249 PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
1250 PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
1251
1252 /* PTC (mobule: SD) */
1253 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1254 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1255 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1256 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1257 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1258 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1259 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1260 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1261 1382
1262 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ 1383 /* PTB (mobule: INTC, ONFI, TMU) */
1384 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
1385 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
1386 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
1387 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
1388 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
1389 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
1390 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
1391 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
1392 PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
1393 PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
1394 PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
1395 PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
1396 PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
1397 PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
1398 PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
1399 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1400
1401 /* PTC (mobule: IRQ, PWMU) */
1263 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1402 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1264 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1403 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1265 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1404 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
@@ -1268,80 +1407,102 @@ static struct pinmux_gpio pinmux_gpios[] = {
1268 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1407 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1269 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1408 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1270 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1409 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1271 PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK), 1410 PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
1272 PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK), 1411 PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
1273 PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK), 1412 PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
1274 PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK), 1413 PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
1275 PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK), 1414 PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
1276 PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK), 1415 PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
1277 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), 1416
1278 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), 1417 /* PTD (mobule: SPI0, DMAC) */
1418 PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
1419 PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
1420 PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
1421 PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
1422 PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
1423 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
1424 PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
1425 PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
1426 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1427 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1428 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1279 1429
1280 /* PTE (mobule: EtherC) */ 1430 /* PTE (mobule: RMII) */
1281 PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK), 1431 PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
1282 PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK), 1432 PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
1283 PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK), 1433 PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
1284 PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK), 1434 PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
1285 PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK), 1435 PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
1286 PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK), 1436 PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
1287 PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK), 1437 PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
1288 PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK), 1438 PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
1289 1439
1290 /* PTF (mobule: EtherC) */ 1440 /* PTF (mobule: RMII, SerMux) */
1291 PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK), 1441 PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
1292 PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK), 1442 PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
1293 PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK), 1443 PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
1294 PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK), 1444 PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
1295 PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK), 1445 PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
1296 PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK), 1446 PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
1297 PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK), 1447 PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
1298 PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK), 1448 PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
1299 1449 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
1300 /* PTG (mobule: SYSTEM, PWMX, LPC) */ 1450
1301 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1451 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1302 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 1452 PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
1303 PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK), 1453 PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
1304 PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK), 1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1305 PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK), 1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1306 PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
1307 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), 1456 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
1308 PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK), 1457 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1309 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), 1458 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
1310 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), 1459 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
1460 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
1461 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
1311 1462
1312 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ 1463 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1313 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1314 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1315 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1316 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), 1464 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
1317 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), 1465 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
1318 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), 1466 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
1319 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), 1467 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
1320 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), 1468 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
1321 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), 1469 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
1322 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), 1470 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1471 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1472 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1473 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1474 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1475 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
1476 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
1323 1477
1324 /* PTI (mobule: INTC) */ 1478 /* PTI (mobule: LBSC, SDHI) */
1325 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), 1479 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1326 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), 1480 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1327 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), 1481 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1328 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), 1482 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1329 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), 1483 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1330 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), 1484 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1331 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), 1485 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1332 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), 1486 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1487 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1488 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1489 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1490 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1491 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1492 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1493 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1494 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1333 1495
1334 /* PTJ (mobule: SCIF234, SERMUX) */ 1496 /* PTJ (mobule: SCIF234, SERMUX) */
1335 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1497 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1498 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1336 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1499 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1337 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1500 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1338 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1501 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
1339 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), 1502 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1340 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), 1503 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1341 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1342 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1343 1504
1344 /* PTK (mobule: SERMUX) */ 1505 /* PTK (mobule: SERMUX, LBSC, SCIF) */
1345 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), 1506 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
1346 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), 1507 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
1347 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), 1508 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
@@ -1349,62 +1510,65 @@ static struct pinmux_gpio pinmux_gpios[] = {
1349 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), 1510 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
1350 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), 1511 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
1351 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), 1512 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
1352 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), 1513 PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
1514 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1515 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1516 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1353 1517
1354 /* PTL (mobule: SERMUX) */ 1518 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
1355 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1356 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), 1519 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
1357 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), 1520 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
1358 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), 1521 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
1359 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), 1522 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
1360 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), 1523 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
1361 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), 1524 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
1362 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), 1525 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1526 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1527 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1528 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1529 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1530 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1531 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1363 1532
1364 /* PTM (mobule: IIC, LPC) */ 1533 /* PTM (mobule: LBSC, IIC) */
1534 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1535 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1536 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1537 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1365 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), 1538 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
1366 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), 1539 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
1367 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), 1540 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
1368 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), 1541 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
1369 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1370 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1371 PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
1372 1542
1373 /* PTN (mobule: SCIF234, EVC) */ 1543 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
1374 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1544 PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
1375 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), 1545 PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1546 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1377 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), 1547 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1378 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), 1548 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1379 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1549 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1380 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), 1550 PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
1381 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), 1551 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
1382 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), 1552 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
1383 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), 1553 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
1384 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), 1554 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
1385 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), 1555 PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
1386 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1387 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1388 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1389 1556
1390 /* PTO (mobule: SGPIO) */ 1557 /* PTO (mobule: SGPIO, SerMux) */
1391 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), 1558 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
1392 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), 1559 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
1393 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), 1560 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
1394 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), 1561 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
1395 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), 1562 PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
1396 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), 1563 PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
1397 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), 1564 PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
1398 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), 1565 PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
1566 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
1568 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1569 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1399 1570
1400 /* PTP (mobule: JMC, SCIF234) */ 1571 /* PTP (mobule: EVC, ADC) */
1401 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1402 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1403 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1404 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1405 PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
1406 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1407 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1408 1572
1409 /* PTQ (mobule: LPC) */ 1573 /* PTQ (mobule: LPC) */
1410 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), 1574 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
@@ -1439,31 +1603,41 @@ static struct pinmux_gpio pinmux_gpios[] = {
1439 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 1603 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
1440 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 1604 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
1441 1605
1442 /* PTT (mobule: SYSTEM, PWMX) */ 1606 /* PTT (mobule: PWMX, AUD) */
1443 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1607 PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
1444 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1608 PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
1609 PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
1610 PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
1611 PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
1612 PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
1613 PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
1614 PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
1445 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1615 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1446 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1616 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1447 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1617 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1448 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1618 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1449 PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK), 1619 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
1450 PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK), 1620 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1451 PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
1452 PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
1453
1454 /* PTU (mobule: LBSC, DMAC) */
1455 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1456 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1457 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1459 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1460 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1461 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1462 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1463 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1464 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1465 1621
1466 /* PTV (mobule: LBSC, DMAC) */ 1622 /* PTU (mobule: LPC, APM) */
1623 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1624 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1625 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1626 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1627 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1628 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1629 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1630 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1631 PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
1632 PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
1633 PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
1634 PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
1635 PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
1636 PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
1637 PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
1638 PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
1639
1640 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
1467 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1641 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1468 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1642 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1469 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1643 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
@@ -1472,12 +1646,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
1472 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1646 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1473 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1647 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1474 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1648 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1475 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1649 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
1476 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1650 PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
1477 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1651 PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
1478 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1652 PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
1653 PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
1654 PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
1655 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
1656 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
1657 PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
1658 PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
1659 PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
1660 PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
1479 1661
1480 /* PTW (mobule: LBSC) */ 1662 /* PTW (mobule: LBSC, EVC, SCIF) */
1481 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1663 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1482 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1664 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1483 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1665 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
@@ -1487,6 +1669,14 @@ static struct pinmux_gpio pinmux_gpios[] = {
1487 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1669 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1488 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1670 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1489 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1671 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1672 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
1673 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
1674 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
1675 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1676 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1677 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1678 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
1679 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
1490 1680
1491 /* PTX (mobule: LBSC) */ 1681 /* PTX (mobule: LBSC) */
1492 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1682 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
@@ -1497,6 +1687,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
1497 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1687 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1498 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1688 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1499 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1689 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1690 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
1691 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
1692 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
1693 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
1500 1694
1501 /* PTY (mobule: LBSC) */ 1695 /* PTY (mobule: LBSC) */
1502 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1696 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
@@ -1507,18 +1701,36 @@ static struct pinmux_gpio pinmux_gpios[] = {
1507 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1701 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1508 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1702 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1509 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1703 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1704
1705 /* PTZ (mobule: eMMC, ONFI) */
1706 PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
1707 PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
1708 PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
1709 PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
1710 PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
1711 PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
1712 PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
1713 PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
1714 PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
1715 PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
1716 PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
1717 PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
1718 PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
1719 PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
1720 PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
1721 PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
1510 }; 1722 };
1511 1723
1512static struct pinmux_cfg_reg pinmux_config_regs[] = { 1724static struct pinmux_cfg_reg pinmux_config_regs[] = {
1513 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { 1725 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1514 PTA7_FN, PTA7_OUT, PTA7_IN, 0, 1726 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
1515 PTA6_FN, PTA6_OUT, PTA6_IN, 0, 1727 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
1516 PTA5_FN, PTA5_OUT, PTA5_IN, 0, 1728 PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
1517 PTA4_FN, PTA4_OUT, PTA4_IN, 0, 1729 PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
1518 PTA3_FN, PTA3_OUT, PTA3_IN, 0, 1730 PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
1519 PTA2_FN, PTA2_OUT, PTA2_IN, 0, 1731 PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
1520 PTA1_FN, PTA1_OUT, PTA1_IN, 0, 1732 PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
1521 PTA0_FN, PTA0_OUT, PTA0_IN, 0 } 1733 PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
1522 }, 1734 },
1523 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { 1735 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1524 PTB7_FN, PTB7_OUT, PTB7_IN, 0, 1736 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
@@ -1541,125 +1753,126 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1541 PTC0_FN, PTC0_OUT, PTC0_IN, 0 } 1753 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
1542 }, 1754 },
1543 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { 1755 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1544 PTD7_FN, PTD7_OUT, PTD7_IN, 0, 1756 PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
1545 PTD6_FN, PTD6_OUT, PTD6_IN, 0, 1757 PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
1546 PTD5_FN, PTD5_OUT, PTD5_IN, 0, 1758 PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
1547 PTD4_FN, PTD4_OUT, PTD4_IN, 0, 1759 PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
1548 PTD3_FN, PTD3_OUT, PTD3_IN, 0, 1760 PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
1549 PTD2_FN, PTD2_OUT, PTD2_IN, 0, 1761 PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
1550 PTD1_FN, PTD1_OUT, PTD1_IN, 0, 1762 PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
1551 PTD0_FN, PTD0_OUT, PTD0_IN, 0 } 1763 PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
1552 }, 1764 },
1553 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { 1765 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1554 PTE7_FN, PTE7_OUT, PTE7_IN, 0, 1766 PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
1555 PTE6_FN, PTE6_OUT, PTE6_IN, 0, 1767 PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
1556 PTE5_FN, PTE5_OUT, PTE5_IN, 0, 1768 PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
1557 PTE4_FN, PTE4_OUT, PTE4_IN, 0, 1769 PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
1558 PTE3_FN, PTE3_OUT, PTE3_IN, 0, 1770 PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
1559 PTE2_FN, PTE2_OUT, PTE2_IN, 0, 1771 PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
1560 PTE1_FN, PTE1_OUT, PTE1_IN, 0, 1772 PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
1561 PTE0_FN, PTE0_OUT, PTE0_IN, 0 } 1773 PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
1562 }, 1774 },
1563 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { 1775 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1564 PTF7_FN, PTF7_OUT, PTF7_IN, 0, 1776 PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
1565 PTF6_FN, PTF6_OUT, PTF6_IN, 0, 1777 PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
1566 PTF5_FN, PTF5_OUT, PTF5_IN, 0, 1778 PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
1567 PTF4_FN, PTF4_OUT, PTF4_IN, 0, 1779 PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
1568 PTF3_FN, PTF3_OUT, PTF3_IN, 0, 1780 PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
1569 PTF2_FN, PTF2_OUT, PTF2_IN, 0, 1781 PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
1570 PTF1_FN, PTF1_OUT, PTF1_IN, 0, 1782 PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
1571 PTF0_FN, PTF0_OUT, PTF0_IN, 0 } 1783 PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
1572 }, 1784 },
1573 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { 1785 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1574 PTG7_FN, PTG7_OUT, PTG7_IN, 0, 1786 PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
1575 PTG6_FN, PTG6_OUT, PTG6_IN, 0, 1787 PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
1576 PTG5_FN, PTG5_OUT, PTG5_IN, 0, 1788 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
1577 PTG4_FN, PTG4_OUT, PTG4_IN, 0, 1789 PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
1578 PTG3_FN, PTG3_OUT, PTG3_IN, 0, 1790 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1579 PTG2_FN, PTG2_OUT, PTG2_IN, 0, 1791 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1580 PTG1_FN, PTG1_OUT, PTG1_IN, 0, 1792 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1581 PTG0_FN, PTG0_OUT, PTG0_IN, 0 } 1793 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
1582 }, 1794 },
1583 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { 1795 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1584 PTH7_FN, PTH7_OUT, PTH7_IN, 0, 1796 PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
1585 PTH6_FN, PTH6_OUT, PTH6_IN, 0, 1797 PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
1586 PTH5_FN, PTH5_OUT, PTH5_IN, 0, 1798 PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
1587 PTH4_FN, PTH4_OUT, PTH4_IN, 0, 1799 PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
1588 PTH3_FN, PTH3_OUT, PTH3_IN, 0, 1800 PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
1589 PTH2_FN, PTH2_OUT, PTH2_IN, 0, 1801 PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
1590 PTH1_FN, PTH1_OUT, PTH1_IN, 0, 1802 PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
1591 PTH0_FN, PTH0_OUT, PTH0_IN, 0 } 1803 PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
1592 }, 1804 },
1593 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { 1805 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1594 PTI7_FN, PTI7_OUT, PTI7_IN, 0, 1806 PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
1595 PTI6_FN, PTI6_OUT, PTI6_IN, 0, 1807 PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
1596 PTI5_FN, PTI5_OUT, PTI5_IN, 0, 1808 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
1597 PTI4_FN, PTI4_OUT, PTI4_IN, 0, 1809 PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
1598 PTI3_FN, PTI3_OUT, PTI3_IN, 0, 1810 PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
1599 PTI2_FN, PTI2_OUT, PTI2_IN, 0, 1811 PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
1600 PTI1_FN, PTI1_OUT, PTI1_IN, 0, 1812 PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
1601 PTI0_FN, PTI0_OUT, PTI0_IN, 0 } 1813 PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
1602 }, 1814 },
1603 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { 1815 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
1604 PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0, 1816 0, 0, 0, 0, /* reserved: always set 1 */
1605 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, 1817 PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
1606 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, 1818 PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
1607 PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, 1819 PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
1608 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, 1820 PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
1609 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, 1821 PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
1610 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, 1822 PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
1611 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } 1823 PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
1612 }, 1824 },
1613 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { 1825 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
1614 PTK7_FN, PTK7_OUT, PTK7_IN, 0, 1826 PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
1615 PTK6_FN, PTK6_OUT, PTK6_IN, 0, 1827 PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
1616 PTK5_FN, PTK5_OUT, PTK5_IN, 0, 1828 PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
1617 PTK4_FN, PTK4_OUT, PTK4_IN, 0, 1829 PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
1618 PTK3_FN, PTK3_OUT, PTK3_IN, 0, 1830 PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
1619 PTK2_FN, PTK2_OUT, PTK2_IN, 0, 1831 PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
1620 PTK1_FN, PTK1_OUT, PTK1_IN, 0, 1832 PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
1621 PTK0_FN, PTK0_OUT, PTK0_IN, 0 } 1833 PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
1622 }, 1834 },
1623 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { 1835 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
1624 PTL7_FN, PTL7_OUT, PTL7_IN, 0, 1836 0, 0, 0, 0, /* reserved: always set 1 */
1625 PTL6_FN, PTL6_OUT, PTL6_IN, 0, 1837 PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
1626 PTL5_FN, PTL5_OUT, PTL5_IN, 0, 1838 PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
1627 PTL4_FN, PTL4_OUT, PTL4_IN, 0, 1839 PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
1628 PTL3_FN, PTL3_OUT, PTL3_IN, 0, 1840 PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
1629 PTL2_FN, PTL2_OUT, PTL2_IN, 0, 1841 PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
1630 PTL1_FN, PTL1_OUT, PTL1_IN, 0, 1842 PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
1631 PTL0_FN, PTL0_OUT, PTL0_IN, 0 } 1843 PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
1632 }, 1844 },
1633 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { 1845 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
1634 0, 0, 0, 0, /* reserved: always set 1 */ 1846 PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
1635 PTM6_FN, PTM6_OUT, PTM6_IN, 0, 1847 PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
1636 PTM5_FN, PTM5_OUT, PTM5_IN, 0, 1848 PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
1637 PTM4_FN, PTM4_OUT, PTM4_IN, 0, 1849 PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
1638 PTM3_FN, PTM3_OUT, PTM3_IN, 0, 1850 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1639 PTM2_FN, PTM2_OUT, PTM2_IN, 0, 1851 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1640 PTM1_FN, PTM1_OUT, PTM1_IN, 0, 1852 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1641 PTM0_FN, PTM0_OUT, PTM0_IN, 0 } 1853 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
1642 }, 1854 },
1643 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { 1855 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
1644 PTN7_FN, PTN7_OUT, PTN7_IN, 0, 1856 0, 0, 0, 0, /* reserved: always set 1 */
1645 PTN6_FN, PTN6_OUT, PTN6_IN, 0, 1857 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1646 PTN5_FN, PTN5_OUT, PTN5_IN, 0, 1858 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
1647 PTN4_FN, PTN4_OUT, PTN4_IN, 0, 1859 PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
1648 PTN3_FN, PTN3_OUT, PTN3_IN, 0, 1860 PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
1649 PTN2_FN, PTN2_OUT, PTN2_IN, 0, 1861 PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
1650 PTN1_FN, PTN1_OUT, PTN1_IN, 0, 1862 PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
1651 PTN0_FN, PTN0_OUT, PTN0_IN, 0 } 1863 PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
1652 }, 1864 },
1653 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { 1865 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
1654 PTO7_FN, PTO7_OUT, PTO7_IN, 0, 1866 PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
1655 PTO6_FN, PTO6_OUT, PTO6_IN, 0, 1867 PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
1656 PTO5_FN, PTO5_OUT, PTO5_IN, 0, 1868 PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
1657 PTO4_FN, PTO4_OUT, PTO4_IN, 0, 1869 PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
1658 PTO3_FN, PTO3_OUT, PTO3_IN, 0, 1870 PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
1659 PTO2_FN, PTO2_OUT, PTO2_IN, 0, 1871 PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
1660 PTO1_FN, PTO1_OUT, PTO1_IN, 0, 1872 PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
1661 PTO0_FN, PTO0_OUT, PTO0_IN, 0 } 1873 PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
1662 }, 1874 },
1875#if 0 /* FIXME: Remove it? */
1663 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { 1876 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
1664 0, 0, 0, 0, /* reserved: always set 1 */ 1877 0, 0, 0, 0, /* reserved: always set 1 */
1665 PTP6_FN, PTP6_OUT, PTP6_IN, 0, 1878 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
@@ -1670,6 +1883,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1670 PTP1_FN, PTP1_OUT, PTP1_IN, 0, 1883 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1671 PTP0_FN, PTP0_OUT, PTP0_IN, 0 } 1884 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
1672 }, 1885 },
1886#endif
1673 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { 1887 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
1674 0, 0, 0, 0, /* reserved: always set 1 */ 1888 0, 0, 0, 0, /* reserved: always set 1 */
1675 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, 1889 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
@@ -1701,14 +1915,14 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1701 PTS0_FN, PTS0_OUT, PTS0_IN, 0 } 1915 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
1702 }, 1916 },
1703 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { 1917 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
1704 0, 0, 0, 0, /* reserved: always set 1 */ 1918 PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
1705 0, 0, 0, 0, /* reserved: always set 1 */ 1919 PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
1706 PTT5_FN, PTT5_OUT, PTT5_IN, 0, 1920 PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
1707 PTT4_FN, PTT4_OUT, PTT4_IN, 0, 1921 PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
1708 PTT3_FN, PTT3_OUT, PTT3_IN, 0, 1922 PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
1709 PTT2_FN, PTT2_OUT, PTT2_IN, 0, 1923 PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
1710 PTT1_FN, PTT1_OUT, PTT1_IN, 0, 1924 PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
1711 PTT0_FN, PTT0_OUT, PTT0_IN, 0 } 1925 PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
1712 }, 1926 },
1713 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { 1927 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
1714 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, 1928 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
@@ -1727,16 +1941,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, 1941 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
1728 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, 1942 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
1729 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, 1943 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
1730 PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU, 1944 PTV1_FN, PTV1_OUT, PTV1_IN, 0,
1731 PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU } 1945 PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
1732 }, 1946 },
1733 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { 1947 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
1734 PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU, 1948 PTW7_FN, PTW7_OUT, PTW7_IN, 0,
1735 PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU, 1949 PTW6_FN, PTW6_OUT, PTW6_IN, 0,
1736 PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU, 1950 PTW5_FN, PTW5_OUT, PTW5_IN, 0,
1737 PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU, 1951 PTW4_FN, PTW4_OUT, PTW4_IN, 0,
1738 PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU, 1952 PTW3_FN, PTW3_OUT, PTW3_IN, 0,
1739 PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU, 1953 PTW2_FN, PTW2_OUT, PTW2_IN, 0,
1740 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, 1954 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
1741 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } 1955 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
1742 }, 1956 },
@@ -1761,32 +1975,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1761 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } 1975 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
1762 }, 1976 },
1763 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { 1977 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
1764 0, PTZ7_OUT, PTZ7_IN, 0, 1978 PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
1765 0, PTZ6_OUT, PTZ6_IN, 0, 1979 PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
1766 0, PTZ5_OUT, PTZ5_IN, 0, 1980 PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
1767 0, PTZ4_OUT, PTZ4_IN, 0, 1981 PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
1768 0, PTZ3_OUT, PTZ3_IN, 0, 1982 PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
1769 0, PTZ2_OUT, PTZ2_IN, 0, 1983 PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
1770 0, PTZ1_OUT, PTZ1_IN, 0, 1984 PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
1771 0, PTZ0_OUT, PTZ0_IN, 0 } 1985 PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
1772 }, 1986 },
1773 1987
1774 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { 1988 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
1775 PS0_15_FN3, PS0_15_FN1, 1989 PS0_15_FN1, PS0_15_FN2,
1776 PS0_14_FN3, PS0_14_FN1, 1990 PS0_14_FN1, PS0_14_FN2,
1777 PS0_13_FN3, PS0_13_FN1, 1991 PS0_13_FN1, PS0_13_FN2,
1778 PS0_12_FN3, PS0_12_FN1, 1992 PS0_12_FN1, PS0_12_FN2,
1779 0, 0, 1993 PS0_11_FN1, PS0_11_FN2,
1780 0, 0, 1994 PS0_10_FN1, PS0_10_FN2,
1995 PS0_9_FN1, PS0_9_FN2,
1996 PS0_8_FN1, PS0_8_FN2,
1997 PS0_7_FN1, PS0_7_FN2,
1998 PS0_6_FN1, PS0_6_FN2,
1999 PS0_5_FN1, PS0_5_FN2,
2000 PS0_4_FN1, PS0_4_FN2,
2001 PS0_3_FN1, PS0_3_FN2,
2002 PS0_2_FN1, PS0_2_FN2,
1781 0, 0, 2003 0, 0,
1782 0, 0,
1783 PS0_7_FN2, PS0_7_FN1,
1784 PS0_6_FN2, PS0_6_FN1,
1785 PS0_5_FN2, PS0_5_FN1,
1786 PS0_4_FN2, PS0_4_FN1,
1787 PS0_3_FN2, PS0_3_FN1,
1788 PS0_2_FN2, PS0_2_FN1,
1789 PS0_1_FN2, PS0_1_FN1,
1790 0, 0, } 2004 0, 0, }
1791 }, 2005 },
1792 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { 2006 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
@@ -1795,73 +2009,136 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1795 0, 0, 2009 0, 0,
1796 0, 0, 2010 0, 0,
1797 0, 0, 2011 0, 0,
2012 PS1_10_FN1, PS1_10_FN2,
2013 PS1_9_FN1, PS1_9_FN2,
2014 PS1_8_FN1, PS1_8_FN2,
1798 0, 0, 2015 0, 0,
1799 0, 0, 2016 0, 0,
1800 0, 0, 2017 0, 0,
1801 PS1_7_FN1, PS1_7_FN3,
1802 PS1_6_FN1, PS1_6_FN3,
1803 0, 0,
1804 0, 0,
1805 0, 0, 2018 0, 0,
1806 0, 0, 2019 0, 0,
2020 PS1_2_FN1, PS1_2_FN2,
1807 0, 0, 2021 0, 0,
1808 0, 0, } 2022 0, 0, }
1809 }, 2023 },
1810 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { 2024 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
1811 0, 0, 2025 0, 0,
1812 0, 0, 2026 0, 0,
1813 PS2_13_FN3, PS2_13_FN1, 2027 PS2_13_FN1, PS2_13_FN2,
1814 PS2_12_FN3, PS2_12_FN1, 2028 PS2_12_FN1, PS2_12_FN2,
1815 0, 0, 2029 0, 0,
1816 0, 0, 2030 0, 0,
1817 0, 0, 2031 0, 0,
1818 0, 0, 2032 0, 0,
2033 PS2_7_FN1, PS2_7_FN2,
2034 PS2_6_FN1, PS2_6_FN2,
2035 PS2_5_FN1, PS2_5_FN2,
2036 PS2_4_FN1, PS2_4_FN2,
1819 0, 0, 2037 0, 0,
2038 PS2_2_FN1, PS2_2_FN2,
1820 0, 0, 2039 0, 0,
2040 0, 0, }
2041 },
2042 { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
2043 PS3_15_FN1, PS3_15_FN2,
2044 PS3_14_FN1, PS3_14_FN2,
2045 PS3_13_FN1, PS3_13_FN2,
2046 PS3_12_FN1, PS3_12_FN2,
2047 PS3_11_FN1, PS3_11_FN2,
2048 PS3_10_FN1, PS3_10_FN2,
2049 PS3_9_FN1, PS3_9_FN2,
2050 PS3_8_FN1, PS3_8_FN2,
2051 PS3_7_FN1, PS3_7_FN2,
1821 0, 0, 2052 0, 0,
1822 0, 0, 2053 0, 0,
1823 0, 0, 2054 0, 0,
1824 0, 0, 2055 0, 0,
1825 PS2_1_FN1, PS2_1_FN2, 2056 PS3_2_FN1, PS3_2_FN2,
1826 PS2_0_FN1, PS2_0_FN2, } 2057 PS3_1_FN1, PS3_1_FN2,
2058 0, 0, }
1827 }, 2059 },
2060
1828 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { 2061 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
1829 PS4_15_FN2, PS4_15_FN1,
1830 PS4_14_FN2, PS4_14_FN1,
1831 PS4_13_FN2, PS4_13_FN1,
1832 PS4_12_FN2, PS4_12_FN1,
1833 PS4_11_FN2, PS4_11_FN1,
1834 PS4_10_FN2, PS4_10_FN1,
1835 PS4_9_FN2, PS4_9_FN1,
1836 0, 0, 2062 0, 0,
2063 PS4_14_FN1, PS4_14_FN2,
2064 PS4_13_FN1, PS4_13_FN2,
2065 PS4_12_FN1, PS4_12_FN2,
1837 0, 0, 2066 0, 0,
2067 PS4_10_FN1, PS4_10_FN2,
2068 PS4_9_FN1, PS4_9_FN2,
2069 PS4_8_FN1, PS4_8_FN2,
1838 0, 0, 2070 0, 0,
1839 0, 0, 2071 0, 0,
1840 0, 0, 2072 0, 0,
1841 PS4_3_FN2, PS4_3_FN1, 2073 PS4_4_FN1, PS4_4_FN2,
1842 PS4_2_FN2, PS4_2_FN1, 2074 PS4_3_FN1, PS4_3_FN2,
1843 PS4_1_FN2, PS4_1_FN1, 2075 PS4_2_FN1, PS4_2_FN2,
1844 PS4_0_FN2, PS4_0_FN1, } 2076 PS4_1_FN1, PS4_1_FN2,
2077 PS4_0_FN1, PS4_0_FN2, }
1845 }, 2078 },
1846 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { 2079 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
1847 0, 0, 2080 0, 0,
1848 0, 0, 2081 0, 0,
1849 0, 0, 2082 0, 0,
1850 0, 0, 2083 0, 0,
1851 0, 0, 2084 PS5_11_FN1, PS5_11_FN2,
1852 0, 0, 2085 PS5_10_FN1, PS5_10_FN2,
1853 PS5_9_FN1, PS5_9_FN2, 2086 PS5_9_FN1, PS5_9_FN2,
1854 PS5_8_FN1, PS5_8_FN2, 2087 PS5_8_FN1, PS5_8_FN2,
1855 PS5_7_FN1, PS5_7_FN2, 2088 PS5_7_FN1, PS5_7_FN2,
1856 PS5_6_FN1, PS5_6_FN2, 2089 PS5_6_FN1, PS5_6_FN2,
1857 PS5_5_FN1, PS5_5_FN2, 2090 PS5_5_FN1, PS5_5_FN2,
2091 PS5_4_FN1, PS5_4_FN2,
2092 PS5_3_FN1, PS5_3_FN2,
2093 PS5_2_FN1, PS5_2_FN2,
2094 0, 0,
2095 0, 0, }
2096 },
2097 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
2098 PS6_15_FN1, PS6_15_FN2,
2099 PS6_14_FN1, PS6_14_FN2,
2100 PS6_13_FN1, PS6_13_FN2,
2101 PS6_12_FN1, PS6_12_FN2,
2102 PS6_11_FN1, PS6_11_FN2,
2103 PS6_10_FN1, PS6_10_FN2,
2104 PS6_9_FN1, PS6_9_FN2,
2105 PS6_8_FN1, PS6_8_FN2,
2106 PS6_7_FN1, PS6_7_FN2,
2107 PS6_6_FN1, PS6_6_FN2,
2108 PS6_5_FN1, PS6_5_FN2,
2109 PS6_4_FN1, PS6_4_FN2,
2110 PS6_3_FN1, PS6_3_FN2,
2111 PS6_2_FN1, PS6_2_FN2,
2112 PS6_1_FN1, PS6_1_FN2,
2113 PS6_0_FN1, PS6_0_FN2, }
2114 },
2115 { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
2116 PS7_15_FN1, PS7_15_FN2,
2117 PS7_14_FN1, PS7_14_FN2,
2118 PS7_13_FN1, PS7_13_FN2,
2119 PS7_12_FN1, PS7_12_FN2,
2120 PS7_11_FN1, PS7_11_FN2,
2121 PS7_10_FN1, PS7_10_FN2,
2122 PS7_9_FN1, PS7_9_FN2,
2123 PS7_8_FN1, PS7_8_FN2,
2124 PS7_7_FN1, PS7_7_FN2,
2125 PS7_6_FN1, PS7_6_FN2,
2126 PS7_5_FN1, PS7_5_FN2,
1858 0, 0, 2127 0, 0,
1859 0, 0, 2128 0, 0,
1860 0, 0, 2129 0, 0,
1861 0, 0, 2130 0, 0,
1862 0, 0, } 2131 0, 0, }
1863 }, 2132 },
1864 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { 2133 { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
2134 PS8_15_FN1, PS8_15_FN2,
2135 PS8_14_FN1, PS8_14_FN2,
2136 PS8_13_FN1, PS8_13_FN2,
2137 PS8_12_FN1, PS8_12_FN2,
2138 PS8_11_FN1, PS8_11_FN2,
2139 PS8_10_FN1, PS8_10_FN2,
2140 PS8_9_FN1, PS8_9_FN2,
2141 PS8_8_FN1, PS8_8_FN2,
1865 0, 0, 2142 0, 0,
1866 0, 0, 2143 0, 0,
1867 0, 0, 2144 0, 0,
@@ -1869,15 +2146,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1869 0, 0, 2146 0, 0,
1870 0, 0, 2147 0, 0,
1871 0, 0, 2148 0, 0,
1872 0, 0, 2149 0, 0, }
1873 PS6_7_FN_AN, PS6_7_FN_EV,
1874 PS6_6_FN_AN, PS6_6_FN_EV,
1875 PS6_5_FN_AN, PS6_5_FN_EV,
1876 PS6_4_FN_AN, PS6_4_FN_EV,
1877 PS6_3_FN_AN, PS6_3_FN_EV,
1878 PS6_2_FN_AN, PS6_2_FN_EV,
1879 PS6_1_FN_AN, PS6_1_FN_EV,
1880 PS6_0_FN_AN, PS6_0_FN_EV, }
1881 }, 2150 },
1882 {} 2151 {}
1883}; 2152};
@@ -1920,7 +2189,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1920 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } 2189 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
1921 }, 2190 },
1922 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { 2191 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
1923 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 2192 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1924 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 2193 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1925 }, 2194 },
1926 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { 2195 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
@@ -1928,15 +2197,15 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1928 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 2197 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1929 }, 2198 },
1930 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { 2199 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
1931 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 2200 0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1932 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 2201 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1933 }, 2202 },
1934 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { 2203 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
1935 0, PTM6_DATA, PTM5_DATA, PTM4_DATA, 2204 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1936 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 2205 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1937 }, 2206 },
1938 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { 2207 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
1939 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 2208 0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1940 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 2209 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1941 }, 2210 },
1942 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { 2211 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
@@ -1944,7 +2213,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1944 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } 2213 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
1945 }, 2214 },
1946 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { 2215 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
1947 0, PTP6_DATA, PTP5_DATA, PTP4_DATA, 2216 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
1948 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } 2217 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
1949 }, 2218 },
1950 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { 2219 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
@@ -1960,7 +2229,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1960 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 2229 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1961 }, 2230 },
1962 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { 2231 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
1963 0, 0, PTT5_DATA, PTT4_DATA, 2232 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
1964 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 2233 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1965 }, 2234 },
1966 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { 2235 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
@@ -2000,8 +2269,8 @@ static struct pinmux_info sh7757_pinmux_info = {
2000 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, 2269 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2001 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2270 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2002 2271
2003 .first_gpio = GPIO_PTA7, 2272 .first_gpio = GPIO_PTA0,
2004 .last_gpio = GPIO_FN_D0, 2273 .last_gpio = GPIO_FN_ON_DQ0,
2005 2274
2006 .gpios = pinmux_gpios, 2275 .gpios = pinmux_gpios,
2007 .cfg_regs = pinmux_config_regs, 2276 .cfg_regs = pinmux_config_regs,
@@ -2015,5 +2284,4 @@ static int __init plat_pinmux_setup(void)
2015{ 2284{
2016 return register_pinmux(&sh7757_pinmux_info); 2285 return register_pinmux(&sh7757_pinmux_info);
2017} 2286}
2018
2019arch_initcall(plat_pinmux_setup); 2287arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
new file mode 100644
index 000000000000..aaa5338abbff
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -0,0 +1,587 @@
1/*
2 * SH-X3 prototype CPU pinmux
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <cpu/shx3.h>
14
15enum {
16 PINMUX_RESERVED = 0,
17
18 PINMUX_DATA_BEGIN,
19 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
20 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
21 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
22 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
23 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
24 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
25 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
26 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
27 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
28 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
29 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
30 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
31 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
32 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
33
34 PH5_DATA, PH4_DATA,
35 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
36 PINMUX_DATA_END,
37
38 PINMUX_INPUT_BEGIN,
39 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
40 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
41 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
42 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
43 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
44 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
45 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
46 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
47 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
48 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
49 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
50 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
51 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
52 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
53
54 PH5_IN, PH4_IN,
55 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
56 PINMUX_INPUT_END,
57
58 PINMUX_INPUT_PULLUP_BEGIN,
59 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
60 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
61 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
62 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
63 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
64 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
65 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
66 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
67 PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
68 PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
69 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
70 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
71 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
72 PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
73
74 PH5_IN_PU, PH4_IN_PU,
75 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
76 PINMUX_INPUT_PULLUP_END,
77
78 PINMUX_OUTPUT_BEGIN,
79 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
80 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
81 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
82 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
83 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
84 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
85 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
86 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
87 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
88 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
89 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
90 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
91 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
92 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
93
94 PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PINMUX_OUTPUT_END,
97
98 PINMUX_FUNCTION_BEGIN,
99 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
100 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
101 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
102 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
103 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
104 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
105 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
106 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
107 PE7_FN, PE6_FN, PE5_FN, PE4_FN,
108 PE3_FN, PE2_FN, PE1_FN, PE0_FN,
109 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
110 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
111 PG7_FN, PG6_FN, PG5_FN, PG4_FN,
112 PG3_FN, PG2_FN, PG1_FN, PG0_FN,
113
114 PH5_FN, PH4_FN,
115 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
116 PINMUX_FUNCTION_END,
117
118 PINMUX_MARK_BEGIN,
119
120 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
121 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
122 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
123
124 BACK_MARK, BREQ_MARK,
125 WE3_MARK, WE2_MARK,
126 CS6_MARK, CS5_MARK, CS4_MARK,
127 CLKOUTENB_MARK,
128
129 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
130 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
131
132 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
133
134 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
135
136 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
137 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
138 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
139 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
140
141 CE2B_MARK, CE2A_MARK, IOIS16_MARK,
142 STATUS1_MARK, STATUS0_MARK,
143
144 IRQOUT_MARK,
145
146 PINMUX_MARK_END,
147};
148
149static pinmux_enum_t shx3_pinmux_data[] = {
150
151 /* PA GPIO */
152 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
153 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
154 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
155 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
156 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
157 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
158 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
159 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
160
161 /* PB GPIO */
162 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
163 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
164 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
165 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
166 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
167 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
168 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
169 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
170
171 /* PC GPIO */
172 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
173 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
174 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
175 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
176 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
177 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
178 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
179 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
180
181 /* PD GPIO */
182 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
183 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
184 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
185 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
186 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
187 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
188 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
189 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
190
191 /* PE GPIO */
192 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
193 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
194 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
195 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
196 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
197 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
198 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
199 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
200
201 /* PF GPIO */
202 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
203 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
204 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
205 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
206 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
207 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
208 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
209 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
210
211 /* PG GPIO */
212 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
213 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
214 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
215 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
216 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
217 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
218 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
219 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
220
221 /* PH GPIO */
222 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
223 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
224 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
225 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
226 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
227 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
228
229 /* PA FN */
230 PINMUX_DATA(D31_MARK, PA7_FN),
231 PINMUX_DATA(D30_MARK, PA6_FN),
232 PINMUX_DATA(D29_MARK, PA5_FN),
233 PINMUX_DATA(D28_MARK, PA4_FN),
234 PINMUX_DATA(D27_MARK, PA3_FN),
235 PINMUX_DATA(D26_MARK, PA2_FN),
236 PINMUX_DATA(D25_MARK, PA1_FN),
237 PINMUX_DATA(D24_MARK, PA0_FN),
238
239 /* PB FN */
240 PINMUX_DATA(D23_MARK, PB7_FN),
241 PINMUX_DATA(D22_MARK, PB6_FN),
242 PINMUX_DATA(D21_MARK, PB5_FN),
243 PINMUX_DATA(D20_MARK, PB4_FN),
244 PINMUX_DATA(D19_MARK, PB3_FN),
245 PINMUX_DATA(D18_MARK, PB2_FN),
246 PINMUX_DATA(D17_MARK, PB1_FN),
247 PINMUX_DATA(D16_MARK, PB0_FN),
248
249 /* PC FN */
250 PINMUX_DATA(BACK_MARK, PC7_FN),
251 PINMUX_DATA(BREQ_MARK, PC6_FN),
252 PINMUX_DATA(WE3_MARK, PC5_FN),
253 PINMUX_DATA(WE2_MARK, PC4_FN),
254 PINMUX_DATA(CS6_MARK, PC3_FN),
255 PINMUX_DATA(CS5_MARK, PC2_FN),
256 PINMUX_DATA(CS4_MARK, PC1_FN),
257 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
258
259 /* PD FN */
260 PINMUX_DATA(DACK3_MARK, PD7_FN),
261 PINMUX_DATA(DACK2_MARK, PD6_FN),
262 PINMUX_DATA(DACK1_MARK, PD5_FN),
263 PINMUX_DATA(DACK0_MARK, PD4_FN),
264 PINMUX_DATA(DREQ3_MARK, PD3_FN),
265 PINMUX_DATA(DREQ2_MARK, PD2_FN),
266 PINMUX_DATA(DREQ1_MARK, PD1_FN),
267 PINMUX_DATA(DREQ0_MARK, PD0_FN),
268
269 /* PE FN */
270 PINMUX_DATA(IRQ3_MARK, PE7_FN),
271 PINMUX_DATA(IRQ2_MARK, PE6_FN),
272 PINMUX_DATA(IRQ1_MARK, PE5_FN),
273 PINMUX_DATA(IRQ0_MARK, PE4_FN),
274 PINMUX_DATA(DRAK3_MARK, PE3_FN),
275 PINMUX_DATA(DRAK2_MARK, PE2_FN),
276 PINMUX_DATA(DRAK1_MARK, PE1_FN),
277 PINMUX_DATA(DRAK0_MARK, PE0_FN),
278
279 /* PF FN */
280 PINMUX_DATA(SCK3_MARK, PF7_FN),
281 PINMUX_DATA(SCK2_MARK, PF6_FN),
282 PINMUX_DATA(SCK1_MARK, PF5_FN),
283 PINMUX_DATA(SCK0_MARK, PF4_FN),
284 PINMUX_DATA(IRL3_MARK, PF3_FN),
285 PINMUX_DATA(IRL2_MARK, PF2_FN),
286 PINMUX_DATA(IRL1_MARK, PF1_FN),
287 PINMUX_DATA(IRL0_MARK, PF0_FN),
288
289 /* PG FN */
290 PINMUX_DATA(TXD3_MARK, PG7_FN),
291 PINMUX_DATA(TXD2_MARK, PG6_FN),
292 PINMUX_DATA(TXD1_MARK, PG5_FN),
293 PINMUX_DATA(TXD0_MARK, PG4_FN),
294 PINMUX_DATA(RXD3_MARK, PG3_FN),
295 PINMUX_DATA(RXD2_MARK, PG2_FN),
296 PINMUX_DATA(RXD1_MARK, PG1_FN),
297 PINMUX_DATA(RXD0_MARK, PG0_FN),
298
299 /* PH FN */
300 PINMUX_DATA(CE2B_MARK, PH5_FN),
301 PINMUX_DATA(CE2A_MARK, PH4_FN),
302 PINMUX_DATA(IOIS16_MARK, PH3_FN),
303 PINMUX_DATA(STATUS1_MARK, PH2_FN),
304 PINMUX_DATA(STATUS0_MARK, PH1_FN),
305 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
306};
307
308static struct pinmux_gpio shx3_pinmux_gpios[] = {
309 /* PA */
310 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
311 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
312 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
313 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
314 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
315 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
316 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
317 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
318
319 /* PB */
320 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
321 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
322 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
323 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
324 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
325 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
326 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
327 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
328
329 /* PC */
330 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
331 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
332 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
333 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
334 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
335 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
336 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
337 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
338
339 /* PD */
340 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
341 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
342 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
343 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
344 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
345 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
346 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
347 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
348
349 /* PE */
350 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
351 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
352 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
353 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
354 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
355 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
356 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
357 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
358
359 /* PF */
360 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
361 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
362 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
363 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
364 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
365 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
366 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
367 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
368
369 /* PG */
370 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
371 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
372 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
373 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
374 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
375 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
376 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
377 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
378
379 /* PH */
380 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
381 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
382 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
383 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
384 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
385 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
386
387 /* FN */
388 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
389 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
390 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
391 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
392 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
393 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
394 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
395 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
396 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
397 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
398 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
399 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
400 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
401 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
402 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
403 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
404 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
405 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
406 PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK),
407 PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK),
408 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
409 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
410 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
411 PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK),
412 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
413 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
414 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
415 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
416 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
417 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
418 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
419 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
420 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
421 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
422 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
423 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
424 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
425 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
426 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
427 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
428 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
429 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
430 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
431 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
432 PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK),
433 PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK),
434 PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK),
435 PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK),
436 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
437 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
438 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
439 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
440 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
441 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
442 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
443 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
444 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
445 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
446 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
447 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
448 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
449 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
450};
451
452static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
453 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
454 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
455 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
456 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
457 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
458 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
459 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
460 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
461 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
462 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
463 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
464 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
465 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
466 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
467 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
468 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
469 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
470 },
471 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
472 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
473 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
474 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
475 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
476 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
477 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
478 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
479 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
480 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
481 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
482 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
483 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
484 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
485 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
486 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
487 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
488 },
489 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
490 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
491 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
492 PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
493 PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
494 PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
495 PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
496 PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
497 PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
498 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
499 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
500 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
501 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
502 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
503 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
504 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
505 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
506 },
507 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
508 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
509 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
510 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
511 PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
512 PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
513 PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
514 PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
515 PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
516 0, 0, 0, 0,
517 0, 0, 0, 0,
518 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
519 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
520 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
521 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
522 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
523 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
524 },
525 { },
526};
527
528static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
529 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
530 0, 0, 0, 0, 0, 0, 0, 0,
531 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
532 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
533 0, 0, 0, 0, 0, 0, 0, 0,
534 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
535 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
536 },
537 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
538 0, 0, 0, 0, 0, 0, 0, 0,
539 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
540 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
541 0, 0, 0, 0, 0, 0, 0, 0,
542 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
543 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
544 },
545 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
546 0, 0, 0, 0, 0, 0, 0, 0,
547 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
548 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
549 0, 0, 0, 0, 0, 0, 0, 0,
550 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
551 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
552 },
553 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
554 0, 0, 0, 0, 0, 0, 0, 0,
555 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
556 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
557 0, 0, 0, 0, 0, 0, 0, 0,
558 0, 0, PH5_DATA, PH4_DATA,
559 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
560 },
561 { },
562};
563
564static struct pinmux_info shx3_pinmux_info = {
565 .name = "shx3_pfc",
566 .reserved_id = PINMUX_RESERVED,
567 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
568 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
569 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
570 PINMUX_INPUT_PULLUP_END },
571 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
572 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
573 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
574 .first_gpio = GPIO_PA7,
575 .last_gpio = GPIO_FN_IRQOUT,
576 .gpios = shx3_pinmux_gpios,
577 .gpio_data = shx3_pinmux_data,
578 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
579 .cfg_regs = shx3_pinmux_config_regs,
580 .data_regs = shx3_pinmux_data_regs,
581};
582
583static int __init shx3_pinmux_setup(void)
584{
585 return register_pinmux(&shx3_pinmux_info);
586}
587arch_initcall(shx3_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 3681cafdb4af..1b8848317e9c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000, 20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 }, 25 .irqs = { 80, 80, 80, 80 },
24}; 26};
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
34static struct plat_sci_port scif1_platform_data = { 36static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xffe10000, 37 .mapbase = 0xffe10000,
36 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2,
37 .type = PORT_SCIF, 41 .type = PORT_SCIF,
38 .irqs = { 81, 81, 81, 81 }, 42 .irqs = { 81, 81, 81, 81 },
39}; 43};
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
49static struct plat_sci_port scif2_platform_data = { 53static struct plat_sci_port scif2_platform_data = {
50 .mapbase = 0xffe20000, 54 .mapbase = 0xffe20000,
51 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF, 58 .type = PORT_SCIF,
53 .irqs = { 82, 82, 82, 82 }, 59 .irqs = { 82, 82, 82, 82 },
54}; 60};
@@ -64,6 +70,8 @@ static struct platform_device scif2_device = {
64static struct plat_sci_port scif3_platform_data = { 70static struct plat_sci_port scif3_platform_data = {
65 .mapbase = 0xffe30000, 71 .mapbase = 0xffe30000,
66 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2,
67 .type = PORT_SCIF, 75 .type = PORT_SCIF,
68 .irqs = { 83, 83, 83, 83 }, 76 .irqs = { 83, 83, 83, 83 },
69}; 77};
@@ -360,6 +368,8 @@ void __init plat_early_device_setup(void)
360 368
361enum { 369enum {
362 UNUSED = 0, 370 UNUSED = 0,
371 ENABLED,
372 DISABLED,
363 373
364 /* interrupt sources */ 374 /* interrupt sources */
365 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 375 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -375,15 +385,13 @@ enum {
375 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 385 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
376 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 386 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
377 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 387 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
378 IRDA, 388 IRDA, SDHI, CMT, TSIF, SIU,
379 SDHI0, SDHI1, SDHI2, SDHI3,
380 CMT, TSIF, SIU,
381 TMU0, TMU1, TMU2, 389 TMU0, TMU1, TMU2,
382 JPU, LCDC, 390 JPU, LCDC,
383 391
384 /* interrupt groups */ 392 /* interrupt groups */
385 393
386 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, 394 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
387}; 395};
388 396
389static struct intc_vect vectors[] __initdata = { 397static struct intc_vect vectors[] __initdata = {
@@ -412,8 +420,8 @@ static struct intc_vect vectors[] __initdata = {
412 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 420 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
413 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 421 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
414 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 422 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
415 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 423 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
416 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 424 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
417 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 425 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
418 INTC_VECT(SIU, 0xf80), 426 INTC_VECT(SIU, 0xf80),
419 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 427 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -431,7 +439,6 @@ static struct intc_group groups[] __initdata = {
431 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 439 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
432 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 440 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
433 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 441 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
434 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
435 INTC_GROUP(USB, USBI0, USBI1), 442 INTC_GROUP(USB, USBI0, USBI1),
436}; 443};
437 444
@@ -452,7 +459,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
452 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 459 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
453 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 460 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
454 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 461 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
455 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 462 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
456 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 463 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
457 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 464 { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
458 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 465 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -488,9 +495,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
488 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 495 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
489}; 496};
490 497
491static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, 498static struct intc_desc intc_desc __initdata = {
492 mask_registers, prio_registers, sense_registers, 499 .name = "sh7343",
493 ack_registers); 500 .force_enable = ENABLED,
501 .force_disable = DISABLED,
502 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
503 prio_registers, sense_registers, ack_registers),
504};
494 505
495void __init plat_irq_setup(void) 506void __init plat_irq_setup(void)
496{ 507{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 8dab9e1bbd89..82616af64d62 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -21,6 +21,8 @@
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000, 22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 26 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 27 .irqs = { 80, 80, 80, 80 },
26}; 28};
@@ -319,6 +321,8 @@ void __init plat_early_device_setup(void)
319 321
320enum { 322enum {
321 UNUSED=0, 323 UNUSED=0,
324 ENABLED,
325 DISABLED,
322 326
323 /* interrupt sources */ 327 /* interrupt sources */
324 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 328 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -332,14 +336,13 @@ enum {
332 DENC, MSIOF, 336 DENC, MSIOF,
333 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 337 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
334 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 338 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
335 SDHI0, SDHI1, SDHI2, SDHI3, 339 SDHI, CMT, TSIF, SIU,
336 CMT, TSIF, SIU,
337 TMU0, TMU1, TMU2, 340 TMU0, TMU1, TMU2,
338 VEU2, LCDC, 341 VEU2, LCDC,
339 342
340 /* interrupt groups */ 343 /* interrupt groups */
341 344
342 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 345 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
343}; 346};
344 347
345static struct intc_vect vectors[] __initdata = { 348static struct intc_vect vectors[] __initdata = {
@@ -364,8 +367,8 @@ static struct intc_vect vectors[] __initdata = {
364 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 367 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
365 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 368 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
366 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 369 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
367 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 370 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
368 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 371 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
369 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 372 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
370 INTC_VECT(SIU, 0xf80), 373 INTC_VECT(SIU, 0xf80),
371 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 374 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -381,7 +384,6 @@ static struct intc_group groups[] __initdata = {
381 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 384 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
382 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 385 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
383 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 386 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
384 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
385}; 387};
386 388
387static struct intc_mask_reg mask_registers[] __initdata = { 389static struct intc_mask_reg mask_registers[] __initdata = {
@@ -403,7 +405,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
403 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 405 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
404 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 406 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
405 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 407 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
406 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 408 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
407 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 409 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
408 { 0, 0, 0, CMT, 0, USB, } }, 410 { 0, 0, 0, CMT, 0, USB, } },
409 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 411 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -441,9 +443,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
441 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 443 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
442}; 444};
443 445
444static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 446static struct intc_desc intc_desc __initdata = {
445 mask_registers, prio_registers, sense_registers, 447 .name = "sh7366",
446 ack_registers); 448 .force_enable = ENABLED,
449 .force_disable = DISABLED,
450 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
451 prio_registers, sense_registers, ack_registers),
452};
447 453
448void __init plat_irq_setup(void) 454void __init plat_irq_setup(void)
449{ 455{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 156ccc960015..5813d8023619 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -181,6 +181,8 @@ struct platform_device dma_device = {
181static struct plat_sci_port scif0_platform_data = { 181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000, 182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF, 183 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 186 .type = PORT_SCIF,
185 .irqs = { 80, 80, 80, 80 }, 187 .irqs = { 80, 80, 80, 80 },
186}; 188};
@@ -196,6 +198,8 @@ static struct platform_device scif0_device = {
196static struct plat_sci_port scif1_platform_data = { 198static struct plat_sci_port scif1_platform_data = {
197 .mapbase = 0xffe10000, 199 .mapbase = 0xffe10000,
198 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2,
199 .type = PORT_SCIF, 203 .type = PORT_SCIF,
200 .irqs = { 81, 81, 81, 81 }, 204 .irqs = { 81, 81, 81, 81 },
201}; 205};
@@ -211,6 +215,8 @@ static struct platform_device scif1_device = {
211static struct plat_sci_port scif2_platform_data = { 215static struct plat_sci_port scif2_platform_data = {
212 .mapbase = 0xffe20000, 216 .mapbase = 0xffe20000,
213 .flags = UPF_BOOT_AUTOCONF, 217 .flags = UPF_BOOT_AUTOCONF,
218 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
214 .type = PORT_SCIF, 220 .type = PORT_SCIF,
215 .irqs = { 82, 82, 82, 82 }, 221 .irqs = { 82, 82, 82, 82 },
216}; 222};
@@ -551,7 +557,7 @@ static struct resource siu_resources[] = {
551}; 557};
552 558
553static struct platform_device siu_device = { 559static struct platform_device siu_device = {
554 .name = "sh_siu", 560 .name = "siu-pcm-audio",
555 .id = -1, 561 .id = -1,
556 .dev = { 562 .dev = {
557 .platform_data = &siu_platform_data, 563 .platform_data = &siu_platform_data,
@@ -699,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
699 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
700 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
701 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
702 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 708 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
703 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
704 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 710 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
705 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 0eadefdbbba1..072382280f96 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -24,6 +24,8 @@
24static struct plat_sci_port scif0_platform_data = { 24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000, 25 .mapbase = 0xffe00000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2,
27 .type = PORT_SCIF, 29 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 30 .irqs = { 80, 80, 80, 80 },
29}; 31};
@@ -39,6 +41,8 @@ static struct platform_device scif0_device = {
39static struct plat_sci_port scif1_platform_data = { 41static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffe10000, 42 .mapbase = 0xffe10000,
41 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 46 .type = PORT_SCIF,
43 .irqs = { 81, 81, 81, 81 }, 47 .irqs = { 81, 81, 81, 81 },
44}; 48};
@@ -54,6 +58,8 @@ static struct platform_device scif1_device = {
54static struct plat_sci_port scif2_platform_data = { 58static struct plat_sci_port scif2_platform_data = {
55 .mapbase = 0xffe20000, 59 .mapbase = 0xffe20000,
56 .flags = UPF_BOOT_AUTOCONF, 60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2,
57 .type = PORT_SCIF, 63 .type = PORT_SCIF,
58 .irqs = { 82, 82, 82, 82 }, 64 .irqs = { 82, 82, 82, 82 },
59}; 65};
@@ -69,6 +75,8 @@ static struct platform_device scif2_device = {
69static struct plat_sci_port scif3_platform_data = { 75static struct plat_sci_port scif3_platform_data = {
70 .mapbase = 0xa4e30000, 76 .mapbase = 0xa4e30000,
71 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79 .scbrr_algo_id = SCBRR_ALGO_3,
72 .type = PORT_SCIFA, 80 .type = PORT_SCIFA,
73 .irqs = { 56, 56, 56, 56 }, 81 .irqs = { 56, 56, 56, 56 },
74}; 82};
@@ -84,6 +92,8 @@ static struct platform_device scif3_device = {
84static struct plat_sci_port scif4_platform_data = { 92static struct plat_sci_port scif4_platform_data = {
85 .mapbase = 0xa4e40000, 93 .mapbase = 0xa4e40000,
86 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96 .scbrr_algo_id = SCBRR_ALGO_3,
87 .type = PORT_SCIFA, 97 .type = PORT_SCIFA,
88 .irqs = { 88, 88, 88, 88 }, 98 .irqs = { 88, 88, 88, 88 },
89}; 99};
@@ -99,6 +109,8 @@ static struct platform_device scif4_device = {
99static struct plat_sci_port scif5_platform_data = { 109static struct plat_sci_port scif5_platform_data = {
100 .mapbase = 0xa4e50000, 110 .mapbase = 0xa4e50000,
101 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113 .scbrr_algo_id = SCBRR_ALGO_3,
102 .type = PORT_SCIFA, 114 .type = PORT_SCIFA,
103 .irqs = { 109, 109, 109, 109 }, 115 .irqs = { 109, 109, 109, 109 },
104}; 116};
@@ -719,7 +731,7 @@ static struct intc_group groups[] __initdata = {
719static struct intc_mask_reg mask_registers[] __initdata = { 731static struct intc_mask_reg mask_registers[] __initdata = {
720 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 732 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
721 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 733 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
722 0, DISABLED, ENABLED, ENABLED } }, 734 0, ENABLED, ENABLED, ENABLED } },
723 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 735 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
724 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 736 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
725 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 737 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -736,7 +748,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
736 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 748 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
737 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 749 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
738 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 750 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
739 { 0, DISABLED, ENABLED, ENABLED, 751 { 0, ENABLED, ENABLED, ENABLED,
740 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 752 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
741 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 753 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
742 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 754 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 79c556e56262..134a397b1918 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -93,6 +93,46 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
94 .mid_rid = 0x36, 94 .mid_rid = 0x36,
95 }, { 95 }, {
96 .slave_id = SHDMA_SLAVE_USB0D0_TX,
97 .addr = 0xA4D80100,
98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
99 .mid_rid = 0x73,
100 }, {
101 .slave_id = SHDMA_SLAVE_USB0D0_RX,
102 .addr = 0xA4D80100,
103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
104 .mid_rid = 0x73,
105 }, {
106 .slave_id = SHDMA_SLAVE_USB0D1_TX,
107 .addr = 0xA4D80120,
108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
109 .mid_rid = 0x77,
110 }, {
111 .slave_id = SHDMA_SLAVE_USB0D1_RX,
112 .addr = 0xA4D80120,
113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
114 .mid_rid = 0x77,
115 }, {
116 .slave_id = SHDMA_SLAVE_USB1D0_TX,
117 .addr = 0xA4D90100,
118 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
119 .mid_rid = 0xab,
120 }, {
121 .slave_id = SHDMA_SLAVE_USB1D0_RX,
122 .addr = 0xA4D90100,
123 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
124 .mid_rid = 0xab,
125 }, {
126 .slave_id = SHDMA_SLAVE_USB1D1_TX,
127 .addr = 0xA4D90120,
128 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
129 .mid_rid = 0xaf,
130 }, {
131 .slave_id = SHDMA_SLAVE_USB1D1_RX,
132 .addr = 0xA4D90120,
133 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
134 .mid_rid = 0xaf,
135 }, {
96 .slave_id = SHDMA_SLAVE_SDHI0_TX, 136 .slave_id = SHDMA_SLAVE_SDHI0_TX,
97 .addr = 0x04ce0030, 137 .addr = 0x04ce0030,
98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 138 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
@@ -257,6 +297,8 @@ static struct platform_device dma1_device = {
257static struct plat_sci_port scif0_platform_data = { 297static struct plat_sci_port scif0_platform_data = {
258 .mapbase = 0xffe00000, 298 .mapbase = 0xffe00000,
259 .flags = UPF_BOOT_AUTOCONF, 299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
301 .scbrr_algo_id = SCBRR_ALGO_2,
260 .type = PORT_SCIF, 302 .type = PORT_SCIF,
261 .irqs = { 80, 80, 80, 80 }, 303 .irqs = { 80, 80, 80, 80 },
262}; 304};
@@ -272,6 +314,8 @@ static struct platform_device scif0_device = {
272static struct plat_sci_port scif1_platform_data = { 314static struct plat_sci_port scif1_platform_data = {
273 .mapbase = 0xffe10000, 315 .mapbase = 0xffe10000,
274 .flags = UPF_BOOT_AUTOCONF, 316 .flags = UPF_BOOT_AUTOCONF,
317 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
318 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF, 319 .type = PORT_SCIF,
276 .irqs = { 81, 81, 81, 81 }, 320 .irqs = { 81, 81, 81, 81 },
277}; 321};
@@ -287,6 +331,8 @@ static struct platform_device scif1_device = {
287static struct plat_sci_port scif2_platform_data = { 331static struct plat_sci_port scif2_platform_data = {
288 .mapbase = 0xffe20000, 332 .mapbase = 0xffe20000,
289 .flags = UPF_BOOT_AUTOCONF, 333 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
290 .type = PORT_SCIF, 336 .type = PORT_SCIF,
291 .irqs = { 82, 82, 82, 82 }, 337 .irqs = { 82, 82, 82, 82 },
292}; 338};
@@ -302,6 +348,8 @@ static struct platform_device scif2_device = {
302static struct plat_sci_port scif3_platform_data = { 348static struct plat_sci_port scif3_platform_data = {
303 .mapbase = 0xa4e30000, 349 .mapbase = 0xa4e30000,
304 .flags = UPF_BOOT_AUTOCONF, 350 .flags = UPF_BOOT_AUTOCONF,
351 .scscr = SCSCR_RE | SCSCR_TE,
352 .scbrr_algo_id = SCBRR_ALGO_3,
305 .type = PORT_SCIFA, 353 .type = PORT_SCIFA,
306 .irqs = { 56, 56, 56, 56 }, 354 .irqs = { 56, 56, 56, 56 },
307}; 355};
@@ -317,6 +365,8 @@ static struct platform_device scif3_device = {
317static struct plat_sci_port scif4_platform_data = { 365static struct plat_sci_port scif4_platform_data = {
318 .mapbase = 0xa4e40000, 366 .mapbase = 0xa4e40000,
319 .flags = UPF_BOOT_AUTOCONF, 367 .flags = UPF_BOOT_AUTOCONF,
368 .scscr = SCSCR_RE | SCSCR_TE,
369 .scbrr_algo_id = SCBRR_ALGO_3,
320 .type = PORT_SCIFA, 370 .type = PORT_SCIFA,
321 .irqs = { 88, 88, 88, 88 }, 371 .irqs = { 88, 88, 88, 88 },
322}; 372};
@@ -332,6 +382,8 @@ static struct platform_device scif4_device = {
332static struct plat_sci_port scif5_platform_data = { 382static struct plat_sci_port scif5_platform_data = {
333 .mapbase = 0xa4e50000, 383 .mapbase = 0xa4e50000,
334 .flags = UPF_BOOT_AUTOCONF, 384 .flags = UPF_BOOT_AUTOCONF,
385 .scscr = SCSCR_RE | SCSCR_TE,
386 .scbrr_algo_id = SCBRR_ALGO_3,
335 .type = PORT_SCIFA, 387 .type = PORT_SCIFA,
336 .irqs = { 109, 109, 109, 109 }, 388 .irqs = { 109, 109, 109, 109 },
337}; 389};
@@ -524,6 +576,70 @@ static struct platform_device veu1_device = {
524 }, 576 },
525}; 577};
526 578
579/* BEU0 */
580static struct uio_info beu0_platform_data = {
581 .name = "BEU0",
582 .version = "0",
583 .irq = evt2irq(0x8A0),
584};
585
586static struct resource beu0_resources[] = {
587 [0] = {
588 .name = "BEU0",
589 .start = 0xfe930000,
590 .end = 0xfe933400,
591 .flags = IORESOURCE_MEM,
592 },
593 [1] = {
594 /* place holder for contiguous memory */
595 },
596};
597
598static struct platform_device beu0_device = {
599 .name = "uio_pdrv_genirq",
600 .id = 6,
601 .dev = {
602 .platform_data = &beu0_platform_data,
603 },
604 .resource = beu0_resources,
605 .num_resources = ARRAY_SIZE(beu0_resources),
606 .archdata = {
607 .hwblk_id = HWBLK_BEU0,
608 },
609};
610
611/* BEU1 */
612static struct uio_info beu1_platform_data = {
613 .name = "BEU1",
614 .version = "0",
615 .irq = evt2irq(0xA00),
616};
617
618static struct resource beu1_resources[] = {
619 [0] = {
620 .name = "BEU1",
621 .start = 0xfe940000,
622 .end = 0xfe943400,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 /* place holder for contiguous memory */
627 },
628};
629
630static struct platform_device beu1_device = {
631 .name = "uio_pdrv_genirq",
632 .id = 7,
633 .dev = {
634 .platform_data = &beu1_platform_data,
635 },
636 .resource = beu1_resources,
637 .num_resources = ARRAY_SIZE(beu1_resources),
638 .archdata = {
639 .hwblk_id = HWBLK_BEU1,
640 },
641};
642
527static struct sh_timer_config cmt_platform_data = { 643static struct sh_timer_config cmt_platform_data = {
528 .channel_offset = 0x60, 644 .channel_offset = 0x60,
529 .timer_bit = 5, 645 .timer_bit = 5,
@@ -857,6 +973,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
857 &vpu_device, 973 &vpu_device,
858 &veu0_device, 974 &veu0_device,
859 &veu1_device, 975 &veu1_device,
976 &beu0_device,
977 &beu1_device,
860 &jpu_device, 978 &jpu_device,
861 &spu0_device, 979 &spu0_device,
862 &spu1_device, 980 &spu1_device,
@@ -1078,7 +1196,7 @@ static struct intc_group groups[] __initdata = {
1078static struct intc_mask_reg mask_registers[] __initdata = { 1196static struct intc_mask_reg mask_registers[] __initdata = {
1079 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1197 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1080 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1198 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1081 0, DISABLED, ENABLED, ENABLED } }, 1199 0, ENABLED, ENABLED, ENABLED } },
1082 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1200 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1083 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1201 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1084 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1202 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -1100,7 +1218,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
1100 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1218 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1101 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1219 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1102 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1220 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1103 { DISABLED, DISABLED, ENABLED, ENABLED, 1221 { DISABLED, ENABLED, ENABLED, ENABLED,
1104 0, 0, SCIFA5, FSI } }, 1222 0, 0, SCIFA5, FSI } },
1105 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1223 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1106 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1224 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 444aca95b20d..e915deafac89 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7757 Setup 2 * SH7757 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
5 * 5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 * 7 *
@@ -16,17 +16,23 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/sh_timer.h> 18#include <linux/sh_timer.h>
19#include <linux/sh_dma.h>
20
21#include <cpu/dma-register.h>
22#include <cpu/sh7757.h>
19 23
20static struct plat_sci_port scif2_platform_data = { 24static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */ 25 .mapbase = 0xfe4b0000, /* SCIF2 */
22 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 29 .type = PORT_SCIF,
24 .irqs = { 40, 40, 40, 40 }, 30 .irqs = { 40, 40, 40, 40 },
25}; 31};
26 32
27static struct platform_device scif2_device = { 33static struct platform_device scif2_device = {
28 .name = "sh-sci", 34 .name = "sh-sci",
29 .id = 2, 35 .id = 0,
30 .dev = { 36 .dev = {
31 .platform_data = &scif2_platform_data, 37 .platform_data = &scif2_platform_data,
32 }, 38 },
@@ -35,13 +41,15 @@ static struct platform_device scif2_device = {
35static struct plat_sci_port scif3_platform_data = { 41static struct plat_sci_port scif3_platform_data = {
36 .mapbase = 0xfe4c0000, /* SCIF3 */ 42 .mapbase = 0xfe4c0000, /* SCIF3 */
37 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
38 .type = PORT_SCIF, 46 .type = PORT_SCIF,
39 .irqs = { 76, 76, 76, 76 }, 47 .irqs = { 76, 76, 76, 76 },
40}; 48};
41 49
42static struct platform_device scif3_device = { 50static struct platform_device scif3_device = {
43 .name = "sh-sci", 51 .name = "sh-sci",
44 .id = 3, 52 .id = 1,
45 .dev = { 53 .dev = {
46 .platform_data = &scif3_platform_data, 54 .platform_data = &scif3_platform_data,
47 }, 55 },
@@ -50,13 +58,15 @@ static struct platform_device scif3_device = {
50static struct plat_sci_port scif4_platform_data = { 58static struct plat_sci_port scif4_platform_data = {
51 .mapbase = 0xfe4d0000, /* SCIF4 */ 59 .mapbase = 0xfe4d0000, /* SCIF4 */
52 .flags = UPF_BOOT_AUTOCONF, 60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2,
53 .type = PORT_SCIF, 63 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 }, 64 .irqs = { 104, 104, 104, 104 },
55}; 65};
56 66
57static struct platform_device scif4_device = { 67static struct platform_device scif4_device = {
58 .name = "sh-sci", 68 .name = "sh-sci",
59 .id = 4, 69 .id = 2,
60 .dev = { 70 .dev = {
61 .platform_data = &scif4_platform_data, 71 .platform_data = &scif4_platform_data,
62 }, 72 },
@@ -118,12 +128,598 @@ static struct platform_device tmu1_device = {
118 .num_resources = ARRAY_SIZE(tmu1_resources), 128 .num_resources = ARRAY_SIZE(tmu1_resources),
119}; 129};
120 130
131static struct resource spi0_resources[] = {
132 [0] = {
133 .start = 0xfe002000,
134 .end = 0xfe0020ff,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = 86,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143/* DMA */
144static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
145 {
146 .slave_id = SHDMA_SLAVE_SDHI_TX,
147 .addr = 0x1fe50030,
148 .chcr = SM_INC | 0x800 | 0x40000000 |
149 TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc5,
151 },
152 {
153 .slave_id = SHDMA_SLAVE_SDHI_RX,
154 .addr = 0x1fe50030,
155 .chcr = DM_INC | 0x800 | 0x40000000 |
156 TS_INDEX2VAL(XMIT_SZ_16BIT),
157 .mid_rid = 0xc6,
158 },
159 {
160 .slave_id = SHDMA_SLAVE_MMCIF_TX,
161 .addr = 0x1fcb0034,
162 .chcr = SM_INC | 0x800 | 0x40000000 |
163 TS_INDEX2VAL(XMIT_SZ_32BIT),
164 .mid_rid = 0xd3,
165 },
166 {
167 .slave_id = SHDMA_SLAVE_MMCIF_RX,
168 .addr = 0x1fcb0034,
169 .chcr = DM_INC | 0x800 | 0x40000000 |
170 TS_INDEX2VAL(XMIT_SZ_32BIT),
171 .mid_rid = 0xd7,
172 },
173};
174
175static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
176 {
177 .slave_id = SHDMA_SLAVE_SCIF2_TX,
178 .addr = 0x1f4b000c,
179 .chcr = SM_INC | 0x800 | 0x40000000 |
180 TS_INDEX2VAL(XMIT_SZ_8BIT),
181 .mid_rid = 0x21,
182 },
183 {
184 .slave_id = SHDMA_SLAVE_SCIF2_RX,
185 .addr = 0x1f4b0014,
186 .chcr = DM_INC | 0x800 | 0x40000000 |
187 TS_INDEX2VAL(XMIT_SZ_8BIT),
188 .mid_rid = 0x22,
189 },
190 {
191 .slave_id = SHDMA_SLAVE_SCIF3_TX,
192 .addr = 0x1f4c000c,
193 .chcr = SM_INC | 0x800 | 0x40000000 |
194 TS_INDEX2VAL(XMIT_SZ_8BIT),
195 .mid_rid = 0x29,
196 },
197 {
198 .slave_id = SHDMA_SLAVE_SCIF3_RX,
199 .addr = 0x1f4c0014,
200 .chcr = DM_INC | 0x800 | 0x40000000 |
201 TS_INDEX2VAL(XMIT_SZ_8BIT),
202 .mid_rid = 0x2a,
203 },
204 {
205 .slave_id = SHDMA_SLAVE_SCIF4_TX,
206 .addr = 0x1f4d000c,
207 .chcr = SM_INC | 0x800 | 0x40000000 |
208 TS_INDEX2VAL(XMIT_SZ_8BIT),
209 .mid_rid = 0x41,
210 },
211 {
212 .slave_id = SHDMA_SLAVE_SCIF4_RX,
213 .addr = 0x1f4d0014,
214 .chcr = DM_INC | 0x800 | 0x40000000 |
215 TS_INDEX2VAL(XMIT_SZ_8BIT),
216 .mid_rid = 0x42,
217 },
218};
219
220static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
221 {
222 .slave_id = SHDMA_SLAVE_RIIC0_TX,
223 .addr = 0x1e500012,
224 .chcr = SM_INC | 0x800 | 0x40000000 |
225 TS_INDEX2VAL(XMIT_SZ_8BIT),
226 .mid_rid = 0x21,
227 },
228 {
229 .slave_id = SHDMA_SLAVE_RIIC0_RX,
230 .addr = 0x1e500013,
231 .chcr = DM_INC | 0x800 | 0x40000000 |
232 TS_INDEX2VAL(XMIT_SZ_8BIT),
233 .mid_rid = 0x22,
234 },
235 {
236 .slave_id = SHDMA_SLAVE_RIIC1_TX,
237 .addr = 0x1e510012,
238 .chcr = SM_INC | 0x800 | 0x40000000 |
239 TS_INDEX2VAL(XMIT_SZ_8BIT),
240 .mid_rid = 0x29,
241 },
242 {
243 .slave_id = SHDMA_SLAVE_RIIC1_RX,
244 .addr = 0x1e510013,
245 .chcr = DM_INC | 0x800 | 0x40000000 |
246 TS_INDEX2VAL(XMIT_SZ_8BIT),
247 .mid_rid = 0x2a,
248 },
249 {
250 .slave_id = SHDMA_SLAVE_RIIC2_TX,
251 .addr = 0x1e520012,
252 .chcr = SM_INC | 0x800 | 0x40000000 |
253 TS_INDEX2VAL(XMIT_SZ_8BIT),
254 .mid_rid = 0xa1,
255 },
256 {
257 .slave_id = SHDMA_SLAVE_RIIC2_RX,
258 .addr = 0x1e520013,
259 .chcr = DM_INC | 0x800 | 0x40000000 |
260 TS_INDEX2VAL(XMIT_SZ_8BIT),
261 .mid_rid = 0xa2,
262 },
263 {
264 .slave_id = SHDMA_SLAVE_RIIC3_TX,
265 .addr = 0x1e530012,
266 .chcr = SM_INC | 0x800 | 0x40000000 |
267 TS_INDEX2VAL(XMIT_SZ_8BIT),
268 .mid_rid = 0xa9,
269 },
270 {
271 .slave_id = SHDMA_SLAVE_RIIC3_RX,
272 .addr = 0x1e530013,
273 .chcr = DM_INC | 0x800 | 0x40000000 |
274 TS_INDEX2VAL(XMIT_SZ_8BIT),
275 .mid_rid = 0xaf,
276 },
277 {
278 .slave_id = SHDMA_SLAVE_RIIC4_TX,
279 .addr = 0x1e540012,
280 .chcr = SM_INC | 0x800 | 0x40000000 |
281 TS_INDEX2VAL(XMIT_SZ_8BIT),
282 .mid_rid = 0xc5,
283 },
284 {
285 .slave_id = SHDMA_SLAVE_RIIC4_RX,
286 .addr = 0x1e540013,
287 .chcr = DM_INC | 0x800 | 0x40000000 |
288 TS_INDEX2VAL(XMIT_SZ_8BIT),
289 .mid_rid = 0xc6,
290 },
291};
292
293static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
294 {
295 .slave_id = SHDMA_SLAVE_RIIC5_TX,
296 .addr = 0x1e550012,
297 .chcr = SM_INC | 0x800 | 0x40000000 |
298 TS_INDEX2VAL(XMIT_SZ_8BIT),
299 .mid_rid = 0x21,
300 },
301 {
302 .slave_id = SHDMA_SLAVE_RIIC5_RX,
303 .addr = 0x1e550013,
304 .chcr = DM_INC | 0x800 | 0x40000000 |
305 TS_INDEX2VAL(XMIT_SZ_8BIT),
306 .mid_rid = 0x22,
307 },
308 {
309 .slave_id = SHDMA_SLAVE_RIIC6_TX,
310 .addr = 0x1e560012,
311 .chcr = SM_INC | 0x800 | 0x40000000 |
312 TS_INDEX2VAL(XMIT_SZ_8BIT),
313 .mid_rid = 0x29,
314 },
315 {
316 .slave_id = SHDMA_SLAVE_RIIC6_RX,
317 .addr = 0x1e560013,
318 .chcr = DM_INC | 0x800 | 0x40000000 |
319 TS_INDEX2VAL(XMIT_SZ_8BIT),
320 .mid_rid = 0x2a,
321 },
322 {
323 .slave_id = SHDMA_SLAVE_RIIC7_TX,
324 .addr = 0x1e570012,
325 .chcr = SM_INC | 0x800 | 0x40000000 |
326 TS_INDEX2VAL(XMIT_SZ_8BIT),
327 .mid_rid = 0x41,
328 },
329 {
330 .slave_id = SHDMA_SLAVE_RIIC7_RX,
331 .addr = 0x1e570013,
332 .chcr = DM_INC | 0x800 | 0x40000000 |
333 TS_INDEX2VAL(XMIT_SZ_8BIT),
334 .mid_rid = 0x42,
335 },
336 {
337 .slave_id = SHDMA_SLAVE_RIIC8_TX,
338 .addr = 0x1e580012,
339 .chcr = SM_INC | 0x800 | 0x40000000 |
340 TS_INDEX2VAL(XMIT_SZ_8BIT),
341 .mid_rid = 0x45,
342 },
343 {
344 .slave_id = SHDMA_SLAVE_RIIC8_RX,
345 .addr = 0x1e580013,
346 .chcr = DM_INC | 0x800 | 0x40000000 |
347 TS_INDEX2VAL(XMIT_SZ_8BIT),
348 .mid_rid = 0x46,
349 },
350 {
351 .slave_id = SHDMA_SLAVE_RIIC9_TX,
352 .addr = 0x1e590012,
353 .chcr = SM_INC | 0x800 | 0x40000000 |
354 TS_INDEX2VAL(XMIT_SZ_8BIT),
355 .mid_rid = 0x51,
356 },
357 {
358 .slave_id = SHDMA_SLAVE_RIIC9_RX,
359 .addr = 0x1e590013,
360 .chcr = DM_INC | 0x800 | 0x40000000 |
361 TS_INDEX2VAL(XMIT_SZ_8BIT),
362 .mid_rid = 0x52,
363 },
364};
365
366static const struct sh_dmae_channel sh7757_dmae_channels[] = {
367 {
368 .offset = 0,
369 .dmars = 0,
370 .dmars_bit = 0,
371 }, {
372 .offset = 0x10,
373 .dmars = 0,
374 .dmars_bit = 8,
375 }, {
376 .offset = 0x20,
377 .dmars = 4,
378 .dmars_bit = 0,
379 }, {
380 .offset = 0x30,
381 .dmars = 4,
382 .dmars_bit = 8,
383 }, {
384 .offset = 0x50,
385 .dmars = 8,
386 .dmars_bit = 0,
387 }, {
388 .offset = 0x60,
389 .dmars = 8,
390 .dmars_bit = 8,
391 }
392};
393
394static const unsigned int ts_shift[] = TS_SHIFT;
395
396static struct sh_dmae_pdata dma0_platform_data = {
397 .slave = sh7757_dmae0_slaves,
398 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
399 .channel = sh7757_dmae_channels,
400 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
401 .ts_low_shift = CHCR_TS_LOW_SHIFT,
402 .ts_low_mask = CHCR_TS_LOW_MASK,
403 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
404 .ts_high_mask = CHCR_TS_HIGH_MASK,
405 .ts_shift = ts_shift,
406 .ts_shift_num = ARRAY_SIZE(ts_shift),
407 .dmaor_init = DMAOR_INIT,
408};
409
410static struct sh_dmae_pdata dma1_platform_data = {
411 .slave = sh7757_dmae1_slaves,
412 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
413 .channel = sh7757_dmae_channels,
414 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
415 .ts_low_shift = CHCR_TS_LOW_SHIFT,
416 .ts_low_mask = CHCR_TS_LOW_MASK,
417 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
418 .ts_high_mask = CHCR_TS_HIGH_MASK,
419 .ts_shift = ts_shift,
420 .ts_shift_num = ARRAY_SIZE(ts_shift),
421 .dmaor_init = DMAOR_INIT,
422};
423
424static struct sh_dmae_pdata dma2_platform_data = {
425 .slave = sh7757_dmae2_slaves,
426 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
427 .channel = sh7757_dmae_channels,
428 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
429 .ts_low_shift = CHCR_TS_LOW_SHIFT,
430 .ts_low_mask = CHCR_TS_LOW_MASK,
431 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
432 .ts_high_mask = CHCR_TS_HIGH_MASK,
433 .ts_shift = ts_shift,
434 .ts_shift_num = ARRAY_SIZE(ts_shift),
435 .dmaor_init = DMAOR_INIT,
436};
437
438static struct sh_dmae_pdata dma3_platform_data = {
439 .slave = sh7757_dmae3_slaves,
440 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
441 .channel = sh7757_dmae_channels,
442 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
443 .ts_low_shift = CHCR_TS_LOW_SHIFT,
444 .ts_low_mask = CHCR_TS_LOW_MASK,
445 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
446 .ts_high_mask = CHCR_TS_HIGH_MASK,
447 .ts_shift = ts_shift,
448 .ts_shift_num = ARRAY_SIZE(ts_shift),
449 .dmaor_init = DMAOR_INIT,
450};
451
452/* channel 0 to 5 */
453static struct resource sh7757_dmae0_resources[] = {
454 [0] = {
455 /* Channel registers and DMAOR */
456 .start = 0xff608020,
457 .end = 0xff60808f,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 /* DMARSx */
462 .start = 0xff609000,
463 .end = 0xff60900b,
464 .flags = IORESOURCE_MEM,
465 },
466 {
467 .start = 34,
468 .end = 34,
469 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
470 },
471};
472
473/* channel 6 to 11 */
474static struct resource sh7757_dmae1_resources[] = {
475 [0] = {
476 /* Channel registers and DMAOR */
477 .start = 0xff618020,
478 .end = 0xff61808f,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
482 /* DMARSx */
483 .start = 0xff619000,
484 .end = 0xff61900b,
485 .flags = IORESOURCE_MEM,
486 },
487 {
488 /* DMA error */
489 .start = 34,
490 .end = 34,
491 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
492 },
493 {
494 /* IRQ for channels 4 */
495 .start = 46,
496 .end = 46,
497 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
498 },
499 {
500 /* IRQ for channels 5 */
501 .start = 46,
502 .end = 46,
503 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
504 },
505 {
506 /* IRQ for channels 6 */
507 .start = 88,
508 .end = 88,
509 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
510 },
511 {
512 /* IRQ for channels 7 */
513 .start = 88,
514 .end = 88,
515 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
516 },
517 {
518 /* IRQ for channels 8 */
519 .start = 88,
520 .end = 88,
521 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
522 },
523 {
524 /* IRQ for channels 9 */
525 .start = 88,
526 .end = 88,
527 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
528 },
529 {
530 /* IRQ for channels 10 */
531 .start = 88,
532 .end = 88,
533 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
534 },
535 {
536 /* IRQ for channels 11 */
537 .start = 88,
538 .end = 88,
539 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
540 },
541};
542
543/* channel 12 to 17 */
544static struct resource sh7757_dmae2_resources[] = {
545 [0] = {
546 /* Channel registers and DMAOR */
547 .start = 0xff708020,
548 .end = 0xff70808f,
549 .flags = IORESOURCE_MEM,
550 },
551 [1] = {
552 /* DMARSx */
553 .start = 0xff709000,
554 .end = 0xff70900b,
555 .flags = IORESOURCE_MEM,
556 },
557 {
558 /* DMA error */
559 .start = 323,
560 .end = 323,
561 .flags = IORESOURCE_IRQ,
562 },
563 {
564 /* IRQ for channels 12 to 16 */
565 .start = 272,
566 .end = 276,
567 .flags = IORESOURCE_IRQ,
568 },
569 {
570 /* IRQ for channel 17 */
571 .start = 279,
572 .end = 279,
573 .flags = IORESOURCE_IRQ,
574 },
575};
576
577/* channel 18 to 23 */
578static struct resource sh7757_dmae3_resources[] = {
579 [0] = {
580 /* Channel registers and DMAOR */
581 .start = 0xff718020,
582 .end = 0xff71808f,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 /* DMARSx */
587 .start = 0xff719000,
588 .end = 0xff71900b,
589 .flags = IORESOURCE_MEM,
590 },
591 {
592 /* DMA error */
593 .start = 324,
594 .end = 324,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 /* IRQ for channels 18 to 22 */
599 .start = 280,
600 .end = 284,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 /* IRQ for channel 23 */
605 .start = 288,
606 .end = 288,
607 .flags = IORESOURCE_IRQ,
608 },
609};
610
611static struct platform_device dma0_device = {
612 .name = "sh-dma-engine",
613 .id = 0,
614 .resource = sh7757_dmae0_resources,
615 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
616 .dev = {
617 .platform_data = &dma0_platform_data,
618 },
619};
620
621static struct platform_device dma1_device = {
622 .name = "sh-dma-engine",
623 .id = 1,
624 .resource = sh7757_dmae1_resources,
625 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
626 .dev = {
627 .platform_data = &dma1_platform_data,
628 },
629};
630
631static struct platform_device dma2_device = {
632 .name = "sh-dma-engine",
633 .id = 2,
634 .resource = sh7757_dmae2_resources,
635 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
636 .dev = {
637 .platform_data = &dma2_platform_data,
638 },
639};
640
641static struct platform_device dma3_device = {
642 .name = "sh-dma-engine",
643 .id = 3,
644 .resource = sh7757_dmae3_resources,
645 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
646 .dev = {
647 .platform_data = &dma3_platform_data,
648 },
649};
650
651static struct platform_device spi0_device = {
652 .name = "sh_spi",
653 .id = 0,
654 .dev = {
655 .dma_mask = NULL,
656 .coherent_dma_mask = 0xffffffff,
657 },
658 .num_resources = ARRAY_SIZE(spi0_resources),
659 .resource = spi0_resources,
660};
661
662static struct resource usb_ehci_resources[] = {
663 [0] = {
664 .start = 0xfe4f1000,
665 .end = 0xfe4f10ff,
666 .flags = IORESOURCE_MEM,
667 },
668 [1] = {
669 .start = 57,
670 .end = 57,
671 .flags = IORESOURCE_IRQ,
672 },
673};
674
675static struct platform_device usb_ehci_device = {
676 .name = "sh_ehci",
677 .id = -1,
678 .dev = {
679 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
680 .coherent_dma_mask = DMA_BIT_MASK(32),
681 },
682 .num_resources = ARRAY_SIZE(usb_ehci_resources),
683 .resource = usb_ehci_resources,
684};
685
686static struct resource usb_ohci_resources[] = {
687 [0] = {
688 .start = 0xfe4f1800,
689 .end = 0xfe4f18ff,
690 .flags = IORESOURCE_MEM,
691 },
692 [1] = {
693 .start = 57,
694 .end = 57,
695 .flags = IORESOURCE_IRQ,
696 },
697};
698
699static struct platform_device usb_ohci_device = {
700 .name = "sh_ohci",
701 .id = -1,
702 .dev = {
703 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
704 .coherent_dma_mask = DMA_BIT_MASK(32),
705 },
706 .num_resources = ARRAY_SIZE(usb_ohci_resources),
707 .resource = usb_ohci_resources,
708};
709
121static struct platform_device *sh7757_devices[] __initdata = { 710static struct platform_device *sh7757_devices[] __initdata = {
122 &scif2_device, 711 &scif2_device,
123 &scif3_device, 712 &scif3_device,
124 &scif4_device, 713 &scif4_device,
125 &tmu0_device, 714 &tmu0_device,
126 &tmu1_device, 715 &tmu1_device,
716 &dma0_device,
717 &dma1_device,
718 &dma2_device,
719 &dma3_device,
720 &spi0_device,
721 &usb_ehci_device,
722 &usb_ohci_device,
127}; 723};
128 724
129static int __init sh7757_devices_setup(void) 725static int __init sh7757_devices_setup(void)
@@ -163,39 +759,23 @@ enum {
163 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 759 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
164 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 760 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
165 761
166 SDHI, 762 SDHI, DVC,
167 DVC, 763 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
168 IRQ8, IRQ9, IRQ10, 764 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
169 WDT0,
170 TMU0, TMU1, TMU2, TMU2_TICPI,
171 HUDI, 765 HUDI,
172
173 ARC4, 766 ARC4,
174 DMAC0, 767 DMAC0_5, DMAC6_7, DMAC8_11,
175 IRQ11, 768 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
176 SCIF2, 769 USB0, USB1,
177 DMAC1_6,
178 USB0,
179 IRQ12,
180 JMC, 770 JMC,
181 SPI1, 771 SPI0, SPI1,
182 IRQ13, IRQ14,
183 USB1,
184 TMR01, TMR23, TMR45, 772 TMR01, TMR23, TMR45,
185 WDT1,
186 FRT, 773 FRT,
187 LPC, 774 LPC, LPC5, LPC6, LPC7, LPC8,
188 SCIF0, SCIF1, SCIF3, 775 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
189 PECI0I, PECI1I, PECI2I,
190 IRQ15,
191 ETHERC, 776 ETHERC,
192 SPI0, 777 ADC0, ADC1,
193 ADC1,
194 DMAC1_8,
195 SIM, 778 SIM,
196 TMU3, TMU4, TMU5,
197 ADC0,
198 SCIF4,
199 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 779 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
200 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 780 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
201 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 781 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
@@ -206,9 +786,23 @@ enum {
206 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 786 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
207 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 787 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
208 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 788 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
209 PCIINTA, 789 ONFICTL,
210 PCIE, 790 MMC1, MMC2,
791 ECCU,
792 PCIC,
793 G200,
794 RSPI,
211 SGPIO, 795 SGPIO,
796 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
797 DMINT20, DMINT21, DMINT22, DMINT23,
798 DDRECC,
799 TSIP,
800 PCIE_BRIDGE,
801 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
802 GETHER0, GETHER1, GETHER2,
803 PBIA, PBIB, PBIC,
804 DMAE2, DMAE3,
805 SERMUX2, SERMUX3,
212 806
213 /* interrupt groups */ 807 /* interrupt groups */
214 808
@@ -221,19 +815,18 @@ static struct intc_vect vectors[] __initdata = {
221 INTC_VECT(DVC, 0x4e0), 815 INTC_VECT(DVC, 0x4e0),
222 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 816 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
223 INTC_VECT(IRQ10, 0x540), 817 INTC_VECT(IRQ10, 0x540),
224 INTC_VECT(WDT0, 0x560),
225 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 818 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
226 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 819 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
227 INTC_VECT(HUDI, 0x600), 820 INTC_VECT(HUDI, 0x600),
228 INTC_VECT(ARC4, 0x620), 821 INTC_VECT(ARC4, 0x620),
229 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 822 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
230 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 823 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
231 INTC_VECT(DMAC0, 0x6c0), 824 INTC_VECT(DMAC0_5, 0x6c0),
232 INTC_VECT(IRQ11, 0x6e0), 825 INTC_VECT(IRQ11, 0x6e0),
233 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 826 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
234 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 827 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
235 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 828 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
236 INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), 829 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
237 INTC_VECT(USB0, 0x840), 830 INTC_VECT(USB0, 0x840),
238 INTC_VECT(IRQ12, 0x880), 831 INTC_VECT(IRQ12, 0x880),
239 INTC_VECT(JMC, 0x8a0), 832 INTC_VECT(JMC, 0x8a0),
@@ -242,7 +835,6 @@ static struct intc_vect vectors[] __initdata = {
242 INTC_VECT(USB1, 0x920), 835 INTC_VECT(USB1, 0x920),
243 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 836 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
244 INTC_VECT(TMR45, 0xa40), 837 INTC_VECT(TMR45, 0xa40),
245 INTC_VECT(WDT1, 0xa60),
246 INTC_VECT(FRT, 0xa80), 838 INTC_VECT(FRT, 0xa80),
247 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 839 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
248 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 840 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
@@ -250,14 +842,14 @@ static struct intc_vect vectors[] __initdata = {
250 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 842 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
251 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 843 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
252 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 844 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
253 INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), 845 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
254 INTC_VECT(PECI2I, 0xc40), 846 INTC_VECT(PECI2, 0xc40),
255 INTC_VECT(IRQ15, 0xc60), 847 INTC_VECT(IRQ15, 0xc60),
256 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 848 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
257 INTC_VECT(SPI0, 0xcc0), 849 INTC_VECT(SPI0, 0xcc0),
258 INTC_VECT(ADC1, 0xce0), 850 INTC_VECT(ADC1, 0xce0),
259 INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), 851 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
260 INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), 852 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
261 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 853 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
262 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 854 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
263 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 855 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
@@ -278,17 +870,47 @@ static struct intc_vect vectors[] __initdata = {
278 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 870 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
279 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 871 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
280 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 872 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
281 INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), 873 INTC_VECT(IIC6_2, 0x1920),
874 INTC_VECT(ONFICTL, 0x1960),
875 INTC_VECT(IIC6_3, 0x1980),
282 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 876 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
283 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 877 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
284 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 878 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
285 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 879 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
286 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 880 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
287 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 881 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
288 INTC_VECT(PCIINTA, 0x1ce0), 882 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
289 INTC_VECT(PCIE, 0x1e00), 883 INTC_VECT(ECCU, 0x1cc0),
290 INTC_VECT(SGPIO, 0x1f80), 884 INTC_VECT(PCIC, 0x1ce0),
291 INTC_VECT(SGPIO, 0x1fa0), 885 INTC_VECT(G200, 0x1d00),
886 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
887 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
888 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
889 INTC_VECT(PECI5, 0x1f00),
890 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
891 INTC_VECT(SGPIO, 0x1fc0),
892 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
893 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
894 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
895 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
896 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
897 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
898 INTC_VECT(DDRECC, 0x2620),
899 INTC_VECT(TSIP, 0x2640),
900 INTC_VECT(PCIE_BRIDGE, 0x27c0),
901 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
902 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
903 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
904 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
905 INTC_VECT(WDT8B, 0x2900),
906 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
907 INTC_VECT(GETHER2, 0x29a0),
908 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
909 INTC_VECT(PBIC, 0x2a40),
910 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
911 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
912 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
913 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
292}; 914};
293 915
294static struct intc_group groups[] __initdata = { 916static struct intc_group groups[] __initdata = {
@@ -312,31 +934,45 @@ static struct intc_mask_reg mask_registers[] __initdata = {
312 934
313 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 935 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
314 { 0, 0, 0, 0, 0, 0, 0, 0, 936 { 0, 0, 0, 0, 0, 0, 0, 0,
315 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, 937 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
316 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, 938 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
317 HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 939 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
318 } }, 940 } },
319 941
320 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 942 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
321 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 943 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
322 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 944 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
323 ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, 945 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
324 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 946 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
325 } }, 947 } },
326 948
327 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 949 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
328 { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, 950 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
329 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 951 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
330 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 952 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
331 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 953 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
332 } }, 954 } },
333 955
334 { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ 956 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
335 { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, 957 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
336 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 958 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
337 PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, 959 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
338 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 960 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
339 } }, 961 } },
962
963 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
964 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
965 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
966 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
967 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
968 } },
969
970 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
971 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
972 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
973 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
974 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
975 } },
340}; 976};
341 977
342#define INTPRI 0xffd00010 978#define INTPRI 0xffd00010
@@ -372,6 +1008,22 @@ static struct intc_mask_reg mask_registers[] __initdata = {
372#define INT2PRI29 0xffd100b4 1008#define INT2PRI29 0xffd100b4
373#define INT2PRI30 0xffd100b8 1009#define INT2PRI30 0xffd100b8
374#define INT2PRI31 0xffd100bc 1010#define INT2PRI31 0xffd100bc
1011#define INT2PRI32 0xffd20000
1012#define INT2PRI33 0xffd20004
1013#define INT2PRI34 0xffd20008
1014#define INT2PRI35 0xffd2000c
1015#define INT2PRI36 0xffd20010
1016#define INT2PRI37 0xffd20014
1017#define INT2PRI38 0xffd20018
1018#define INT2PRI39 0xffd2001c
1019#define INT2PRI40 0xffd200a0
1020#define INT2PRI41 0xffd200a4
1021#define INT2PRI42 0xffd200a8
1022#define INT2PRI43 0xffd200ac
1023#define INT2PRI44 0xffd200b0
1024#define INT2PRI45 0xffd200b4
1025#define INT2PRI46 0xffd200b8
1026#define INT2PRI47 0xffd200bc
375 1027
376static struct intc_prio_reg prio_registers[] __initdata = { 1028static struct intc_prio_reg prio_registers[] __initdata = {
377 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 1029 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
@@ -379,49 +1031,71 @@ static struct intc_prio_reg prio_registers[] __initdata = {
379 1031
380 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 1032 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
381 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 1033 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
382 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, 1034 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
383 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, 1035 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
384 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 1036 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
385 { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, 1037 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
386 { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, 1038 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
387 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 1039 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
388 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 1040 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
389 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 1041 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
390 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, 1042 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
391 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, 1043 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
392 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 1044 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
393 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 1045 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
394 1046
395 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 1047 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
396 { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, 1048 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
397 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 1049 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
398 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 1050 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
399 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 1051 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
400 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 1052 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
401 { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, 1053 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
402 { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, 1054 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
403 { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, 1055 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
404 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 1056 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
405 { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, 1057 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
406 { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, 1058 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
407 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, 1059 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
408 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 1060 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
409 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, 1061 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
410 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 1062 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1063 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1064 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1065 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1066 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1067 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1068 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1069 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1070 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1071 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1072 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1073 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1074 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1075 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1076 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1077 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1078 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1079};
1080
1081static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1082 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
1083 IRQ11, IRQ10, IRQ9, IRQ8 } },
411}; 1084};
412 1085
413static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 1086static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
414 mask_registers, prio_registers, NULL); 1087 mask_registers, prio_registers,
1088 sense_registers_irq8to15);
415 1089
416/* Support for external interrupt pins in IRQ mode */ 1090/* Support for external interrupt pins in IRQ mode */
417static struct intc_vect vectors_irq0123[] __initdata = { 1091static struct intc_vect vectors_irq0123[] __initdata = {
418 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 1092 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
419 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 1093 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
420}; 1094};
421 1095
422static struct intc_vect vectors_irq4567[] __initdata = { 1096static struct intc_vect vectors_irq4567[] __initdata = {
423 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 1097 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
424 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 1098 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
425}; 1099};
426 1100
427static struct intc_sense_reg sense_registers[] __initdata = { 1101static struct intc_sense_reg sense_registers[] __initdata = {
@@ -455,14 +1129,14 @@ static struct intc_vect vectors_irl0123[] __initdata = {
455}; 1129};
456 1130
457static struct intc_vect vectors_irl4567[] __initdata = { 1131static struct intc_vect vectors_irl4567[] __initdata = {
458 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), 1132 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
459 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), 1133 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
460 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), 1134 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
461 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0), 1135 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
462 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20), 1136 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
463 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60), 1137 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
464 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0), 1138 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
465 INTC_VECT(IRL4_HHHL, 0xcc0), 1139 INTC_VECT(IRL4_HHHL, 0x3c0),
466}; 1140};
467 1141
468static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 1142static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 5b5f6b005fc5..593eca6509b5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000, 20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
24}; 26};
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
34static struct plat_sci_port scif1_platform_data = { 36static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xffe08000, 37 .mapbase = 0xffe08000,
36 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
40 .scbrr_algo_id = SCBRR_ALGO_2,
37 .type = PORT_SCIF, 41 .type = PORT_SCIF,
38 .irqs = { 76, 76, 76, 76 }, 42 .irqs = { 76, 76, 76, 76 },
39}; 43};
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
49static struct plat_sci_port scif2_platform_data = { 53static struct plat_sci_port scif2_platform_data = {
50 .mapbase = 0xffe10000, 54 .mapbase = 0xffe10000,
51 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
57 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF, 58 .type = PORT_SCIF,
53 .irqs = { 104, 104, 104, 104 }, 59 .irqs = { 104, 104, 104, 104 },
54}; 60};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 7270d7fd6761..2c6aa22cf5f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -17,6 +17,8 @@
17static struct plat_sci_port scif0_platform_data = { 17static struct plat_sci_port scif0_platform_data = {
18 .mapbase = 0xff923000, 18 .mapbase = 0xff923000,
19 .flags = UPF_BOOT_AUTOCONF, 19 .flags = UPF_BOOT_AUTOCONF,
20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scbrr_algo_id = SCBRR_ALGO_2,
20 .type = PORT_SCIF, 22 .type = PORT_SCIF,
21 .irqs = { 61, 61, 61, 61 }, 23 .irqs = { 61, 61, 61, 61 },
22}; 24};
@@ -32,6 +34,8 @@ static struct platform_device scif0_device = {
32static struct plat_sci_port scif1_platform_data = { 34static struct plat_sci_port scif1_platform_data = {
33 .mapbase = 0xff924000, 35 .mapbase = 0xff924000,
34 .flags = UPF_BOOT_AUTOCONF, 36 .flags = UPF_BOOT_AUTOCONF,
37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 39 .type = PORT_SCIF,
36 .irqs = { 62, 62, 62, 62 }, 40 .irqs = { 62, 62, 62, 62 },
37}; 41};
@@ -47,6 +51,8 @@ static struct platform_device scif1_device = {
47static struct plat_sci_port scif2_platform_data = { 51static struct plat_sci_port scif2_platform_data = {
48 .mapbase = 0xff925000, 52 .mapbase = 0xff925000,
49 .flags = UPF_BOOT_AUTOCONF, 53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 56 .type = PORT_SCIF,
51 .irqs = { 63, 63, 63, 63 }, 57 .irqs = { 63, 63, 63, 63 },
52}; 58};
@@ -62,6 +68,8 @@ static struct platform_device scif2_device = {
62static struct plat_sci_port scif3_platform_data = { 68static struct plat_sci_port scif3_platform_data = {
63 .mapbase = 0xff926000, 69 .mapbase = 0xff926000,
64 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 73 .type = PORT_SCIF,
66 .irqs = { 64, 64, 64, 64 }, 74 .irqs = { 64, 64, 64, 64 },
67}; 75};
@@ -77,6 +85,8 @@ static struct platform_device scif3_device = {
77static struct plat_sci_port scif4_platform_data = { 85static struct plat_sci_port scif4_platform_data = {
78 .mapbase = 0xff927000, 86 .mapbase = 0xff927000,
79 .flags = UPF_BOOT_AUTOCONF, 87 .flags = UPF_BOOT_AUTOCONF,
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .scbrr_algo_id = SCBRR_ALGO_2,
80 .type = PORT_SCIF, 90 .type = PORT_SCIF,
81 .irqs = { 65, 65, 65, 65 }, 91 .irqs = { 65, 65, 65, 65 },
82}; 92};
@@ -92,6 +102,8 @@ static struct platform_device scif4_device = {
92static struct plat_sci_port scif5_platform_data = { 102static struct plat_sci_port scif5_platform_data = {
93 .mapbase = 0xff928000, 103 .mapbase = 0xff928000,
94 .flags = UPF_BOOT_AUTOCONF, 104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2,
95 .type = PORT_SCIF, 107 .type = PORT_SCIF,
96 .irqs = { 66, 66, 66, 66 }, 108 .irqs = { 66, 66, 66, 66 },
97}; 109};
@@ -107,6 +119,8 @@ static struct platform_device scif5_device = {
107static struct plat_sci_port scif6_platform_data = { 119static struct plat_sci_port scif6_platform_data = {
108 .mapbase = 0xff929000, 120 .mapbase = 0xff929000,
109 .flags = UPF_BOOT_AUTOCONF, 121 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2,
110 .type = PORT_SCIF, 124 .type = PORT_SCIF,
111 .irqs = { 67, 67, 67, 67 }, 125 .irqs = { 67, 67, 67, 67 },
112}; 126};
@@ -122,6 +136,8 @@ static struct platform_device scif6_device = {
122static struct plat_sci_port scif7_platform_data = { 136static struct plat_sci_port scif7_platform_data = {
123 .mapbase = 0xff92a000, 137 .mapbase = 0xff92a000,
124 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
125 .type = PORT_SCIF, 141 .type = PORT_SCIF,
126 .irqs = { 68, 68, 68, 68 }, 142 .irqs = { 68, 68, 68, 68 },
127}; 143};
@@ -137,6 +153,8 @@ static struct platform_device scif7_device = {
137static struct plat_sci_port scif8_platform_data = { 153static struct plat_sci_port scif8_platform_data = {
138 .mapbase = 0xff92b000, 154 .mapbase = 0xff92b000,
139 .flags = UPF_BOOT_AUTOCONF, 155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
140 .type = PORT_SCIF, 158 .type = PORT_SCIF,
141 .irqs = { 69, 69, 69, 69 }, 159 .irqs = { 69, 69, 69, 69 },
142}; 160};
@@ -152,6 +170,8 @@ static struct platform_device scif8_device = {
152static struct plat_sci_port scif9_platform_data = { 170static struct plat_sci_port scif9_platform_data = {
153 .mapbase = 0xff92c000, 171 .mapbase = 0xff92c000,
154 .flags = UPF_BOOT_AUTOCONF, 172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
155 .type = PORT_SCIF, 175 .type = PORT_SCIF,
156 .irqs = { 70, 70, 70, 70 }, 176 .irqs = { 70, 70, 70, 70 },
157}; 177};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 0f414864f76b..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,6 +20,8 @@
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000, 21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
23 .type = PORT_SCIF, 25 .type = PORT_SCIF,
24 .irqs = { 40, 40, 40, 40 }, 26 .irqs = { 40, 40, 40, 40 },
25}; 27};
@@ -35,6 +37,8 @@ static struct platform_device scif0_device = {
35static struct plat_sci_port scif1_platform_data = { 37static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xffe10000, 38 .mapbase = 0xffe10000,
37 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1,
38 .type = PORT_SCIF, 42 .type = PORT_SCIF,
39 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
40}; 44};
@@ -379,6 +383,7 @@ static int __init sh7780_devices_setup(void)
379 ARRAY_SIZE(sh7780_devices)); 383 ARRAY_SIZE(sh7780_devices));
380} 384}
381arch_initcall(sh7780_devices_setup); 385arch_initcall(sh7780_devices_setup);
386
382static struct platform_device *sh7780_early_devices[] __initdata = { 387static struct platform_device *sh7780_early_devices[] __initdata = {
383 &scif0_device, 388 &scif0_device,
384 &scif1_device, 389 &scif1_device,
@@ -392,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
392 397
393void __init plat_early_device_setup(void) 398void __init plat_early_device_setup(void)
394{ 399{
400 if (mach_is_sh2007()) {
401 scif0_platform_data.scscr &= ~SCSCR_CKE1;
402 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
403 scif1_platform_data.scscr &= ~SCSCR_CKE1;
404 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
405 }
406
395 early_platform_add_devices(sh7780_early_devices, 407 early_platform_add_devices(sh7780_early_devices,
396 ARRAY_SIZE(sh7780_early_devices)); 408 ARRAY_SIZE(sh7780_early_devices));
397} 409}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index c9a572bc6dc8..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -23,6 +23,8 @@
23static struct plat_sci_port scif0_platform_data = { 23static struct plat_sci_port scif0_platform_data = {
24 .mapbase = 0xffea0000, 24 .mapbase = 0xffea0000,
25 .flags = UPF_BOOT_AUTOCONF, 25 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
27 .scbrr_algo_id = SCBRR_ALGO_1,
26 .type = PORT_SCIF, 28 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 29 .irqs = { 40, 40, 40, 40 },
28}; 30};
@@ -38,6 +40,8 @@ static struct platform_device scif0_device = {
38static struct plat_sci_port scif1_platform_data = { 40static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffeb0000, 41 .mapbase = 0xffeb0000,
40 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
41 .type = PORT_SCIF, 45 .type = PORT_SCIF,
42 .irqs = { 44, 44, 44, 44 }, 46 .irqs = { 44, 44, 44, 44 },
43}; 47};
@@ -53,6 +57,8 @@ static struct platform_device scif1_device = {
53static struct plat_sci_port scif2_platform_data = { 57static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffec0000, 58 .mapbase = 0xffec0000,
55 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .scbrr_algo_id = SCBRR_ALGO_1,
56 .type = PORT_SCIF, 62 .type = PORT_SCIF,
57 .irqs = { 60, 60, 60, 60 }, 63 .irqs = { 60, 60, 60, 60 },
58}; 64};
@@ -68,6 +74,8 @@ static struct platform_device scif2_device = {
68static struct plat_sci_port scif3_platform_data = { 74static struct plat_sci_port scif3_platform_data = {
69 .mapbase = 0xffed0000, 75 .mapbase = 0xffed0000,
70 .flags = UPF_BOOT_AUTOCONF, 76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
78 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF, 79 .type = PORT_SCIF,
72 .irqs = { 61, 61, 61, 61 }, 80 .irqs = { 61, 61, 61, 61 },
73}; 81};
@@ -83,6 +91,8 @@ static struct platform_device scif3_device = {
83static struct plat_sci_port scif4_platform_data = { 91static struct plat_sci_port scif4_platform_data = {
84 .mapbase = 0xffee0000, 92 .mapbase = 0xffee0000,
85 .flags = UPF_BOOT_AUTOCONF, 93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
95 .scbrr_algo_id = SCBRR_ALGO_1,
86 .type = PORT_SCIF, 96 .type = PORT_SCIF,
87 .irqs = { 62, 62, 62, 62 }, 97 .irqs = { 62, 62, 62, 62 },
88}; 98};
@@ -98,6 +108,8 @@ static struct platform_device scif4_device = {
98static struct plat_sci_port scif5_platform_data = { 108static struct plat_sci_port scif5_platform_data = {
99 .mapbase = 0xffef0000, 109 .mapbase = 0xffef0000,
100 .flags = UPF_BOOT_AUTOCONF, 110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1,
101 .type = PORT_SCIF, 113 .type = PORT_SCIF,
102 .irqs = { 63, 63, 63, 63 }, 114 .irqs = { 63, 63, 63, 63 },
103}; 115};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 8797723231ea..beba32beb6d9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -29,6 +29,8 @@
29static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffea0000, 30 .mapbase = 0xffea0000,
31 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33 .scbrr_algo_id = SCBRR_ALGO_1,
32 .type = PORT_SCIF, 34 .type = PORT_SCIF,
33 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
34}; 36};
@@ -47,6 +49,8 @@ static struct platform_device scif0_device = {
47static struct plat_sci_port scif1_platform_data = { 49static struct plat_sci_port scif1_platform_data = {
48 .mapbase = 0xffeb0000, 50 .mapbase = 0xffeb0000,
49 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
53 .scbrr_algo_id = SCBRR_ALGO_1,
50 .type = PORT_SCIF, 54 .type = PORT_SCIF,
51 .irqs = { 44, 44, 44, 44 }, 55 .irqs = { 44, 44, 44, 44 },
52}; 56};
@@ -62,6 +66,8 @@ static struct platform_device scif1_device = {
62static struct plat_sci_port scif2_platform_data = { 66static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffec0000, 67 .mapbase = 0xffec0000,
64 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70 .scbrr_algo_id = SCBRR_ALGO_1,
65 .type = PORT_SCIF, 71 .type = PORT_SCIF,
66 .irqs = { 50, 50, 50, 50 }, 72 .irqs = { 50, 50, 50, 50 },
67}; 73};
@@ -77,6 +83,8 @@ static struct platform_device scif2_device = {
77static struct plat_sci_port scif3_platform_data = { 83static struct plat_sci_port scif3_platform_data = {
78 .mapbase = 0xffed0000, 84 .mapbase = 0xffed0000,
79 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
87 .scbrr_algo_id = SCBRR_ALGO_1,
80 .type = PORT_SCIF, 88 .type = PORT_SCIF,
81 .irqs = { 51, 51, 51, 51 }, 89 .irqs = { 51, 51, 51, 51 },
82}; 90};
@@ -92,6 +100,8 @@ static struct platform_device scif3_device = {
92static struct plat_sci_port scif4_platform_data = { 100static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xffee0000, 101 .mapbase = 0xffee0000,
94 .flags = UPF_BOOT_AUTOCONF, 102 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
104 .scbrr_algo_id = SCBRR_ALGO_1,
95 .type = PORT_SCIF, 105 .type = PORT_SCIF,
96 .irqs = { 52, 52, 52, 52 }, 106 .irqs = { 52, 52, 52, 52 },
97}; 107};
@@ -107,6 +117,8 @@ static struct platform_device scif4_device = {
107static struct plat_sci_port scif5_platform_data = { 117static struct plat_sci_port scif5_platform_data = {
108 .mapbase = 0xffef0000, 118 .mapbase = 0xffef0000,
109 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
121 .scbrr_algo_id = SCBRR_ALGO_1,
110 .type = PORT_SCIF, 122 .type = PORT_SCIF,
111 .irqs = { 53, 53, 53, 53 }, 123 .irqs = { 53, 53, 53, 53 },
112}; 124};
@@ -522,10 +534,37 @@ static struct platform_device dma0_device = {
522 }, 534 },
523}; 535};
524 536
537#define USB_EHCI_START 0xffe70000
538#define USB_OHCI_START 0xffe70400
539
540static struct resource usb_ehci_resources[] = {
541 [0] = {
542 .start = USB_EHCI_START,
543 .end = USB_EHCI_START + 0x3ff,
544 .flags = IORESOURCE_MEM,
545 },
546 [1] = {
547 .start = 77,
548 .end = 77,
549 .flags = IORESOURCE_IRQ,
550 },
551};
552
553static struct platform_device usb_ehci_device = {
554 .name = "sh_ehci",
555 .id = -1,
556 .dev = {
557 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
558 .coherent_dma_mask = DMA_BIT_MASK(32),
559 },
560 .num_resources = ARRAY_SIZE(usb_ehci_resources),
561 .resource = usb_ehci_resources,
562};
563
525static struct resource usb_ohci_resources[] = { 564static struct resource usb_ohci_resources[] = {
526 [0] = { 565 [0] = {
527 .start = 0xffe70400, 566 .start = USB_OHCI_START,
528 .end = 0xffe704ff, 567 .end = USB_OHCI_START + 0x3ff,
529 .flags = IORESOURCE_MEM, 568 .flags = IORESOURCE_MEM,
530 }, 569 },
531 [1] = { 570 [1] = {
@@ -535,12 +574,11 @@ static struct resource usb_ohci_resources[] = {
535 }, 574 },
536}; 575};
537 576
538static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
539static struct platform_device usb_ohci_device = { 577static struct platform_device usb_ohci_device = {
540 .name = "sh_ohci", 578 .name = "sh_ohci",
541 .id = -1, 579 .id = -1,
542 .dev = { 580 .dev = {
543 .dma_mask = &usb_ohci_dma_mask, 581 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
544 .coherent_dma_mask = DMA_BIT_MASK(32), 582 .coherent_dma_mask = DMA_BIT_MASK(32),
545 }, 583 },
546 .num_resources = ARRAY_SIZE(usb_ohci_resources), 584 .num_resources = ARRAY_SIZE(usb_ohci_resources),
@@ -570,6 +608,7 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
570 608
571static struct platform_device *sh7786_devices[] __initdata = { 609static struct platform_device *sh7786_devices[] __initdata = {
572 &dma0_device, 610 &dma0_device,
611 &usb_ehci_device,
573 &usb_ohci_device, 612 &usb_ohci_device,
574}; 613};
575 614
@@ -609,7 +648,7 @@ static void __init sh7786_usb_setup(void)
609 * The following settings are necessary 648 * The following settings are necessary
610 * for using the USB modules. 649 * for using the USB modules.
611 * 650 *
612 * see "USB Inital Settings" for detail 651 * see "USB Initial Settings" for detail
613 */ 652 */
614 __raw_writel(USBINITVAL1, USBINITREG1); 653 __raw_writel(USBINITVAL1, USBINITREG1);
615 __raw_writel(USBINITVAL2, USBINITREG2); 654 __raw_writel(USBINITVAL2, USBINITREG2);
@@ -629,33 +668,10 @@ static void __init sh7786_usb_setup(void)
629 } 668 }
630} 669}
631 670
632static int __init sh7786_devices_setup(void)
633{
634 int ret;
635
636 sh7786_usb_setup();
637
638 ret = platform_add_devices(sh7786_early_devices,
639 ARRAY_SIZE(sh7786_early_devices));
640 if (unlikely(ret != 0))
641 return ret;
642
643 return platform_add_devices(sh7786_devices,
644 ARRAY_SIZE(sh7786_devices));
645}
646arch_initcall(sh7786_devices_setup);
647
648void __init plat_early_device_setup(void)
649{
650 early_platform_add_devices(sh7786_early_devices,
651 ARRAY_SIZE(sh7786_early_devices));
652}
653
654enum { 671enum {
655 UNUSED = 0, 672 UNUSED = 0,
656 673
657 /* interrupt sources */ 674 /* interrupt sources */
658
659 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 675 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
660 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 676 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
661 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 677 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
@@ -693,9 +709,12 @@ enum {
693 Thermal, 709 Thermal,
694 INTICI0, INTICI1, INTICI2, INTICI3, 710 INTICI0, INTICI1, INTICI2, INTICI3,
695 INTICI4, INTICI5, INTICI6, INTICI7, 711 INTICI4, INTICI5, INTICI6, INTICI7,
712
713 /* Muxed sub-events */
714 TXI1, BRI1, RXI1, ERI1,
696}; 715};
697 716
698static struct intc_vect vectors[] __initdata = { 717static struct intc_vect sh7786_vectors[] __initdata = {
699 INTC_VECT(WDT, 0x3e0), 718 INTC_VECT(WDT, 0x3e0),
700 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), 719 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
701 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), 720 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
@@ -756,14 +775,12 @@ static struct intc_vect vectors[] __initdata = {
756 775
757#define INTDISTCR0 0xfe4100b0 776#define INTDISTCR0 0xfe4100b0
758#define INTDISTCR1 0xfe4100b4 777#define INTDISTCR1 0xfe4100b4
759#define INTACK 0xfe4100b8
760#define INTACKCLR 0xfe4100bc
761#define INT2DISTCR0 0xfe410900 778#define INT2DISTCR0 0xfe410900
762#define INT2DISTCR1 0xfe410904 779#define INT2DISTCR1 0xfe410904
763#define INT2DISTCR2 0xfe410908 780#define INT2DISTCR2 0xfe410908
764#define INT2DISTCR3 0xfe41090c 781#define INT2DISTCR3 0xfe41090c
765 782
766static struct intc_mask_reg mask_registers[] __initdata = { 783static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
767 { CnINTMSK0, CnINTMSKCLR0, 32, 784 { CnINTMSK0, CnINTMSKCLR0, 32,
768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, 785 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) }, 786 INTC_SMP_BALANCING(INTDISTCR0) },
@@ -807,7 +824,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, 824 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
808}; 825};
809 826
810static struct intc_prio_reg prio_registers[] __initdata = { 827static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
811 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 828 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
812 IRQ4, IRQ5, IRQ6, IRQ7 } }, 829 IRQ4, IRQ5, IRQ6, IRQ7 } },
813 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, 830 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
@@ -851,11 +868,27 @@ static struct intc_prio_reg prio_registers[] __initdata = {
851 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, 868 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
852}; 869};
853 870
854static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, 871static struct intc_subgroup sh7786_subgroups[] __initdata = {
855 mask_registers, prio_registers, NULL); 872 { 0xfe410c20, 32, SCIF1,
873 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
874 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
875};
876
877static struct intc_desc sh7786_intc_desc __initdata = {
878 .name = "sh7786",
879 .hw = {
880 .vectors = sh7786_vectors,
881 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
882 .mask_regs = sh7786_mask_registers,
883 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
884 .subgroups = sh7786_subgroups,
885 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
886 .prio_regs = sh7786_prio_registers,
887 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
888 },
889};
856 890
857/* Support for external interrupt pins in IRQ mode */ 891/* Support for external interrupt pins in IRQ mode */
858
859static struct intc_vect vectors_irq0123[] __initdata = { 892static struct intc_vect vectors_irq0123[] __initdata = {
860 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 893 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
861 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 894 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
@@ -866,23 +899,25 @@ static struct intc_vect vectors_irq4567[] __initdata = {
866 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 899 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
867}; 900};
868 901
869static struct intc_sense_reg sense_registers[] __initdata = { 902static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
870 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 903 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
871 IRQ4, IRQ5, IRQ6, IRQ7 } }, 904 IRQ4, IRQ5, IRQ6, IRQ7 } },
872}; 905};
873 906
874static struct intc_mask_reg ack_registers[] __initdata = { 907static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
875 { 0xfe410024, 0, 32, /* INTREQ */ 908 { 0xfe410024, 0, 32, /* INTREQ */
876 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 909 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
877}; 910};
878 911
879static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", 912static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
880 vectors_irq0123, NULL, mask_registers, 913 vectors_irq0123, NULL, sh7786_mask_registers,
881 prio_registers, sense_registers, ack_registers); 914 sh7786_prio_registers, sh7786_sense_registers,
915 sh7786_ack_registers);
882 916
883static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", 917static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
884 vectors_irq4567, NULL, mask_registers, 918 vectors_irq4567, NULL, sh7786_mask_registers,
885 prio_registers, sense_registers, ack_registers); 919 sh7786_prio_registers, sh7786_sense_registers,
920 sh7786_ack_registers);
886 921
887/* External interrupt pins in IRL mode */ 922/* External interrupt pins in IRL mode */
888 923
@@ -909,10 +944,10 @@ static struct intc_vect vectors_irl4567[] __initdata = {
909}; 944};
910 945
911static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, 946static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
912 NULL, mask_registers, NULL, NULL); 947 NULL, sh7786_mask_registers, NULL, NULL);
913 948
914static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, 949static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
915 NULL, mask_registers, NULL, NULL); 950 NULL, sh7786_mask_registers, NULL, NULL);
916 951
917#define INTC_ICR0 0xfe410000 952#define INTC_ICR0 0xfe410000
918#define INTC_INTMSK0 CnINTMSK0 953#define INTC_INTMSK0 CnINTMSK0
@@ -920,19 +955,6 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
920#define INTC_INTMSK2 INTMSK2 955#define INTC_INTMSK2 INTMSK2
921#define INTC_INTMSKCLR1 CnINTMSKCLR1 956#define INTC_INTMSKCLR1 CnINTMSKCLR1
922#define INTC_INTMSKCLR2 INTMSKCLR2 957#define INTC_INTMSKCLR2 INTMSKCLR2
923#define INTC_USERIMASK 0xfe411000
924
925#ifdef CONFIG_INTC_BALANCING
926unsigned int irq_lookup(unsigned int irq)
927{
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
929}
930
931void irq_finish(unsigned int irq)
932{
933 __raw_writel(irq2evt(irq), INTACKCLR);
934}
935#endif
936 958
937void __init plat_irq_setup(void) 959void __init plat_irq_setup(void)
938{ 960{
@@ -946,8 +968,7 @@ void __init plat_irq_setup(void)
946 /* select IRL mode for IRL3-0 + IRL7-4 */ 968 /* select IRL mode for IRL3-0 + IRL7-4 */
947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 969 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
948 970
949 register_intc_controller(&intc_desc); 971 register_intc_controller(&sh7786_intc_desc);
950 register_intc_userimask(INTC_USERIMASK);
951} 972}
952 973
953void __init plat_irq_setup_pins(int mode) 974void __init plat_irq_setup_pins(int mode)
@@ -991,3 +1012,39 @@ void __init plat_irq_setup_pins(int mode)
991void __init plat_mem_setup(void) 1012void __init plat_mem_setup(void)
992{ 1013{
993} 1014}
1015
1016static int __init sh7786_devices_setup(void)
1017{
1018 int ret, irq;
1019
1020 sh7786_usb_setup();
1021
1022 /*
1023 * De-mux SCIF1 IRQs if possible
1024 */
1025 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1026 if (irq > 0) {
1027 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1028 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1029 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1030 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1031 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1032 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1033 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1034 }
1035
1036 ret = platform_add_devices(sh7786_early_devices,
1037 ARRAY_SIZE(sh7786_early_devices));
1038 if (unlikely(ret != 0))
1039 return ret;
1040
1041 return platform_add_devices(sh7786_devices,
1042 ARRAY_SIZE(sh7786_devices));
1043}
1044arch_initcall(sh7786_devices_setup);
1045
1046void __init plat_early_device_setup(void)
1047{
1048 early_platform_add_devices(sh7786_early_devices,
1049 ARRAY_SIZE(sh7786_early_devices));
1050}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 9158bc5ea38b..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 Prototype Setup 2 * SH-X3 Prototype Setup
3 * 3 *
4 * Copyright (C) 2007 - 2009 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/gpio.h>
15#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <cpu/shx3.h>
16#include <asm/mmzone.h> 18#include <asm/mmzone.h>
17 19
18/* 20/*
@@ -27,6 +29,8 @@
27static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xffc30000, 30 .mapbase = 0xffc30000,
29 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
33 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF, 34 .type = PORT_SCIF,
31 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
32}; 36};
@@ -42,6 +46,8 @@ static struct platform_device scif0_device = {
42static struct plat_sci_port scif1_platform_data = { 46static struct plat_sci_port scif1_platform_data = {
43 .mapbase = 0xffc40000, 47 .mapbase = 0xffc40000,
44 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF,
49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
50 .scbrr_algo_id = SCBRR_ALGO_2,
45 .type = PORT_SCIF, 51 .type = PORT_SCIF,
46 .irqs = { 44, 45, 47, 46 }, 52 .irqs = { 44, 45, 47, 46 },
47}; 53};
@@ -57,6 +63,8 @@ static struct platform_device scif1_device = {
57static struct plat_sci_port scif2_platform_data = { 63static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffc60000, 64 .mapbase = 0xffc60000,
59 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
60 .type = PORT_SCIF, 68 .type = PORT_SCIF,
61 .irqs = { 52, 53, 55, 54 }, 69 .irqs = { 52, 53, 55, 54 },
62}; 70};
@@ -354,6 +362,10 @@ static struct intc_group groups[] __initdata = {
354 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), 362 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
355}; 363};
356 364
365#define INT2DISTCR0 0xfe4108a0
366#define INT2DISTCR1 0xfe4108a4
367#define INT2DISTCR2 0xfe4108a8
368
357static struct intc_mask_reg mask_registers[] __initdata = { 369static struct intc_mask_reg mask_registers[] __initdata = {
358 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ 370 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
359 { IRQ0, IRQ1, IRQ2, IRQ3 } }, 371 { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -363,20 +375,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
363 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, 375 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
364 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, 376 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
365 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ 377 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
366 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, 378 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
379 INTC_SMP_BALANCING(INT2DISTCR0) },
367 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ 380 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
368 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ 381 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
369 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, 382 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
370 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, 383 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
371 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, 384 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
372 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, 385 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
373 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, 386 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
387 INTC_SMP_BALANCING(INT2DISTCR1) },
374 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ 388 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
375 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 389 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
376 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, 390 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
377 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, 391 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
378 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, 392 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
379 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, 393 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
394 INTC_SMP_BALANCING(INT2DISTCR2) },
380}; 395};
381 396
382static struct intc_prio_reg prio_registers[] __initdata = { 397static struct intc_prio_reg prio_registers[] __initdata = {
@@ -433,11 +448,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
433 448
434void __init plat_irq_setup_pins(int mode) 449void __init plat_irq_setup_pins(int mode)
435{ 450{
451 int ret = 0;
452
436 switch (mode) { 453 switch (mode) {
437 case IRQ_MODE_IRQ: 454 case IRQ_MODE_IRQ:
455 ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
456 ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
457 ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
458 ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
459
460 if (unlikely(ret)) {
461 pr_err("Failed to set IRQ mode\n");
462 return;
463 }
464
438 register_intc_controller(&intc_desc_irq); 465 register_intc_controller(&intc_desc_irq);
439 break; 466 break;
440 case IRQ_MODE_IRL3210: 467 case IRQ_MODE_IRL3210:
468 ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
469 ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
470 ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
471 ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
472
473 if (unlikely(ret)) {
474 pr_err("Failed to set IRL mode\n");
475 return;
476 }
477
441 register_intc_controller(&intc_desc_irl); 478 register_intc_controller(&intc_desc_irl);
442 break; 479 break;
443 default: 480 default:
@@ -447,6 +484,9 @@ void __init plat_irq_setup_pins(int mode)
447 484
448void __init plat_irq_setup(void) 485void __init plat_irq_setup(void)
449{ 486{
487 reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
488 reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
489
450 register_intc_controller(&intc_desc); 490 register_intc_controller(&intc_desc);
451} 491}
452 492
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index d910666142b1..18419f1de963 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, 20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 39, 40, 42, 0 }, 25 .irqs = { 39, 40, 42, 0 },
24}; 26};
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 83972aa319c2..e4469e7233cb 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -75,13 +75,12 @@ void sh_mobile_setup_cpuidle(void)
75 i = CPUIDLE_DRIVER_STATE_START; 75 i = CPUIDLE_DRIVER_STATE_START;
76 76
77 state = &dev->states[i++]; 77 state = &dev->states[i++];
78 snprintf(state->name, CPUIDLE_NAME_LEN, "C0"); 78 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
79 strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN); 79 strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
80 state->exit_latency = 1; 80 state->exit_latency = 1;
81 state->target_residency = 1 * 2; 81 state->target_residency = 1 * 2;
82 state->power_usage = 3; 82 state->power_usage = 3;
83 state->flags = 0; 83 state->flags = 0;
84 state->flags |= CPUIDLE_FLAG_SHALLOW;
85 state->flags |= CPUIDLE_FLAG_TIME_VALID; 84 state->flags |= CPUIDLE_FLAG_TIME_VALID;
86 state->enter = cpuidle_sleep_enter; 85 state->enter = cpuidle_sleep_enter;
87 86
@@ -89,7 +88,7 @@ void sh_mobile_setup_cpuidle(void)
89 88
90 if (sh_mobile_sleep_supported & SUSP_SH_SF) { 89 if (sh_mobile_sleep_supported & SUSP_SH_SF) {
91 state = &dev->states[i++]; 90 state = &dev->states[i++];
92 snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); 91 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
93 strncpy(state->desc, "SuperH Sleep Mode [SF]", 92 strncpy(state->desc, "SuperH Sleep Mode [SF]",
94 CPUIDLE_DESC_LEN); 93 CPUIDLE_DESC_LEN);
95 state->exit_latency = 100; 94 state->exit_latency = 100;
@@ -102,7 +101,7 @@ void sh_mobile_setup_cpuidle(void)
102 101
103 if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) { 102 if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
104 state = &dev->states[i++]; 103 state = &dev->states[i++];
105 snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); 104 snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
106 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", 105 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
107 CPUIDLE_DESC_LEN); 106 CPUIDLE_DESC_LEN);
108 state->exit_latency = 2300; 107 state->exit_latency = 2300;
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index e55968712706..a6f95ae4aae7 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -141,7 +141,7 @@ static int sh_pm_enter(suspend_state_t state)
141 return 0; 141 return 0;
142} 142}
143 143
144static struct platform_suspend_ops sh_pm_ops = { 144static const struct platform_suspend_ops sh_pm_ops = {
145 .enter = sh_pm_enter, 145 .enter = sh_pm_enter,
146 .valid = suspend_valid_only_mem, 146 .valid = suspend_valid_only_mem,
147}; 147};
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
index 6dcb8166a64d..64c807c39208 100644
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -139,7 +139,7 @@ void platform_pm_runtime_suspend_idle(void)
139 queue_work(pm_wq, &hwblk_work); 139 queue_work(pm_wq, &hwblk_work);
140} 140}
141 141
142int platform_pm_runtime_suspend(struct device *dev) 142static int default_platform_runtime_suspend(struct device *dev)
143{ 143{
144 struct platform_device *pdev = to_platform_device(dev); 144 struct platform_device *pdev = to_platform_device(dev);
145 struct pdev_archdata *ad = &pdev->archdata; 145 struct pdev_archdata *ad = &pdev->archdata;
@@ -147,7 +147,7 @@ int platform_pm_runtime_suspend(struct device *dev)
147 int hwblk = ad->hwblk_id; 147 int hwblk = ad->hwblk_id;
148 int ret = 0; 148 int ret = 0;
149 149
150 dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk); 150 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
151 151
152 /* ignore off-chip platform devices */ 152 /* ignore off-chip platform devices */
153 if (!hwblk) 153 if (!hwblk)
@@ -157,7 +157,7 @@ int platform_pm_runtime_suspend(struct device *dev)
157 might_sleep(); 157 might_sleep();
158 158
159 /* catch misconfigured drivers not starting with resume */ 159 /* catch misconfigured drivers not starting with resume */
160 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) { 160 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
161 ret = -EINVAL; 161 ret = -EINVAL;
162 goto out; 162 goto out;
163 } 163 }
@@ -170,8 +170,8 @@ int platform_pm_runtime_suspend(struct device *dev)
170 170
171 /* put device on idle list */ 171 /* put device on idle list */
172 spin_lock_irqsave(&hwblk_lock, flags); 172 spin_lock_irqsave(&hwblk_lock, flags);
173 list_add_tail(&pdev->archdata.entry, &hwblk_idle_list); 173 list_add_tail(&ad->entry, &hwblk_idle_list);
174 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags); 174 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
175 spin_unlock_irqrestore(&hwblk_lock, flags); 175 spin_unlock_irqrestore(&hwblk_lock, flags);
176 176
177 /* increase idle count */ 177 /* increase idle count */
@@ -183,20 +183,20 @@ int platform_pm_runtime_suspend(struct device *dev)
183 mutex_unlock(&ad->mutex); 183 mutex_unlock(&ad->mutex);
184 184
185out: 185out:
186 dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n", 186 dev_dbg(dev, "%s() [%d] returns %d\n",
187 hwblk, ret); 187 __func__, hwblk, ret);
188 188
189 return ret; 189 return ret;
190} 190}
191 191
192int platform_pm_runtime_resume(struct device *dev) 192static int default_platform_runtime_resume(struct device *dev)
193{ 193{
194 struct platform_device *pdev = to_platform_device(dev); 194 struct platform_device *pdev = to_platform_device(dev);
195 struct pdev_archdata *ad = &pdev->archdata; 195 struct pdev_archdata *ad = &pdev->archdata;
196 int hwblk = ad->hwblk_id; 196 int hwblk = ad->hwblk_id;
197 int ret = 0; 197 int ret = 0;
198 198
199 dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk); 199 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
200 200
201 /* ignore off-chip platform devices */ 201 /* ignore off-chip platform devices */
202 if (!hwblk) 202 if (!hwblk)
@@ -228,19 +228,19 @@ int platform_pm_runtime_resume(struct device *dev)
228 */ 228 */
229 mutex_unlock(&ad->mutex); 229 mutex_unlock(&ad->mutex);
230out: 230out:
231 dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n", 231 dev_dbg(dev, "%s() [%d] returns %d\n",
232 hwblk, ret); 232 __func__, hwblk, ret);
233 233
234 return ret; 234 return ret;
235} 235}
236 236
237int platform_pm_runtime_idle(struct device *dev) 237static int default_platform_runtime_idle(struct device *dev)
238{ 238{
239 struct platform_device *pdev = to_platform_device(dev); 239 struct platform_device *pdev = to_platform_device(dev);
240 int hwblk = pdev->archdata.hwblk_id; 240 int hwblk = pdev->archdata.hwblk_id;
241 int ret = 0; 241 int ret = 0;
242 242
243 dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk); 243 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
244 244
245 /* ignore off-chip platform devices */ 245 /* ignore off-chip platform devices */
246 if (!hwblk) 246 if (!hwblk)
@@ -252,10 +252,19 @@ int platform_pm_runtime_idle(struct device *dev)
252 /* suspend synchronously to disable clocks immediately */ 252 /* suspend synchronously to disable clocks immediately */
253 ret = pm_runtime_suspend(dev); 253 ret = pm_runtime_suspend(dev);
254out: 254out:
255 dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk); 255 dev_dbg(dev, "%s() [%d] done!\n", __func__, hwblk);
256 return ret; 256 return ret;
257} 257}
258 258
259static struct dev_power_domain default_power_domain = {
260 .ops = {
261 .runtime_suspend = default_platform_runtime_suspend,
262 .runtime_resume = default_platform_runtime_resume,
263 .runtime_idle = default_platform_runtime_idle,
264 USE_PLATFORM_PM_SLEEP_OPS
265 },
266};
267
259static int platform_bus_notify(struct notifier_block *nb, 268static int platform_bus_notify(struct notifier_block *nb,
260 unsigned long action, void *data) 269 unsigned long action, void *data)
261{ 270{
@@ -276,6 +285,7 @@ static int platform_bus_notify(struct notifier_block *nb,
276 hwblk_disable(hwblk_info, hwblk); 285 hwblk_disable(hwblk_info, hwblk);
277 /* make sure driver re-inits itself once */ 286 /* make sure driver re-inits itself once */
278 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags); 287 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
288 dev->pwr_domain = &default_power_domain;
279 break; 289 break;
280 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */ 290 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
281 case BUS_NOTIFY_BOUND_DRIVER: 291 case BUS_NOTIFY_BOUND_DRIVER:
@@ -289,6 +299,7 @@ static int platform_bus_notify(struct notifier_block *nb,
289 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags); 299 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
290 break; 300 break;
291 case BUS_NOTIFY_DEL_DEVICE: 301 case BUS_NOTIFY_DEL_DEVICE:
302 dev->pwr_domain = NULL;
292 break; 303 break;
293 } 304 }
294 return 0; 305 return 0;
diff --git a/arch/sh/kernel/crash_dump.c b/arch/sh/kernel/crash_dump.c
index 37c97d444576..569e7b171c01 100644
--- a/arch/sh/kernel/crash_dump.c
+++ b/arch/sh/kernel/crash_dump.c
@@ -9,28 +9,6 @@
9#include <linux/io.h> 9#include <linux/io.h>
10#include <asm/uaccess.h> 10#include <asm/uaccess.h>
11 11
12/* Stores the physical address of elf header of crash image. */
13unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
14
15/*
16 * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
17 * is_kdump_kernel() to determine if we are booting after a panic. Hence
18 * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
19 *
20 * elfcorehdr= specifies the location of elf core header
21 * stored by the crashed kernel.
22 */
23static int __init parse_elfcorehdr(char *arg)
24{
25 if (!arg)
26 return -EINVAL;
27
28 elfcorehdr_addr = memparse(arg, &arg);
29
30 return 0;
31}
32early_param("elfcorehdr", parse_elfcorehdr);
33
34/** 12/**
35 * copy_oldmem_page - copy one page from "oldmem" 13 * copy_oldmem_page - copy one page from "oldmem"
36 * @pfn: page frame number to be copied 14 * @pfn: page frame number to be copied
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 6f5ad1513409..694158b9a50f 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -69,19 +69,6 @@ stack_reader_dump(struct task_struct *task, struct pt_regs *regs,
69 } 69 }
70} 70}
71 71
72static void
73print_trace_warning_symbol(void *data, char *msg, unsigned long symbol)
74{
75 printk(data);
76 print_symbol(msg, symbol);
77 printk("\n");
78}
79
80static void print_trace_warning(void *data, char *msg)
81{
82 printk("%s%s\n", (char *)data, msg);
83}
84
85static int print_trace_stack(void *data, char *name) 72static int print_trace_stack(void *data, char *name)
86{ 73{
87 printk("%s <%s> ", (char *)data, name); 74 printk("%s <%s> ", (char *)data, name);
@@ -98,8 +85,6 @@ static void print_trace_address(void *data, unsigned long addr, int reliable)
98} 85}
99 86
100static const struct stacktrace_ops print_trace_ops = { 87static const struct stacktrace_ops print_trace_ops = {
101 .warning = print_trace_warning,
102 .warning_symbol = print_trace_warning_symbol,
103 .stack = print_trace_stack, 88 .stack = print_trace_stack,
104 .address = print_trace_address, 89 .address = print_trace_address,
105}; 90};
diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S
index 6e35f012cc03..7db248936b60 100644
--- a/arch/sh/kernel/head_32.S
+++ b/arch/sh/kernel/head_32.S
@@ -330,7 +330,7 @@ ENTRY(_stext)
330#if defined(CONFIG_CPU_SH2) 330#if defined(CONFIG_CPU_SH2)
3311: .long 0x000000F0 ! IMASK=0xF 3311: .long 0x000000F0 ! IMASK=0xF
332#else 332#else
3331: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF 3331: .long 0x500080F0 ! MD=1, RB=0, BL=1, FD=1, IMASK=0xF
334#endif 334#endif
335ENTRY(stack_start) 335ENTRY(stack_start)
3362: .long init_thread_union+THREAD_SIZE 3362: .long init_thread_union+THREAD_SIZE
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
deleted file mode 100644
index 447d78f666f9..000000000000
--- a/arch/sh/kernel/io_generic.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * arch/sh/kernel/io_generic.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * Generic I/O routine. These can be used where a machine specific version
8 * is not required.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/module.h>
15#include <linux/io.h>
16#include <asm/machvec.h>
17
18#ifdef CONFIG_CPU_SH3
19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
20 * workaround. */
21/* I'm not sure SH7709 has this kind of bug */
22#define dummy_read() __raw_readb(0xba000000)
23#else
24#define dummy_read()
25#endif
26
27unsigned long generic_io_base = 0;
28
29u8 generic_inb(unsigned long port)
30{
31 return __raw_readb(__ioport_map(port, 1));
32}
33
34u16 generic_inw(unsigned long port)
35{
36 return __raw_readw(__ioport_map(port, 2));
37}
38
39u32 generic_inl(unsigned long port)
40{
41 return __raw_readl(__ioport_map(port, 4));
42}
43
44u8 generic_inb_p(unsigned long port)
45{
46 unsigned long v = generic_inb(port);
47
48 ctrl_delay();
49 return v;
50}
51
52u16 generic_inw_p(unsigned long port)
53{
54 unsigned long v = generic_inw(port);
55
56 ctrl_delay();
57 return v;
58}
59
60u32 generic_inl_p(unsigned long port)
61{
62 unsigned long v = generic_inl(port);
63
64 ctrl_delay();
65 return v;
66}
67
68/*
69 * insb/w/l all read a series of bytes/words/longs from a fixed port
70 * address. However as the port address doesn't change we only need to
71 * convert the port address to real address once.
72 */
73
74void generic_insb(unsigned long port, void *dst, unsigned long count)
75{
76 __raw_readsb(__ioport_map(port, 1), dst, count);
77 dummy_read();
78}
79
80void generic_insw(unsigned long port, void *dst, unsigned long count)
81{
82 __raw_readsw(__ioport_map(port, 2), dst, count);
83 dummy_read();
84}
85
86void generic_insl(unsigned long port, void *dst, unsigned long count)
87{
88 __raw_readsl(__ioport_map(port, 4), dst, count);
89 dummy_read();
90}
91
92void generic_outb(u8 b, unsigned long port)
93{
94 __raw_writeb(b, __ioport_map(port, 1));
95}
96
97void generic_outw(u16 b, unsigned long port)
98{
99 __raw_writew(b, __ioport_map(port, 2));
100}
101
102void generic_outl(u32 b, unsigned long port)
103{
104 __raw_writel(b, __ioport_map(port, 4));
105}
106
107void generic_outb_p(u8 b, unsigned long port)
108{
109 generic_outb(b, port);
110 ctrl_delay();
111}
112
113void generic_outw_p(u16 b, unsigned long port)
114{
115 generic_outw(b, port);
116 ctrl_delay();
117}
118
119void generic_outl_p(u32 b, unsigned long port)
120{
121 generic_outl(b, port);
122 ctrl_delay();
123}
124
125/*
126 * outsb/w/l all write a series of bytes/words/longs to a fixed port
127 * address. However as the port address doesn't change we only need to
128 * convert the port address to real address once.
129 */
130void generic_outsb(unsigned long port, const void *src, unsigned long count)
131{
132 __raw_writesb(__ioport_map(port, 1), src, count);
133 dummy_read();
134}
135
136void generic_outsw(unsigned long port, const void *src, unsigned long count)
137{
138 __raw_writesw(__ioport_map(port, 2), src, count);
139 dummy_read();
140}
141
142void generic_outsl(unsigned long port, const void *src, unsigned long count)
143{
144 __raw_writesl(__ioport_map(port, 4), src, count);
145 dummy_read();
146}
147
148void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
149{
150#ifdef P1SEG
151 if (PXSEG(addr) >= P1SEG)
152 return (void __iomem *)addr;
153#endif
154
155 return (void __iomem *)(addr + generic_io_base);
156}
157
158void generic_ioport_unmap(void __iomem *addr)
159{
160}
161
162#ifndef CONFIG_GENERIC_IOMAP
163void __iomem *ioport_map(unsigned long port, unsigned int nr)
164{
165 void __iomem *ret;
166
167 ret = __ioport_map_trapped(port, nr);
168 if (ret)
169 return ret;
170
171 return __ioport_map(port, nr);
172}
173EXPORT_SYMBOL(ioport_map);
174
175void ioport_unmap(void __iomem *addr)
176{
177 sh_mv.mv_ioport_unmap(addr);
178}
179EXPORT_SYMBOL(ioport_unmap);
180#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 2947d2bd1291..32c385ef1011 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -291,7 +291,7 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address)
291 } 291 }
292 292
293 tmp = handle_unaligned_access(instruction, regs, 293 tmp = handle_unaligned_access(instruction, regs,
294 &trapped_io_access, 1); 294 &trapped_io_access, 1, address);
295 set_fs(oldfs); 295 set_fs(oldfs);
296 return tmp == 0; 296 return tmp == 0;
297} 297}
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
new file mode 100644
index 000000000000..2e8e8b9b9cef
--- /dev/null
+++ b/arch/sh/kernel/iomap.c
@@ -0,0 +1,165 @@
1/*
2 * arch/sh/kernel/iomap.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13
14unsigned int ioread8(void __iomem *addr)
15{
16 return readb(addr);
17}
18EXPORT_SYMBOL(ioread8);
19
20unsigned int ioread16(void __iomem *addr)
21{
22 return readw(addr);
23}
24EXPORT_SYMBOL(ioread16);
25
26unsigned int ioread16be(void __iomem *addr)
27{
28 return be16_to_cpu(__raw_readw(addr));
29}
30EXPORT_SYMBOL(ioread16be);
31
32unsigned int ioread32(void __iomem *addr)
33{
34 return readl(addr);
35}
36EXPORT_SYMBOL(ioread32);
37
38unsigned int ioread32be(void __iomem *addr)
39{
40 return be32_to_cpu(__raw_readl(addr));
41}
42EXPORT_SYMBOL(ioread32be);
43
44void iowrite8(u8 val, void __iomem *addr)
45{
46 writeb(val, addr);
47}
48EXPORT_SYMBOL(iowrite8);
49
50void iowrite16(u16 val, void __iomem *addr)
51{
52 writew(val, addr);
53}
54EXPORT_SYMBOL(iowrite16);
55
56void iowrite16be(u16 val, void __iomem *addr)
57{
58 __raw_writew(cpu_to_be16(val), addr);
59}
60EXPORT_SYMBOL(iowrite16be);
61
62void iowrite32(u32 val, void __iomem *addr)
63{
64 writel(val, addr);
65}
66EXPORT_SYMBOL(iowrite32);
67
68void iowrite32be(u32 val, void __iomem *addr)
69{
70 __raw_writel(cpu_to_be32(val), addr);
71}
72EXPORT_SYMBOL(iowrite32be);
73
74/*
75 * These are the "repeat MMIO read/write" functions.
76 * Note the "__raw" accesses, since we don't want to
77 * convert to CPU byte order. We write in "IO byte
78 * order" (we also don't have IO barriers).
79 */
80static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
81{
82 while (--count >= 0) {
83 u8 data = __raw_readb(addr);
84 *dst = data;
85 dst++;
86 }
87}
88
89static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
90{
91 while (--count >= 0) {
92 u16 data = __raw_readw(addr);
93 *dst = data;
94 dst++;
95 }
96}
97
98static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
99{
100 while (--count >= 0) {
101 u32 data = __raw_readl(addr);
102 *dst = data;
103 dst++;
104 }
105}
106
107static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
108{
109 while (--count >= 0) {
110 __raw_writeb(*src, addr);
111 src++;
112 }
113}
114
115static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
116{
117 while (--count >= 0) {
118 __raw_writew(*src, addr);
119 src++;
120 }
121}
122
123static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
124{
125 while (--count >= 0) {
126 __raw_writel(*src, addr);
127 src++;
128 }
129}
130
131void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
132{
133 mmio_insb(addr, dst, count);
134}
135EXPORT_SYMBOL(ioread8_rep);
136
137void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
138{
139 mmio_insw(addr, dst, count);
140}
141EXPORT_SYMBOL(ioread16_rep);
142
143void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
144{
145 mmio_insl(addr, dst, count);
146}
147EXPORT_SYMBOL(ioread32_rep);
148
149void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
150{
151 mmio_outsb(addr, src, count);
152}
153EXPORT_SYMBOL(iowrite8_rep);
154
155void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
156{
157 mmio_outsw(addr, src, count);
158}
159EXPORT_SYMBOL(iowrite16_rep);
160
161void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
162{
163 mmio_outsl(addr, src, count);
164}
165EXPORT_SYMBOL(iowrite32_rep);
diff --git a/arch/sh/kernel/ioport.c b/arch/sh/kernel/ioport.c
new file mode 100644
index 000000000000..e3ad6103e7c1
--- /dev/null
+++ b/arch/sh/kernel/ioport.c
@@ -0,0 +1,43 @@
1/*
2 * arch/sh/kernel/ioport.c
3 *
4 * Copyright (C) 2000 Niibe Yutaka
5 * Copyright (C) 2005 - 2007 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13
14const unsigned long sh_io_port_base __read_mostly = -1;
15EXPORT_SYMBOL(sh_io_port_base);
16
17void __iomem *__ioport_map(unsigned long addr, unsigned int size)
18{
19 if (sh_mv.mv_ioport_map)
20 return sh_mv.mv_ioport_map(addr, size);
21
22 return (void __iomem *)(addr + sh_io_port_base);
23}
24EXPORT_SYMBOL(__ioport_map);
25
26void __iomem *ioport_map(unsigned long port, unsigned int nr)
27{
28 void __iomem *ret;
29
30 ret = __ioport_map_trapped(port, nr);
31 if (ret)
32 return ret;
33
34 return __ioport_map(port, nr);
35}
36EXPORT_SYMBOL(ioport_map);
37
38void ioport_unmap(void __iomem *addr)
39{
40 if (sh_mv.mv_ioport_unmap)
41 sh_mv.mv_ioport_unmap(addr);
42}
43EXPORT_SYMBOL(ioport_unmap);
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 257de1f0692b..a3ee91971129 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -13,6 +13,7 @@
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <linux/ftrace.h> 14#include <linux/ftrace.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/ratelimit.h>
16#include <asm/processor.h> 17#include <asm/processor.h>
17#include <asm/machvec.h> 18#include <asm/machvec.h>
18#include <asm/uaccess.h> 19#include <asm/uaccess.h>
@@ -34,9 +35,9 @@ void ack_bad_irq(unsigned int irq)
34 35
35#if defined(CONFIG_PROC_FS) 36#if defined(CONFIG_PROC_FS)
36/* 37/*
37 * /proc/interrupts printing: 38 * /proc/interrupts printing for arch specific interrupts
38 */ 39 */
39static int show_other_interrupts(struct seq_file *p, int prec) 40int arch_show_interrupts(struct seq_file *p, int prec)
40{ 41{
41 int j; 42 int j;
42 43
@@ -49,58 +50,6 @@ static int show_other_interrupts(struct seq_file *p, int prec)
49 50
50 return 0; 51 return 0;
51} 52}
52
53int show_interrupts(struct seq_file *p, void *v)
54{
55 unsigned long flags, any_count = 0;
56 int i = *(loff_t *)v, j, prec;
57 struct irqaction *action;
58 struct irq_desc *desc;
59
60 if (i > nr_irqs)
61 return 0;
62
63 for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
64 j *= 10;
65
66 if (i == nr_irqs)
67 return show_other_interrupts(p, prec);
68
69 if (i == 0) {
70 seq_printf(p, "%*s", prec + 8, "");
71 for_each_online_cpu(j)
72 seq_printf(p, "CPU%-8d", j);
73 seq_putc(p, '\n');
74 }
75
76 desc = irq_to_desc(i);
77 if (!desc)
78 return 0;
79
80 raw_spin_lock_irqsave(&desc->lock, flags);
81 for_each_online_cpu(j)
82 any_count |= kstat_irqs_cpu(i, j);
83 action = desc->action;
84 if (!action && !any_count)
85 goto out;
86
87 seq_printf(p, "%*d: ", prec, i);
88 for_each_online_cpu(j)
89 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
90 seq_printf(p, " %14s", desc->chip->name);
91 seq_printf(p, "-%-8s", desc->name);
92
93 if (action) {
94 seq_printf(p, " %s", action->name);
95 while ((action = action->next) != NULL)
96 seq_printf(p, ", %s", action->name);
97 }
98
99 seq_putc(p, '\n');
100out:
101 raw_spin_unlock_irqrestore(&desc->lock, flags);
102 return 0;
103}
104#endif 53#endif
105 54
106#ifdef CONFIG_IRQSTACKS 55#ifdef CONFIG_IRQSTACKS
@@ -235,7 +184,7 @@ asmlinkage void do_softirq(void)
235 ); 184 );
236 185
237 /* 186 /*
238 * Shouldnt happen, we returned above if in_interrupt(): 187 * Shouldn't happen, we returned above if in_interrupt():
239 */ 188 */
240 WARN_ON_ONCE(softirq_count()); 189 WARN_ON_ONCE(softirq_count());
241 } 190 }
@@ -273,16 +222,12 @@ void __init init_IRQ(void)
273{ 222{
274 plat_irq_setup(); 223 plat_irq_setup();
275 224
276 /*
277 * Pin any of the legacy IRQ vectors that haven't already been
278 * grabbed by the platform
279 */
280 reserve_irq_legacy();
281
282 /* Perform the machine specific initialisation */ 225 /* Perform the machine specific initialisation */
283 if (sh_mv.mv_init_irq) 226 if (sh_mv.mv_init_irq)
284 sh_mv.mv_init_irq(); 227 sh_mv.mv_init_irq();
285 228
229 intc_finalize();
230
286 irq_ctx_init(smp_processor_id()); 231 irq_ctx_init(smp_processor_id());
287} 232}
288 233
@@ -290,18 +235,21 @@ void __init init_IRQ(void)
290int __init arch_probe_nr_irqs(void) 235int __init arch_probe_nr_irqs(void)
291{ 236{
292 nr_irqs = sh_mv.mv_nr_irqs; 237 nr_irqs = sh_mv.mv_nr_irqs;
293 return 0; 238 return NR_IRQS_LEGACY;
294} 239}
295#endif 240#endif
296 241
297#ifdef CONFIG_HOTPLUG_CPU 242#ifdef CONFIG_HOTPLUG_CPU
298static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) 243static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
299{ 244{
245 struct irq_desc *desc = irq_to_desc(irq);
246 struct irq_chip *chip = irq_data_get_irq_chip(data);
247
300 printk(KERN_INFO "IRQ%u: moving from cpu%u to cpu%u\n", 248 printk(KERN_INFO "IRQ%u: moving from cpu%u to cpu%u\n",
301 irq, desc->node, cpu); 249 irq, data->node, cpu);
302 250
303 raw_spin_lock_irq(&desc->lock); 251 raw_spin_lock_irq(&desc->lock);
304 desc->chip->set_affinity(irq, cpumask_of(cpu)); 252 chip->irq_set_affinity(data, cpumask_of(cpu), false);
305 raw_spin_unlock_irq(&desc->lock); 253 raw_spin_unlock_irq(&desc->lock);
306} 254}
307 255
@@ -312,24 +260,24 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
312 */ 260 */
313void migrate_irqs(void) 261void migrate_irqs(void)
314{ 262{
315 struct irq_desc *desc;
316 unsigned int irq, cpu = smp_processor_id(); 263 unsigned int irq, cpu = smp_processor_id();
317 264
318 for_each_irq_desc(irq, desc) { 265 for_each_active_irq(irq) {
319 if (desc->node == cpu) { 266 struct irq_data *data = irq_get_irq_data(irq);
320 unsigned int newcpu = cpumask_any_and(desc->affinity, 267
268 if (data->node == cpu) {
269 unsigned int newcpu = cpumask_any_and(data->affinity,
321 cpu_online_mask); 270 cpu_online_mask);
322 if (newcpu >= nr_cpu_ids) { 271 if (newcpu >= nr_cpu_ids) {
323 if (printk_ratelimit()) 272 pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
324 printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n", 273 irq, cpu);
325 irq, cpu);
326 274
327 cpumask_setall(desc->affinity); 275 cpumask_setall(data->affinity);
328 newcpu = cpumask_any_and(desc->affinity, 276 newcpu = cpumask_any_and(data->affinity,
329 cpu_online_mask); 277 cpu_online_mask);
330 } 278 }
331 279
332 route_irq(desc, irq, newcpu); 280 route_irq(data, irq, newcpu);
333 } 281 }
334 } 282 }
335} 283}
diff --git a/arch/sh/kernel/irq_32.c b/arch/sh/kernel/irq_32.c
index e33ab15831f9..e5a755be9129 100644
--- a/arch/sh/kernel/irq_32.c
+++ b/arch/sh/kernel/irq_32.c
@@ -10,11 +10,11 @@
10#include <linux/irqflags.h> 10#include <linux/irqflags.h>
11#include <linux/module.h> 11#include <linux/module.h>
12 12
13void notrace raw_local_irq_restore(unsigned long flags) 13void notrace arch_local_irq_restore(unsigned long flags)
14{ 14{
15 unsigned long __dummy0, __dummy1; 15 unsigned long __dummy0, __dummy1;
16 16
17 if (flags == RAW_IRQ_DISABLED) { 17 if (flags == ARCH_IRQ_DISABLED) {
18 __asm__ __volatile__ ( 18 __asm__ __volatile__ (
19 "stc sr, %0\n\t" 19 "stc sr, %0\n\t"
20 "or #0xf0, %0\n\t" 20 "or #0xf0, %0\n\t"
@@ -33,14 +33,14 @@ void notrace raw_local_irq_restore(unsigned long flags)
33#endif 33#endif
34 "ldc %0, sr\n\t" 34 "ldc %0, sr\n\t"
35 : "=&r" (__dummy0), "=r" (__dummy1) 35 : "=&r" (__dummy0), "=r" (__dummy1)
36 : "1" (~RAW_IRQ_DISABLED) 36 : "1" (~ARCH_IRQ_DISABLED)
37 : "memory" 37 : "memory"
38 ); 38 );
39 } 39 }
40} 40}
41EXPORT_SYMBOL(raw_local_irq_restore); 41EXPORT_SYMBOL(arch_local_irq_restore);
42 42
43unsigned long notrace __raw_local_save_flags(void) 43unsigned long notrace arch_local_save_flags(void)
44{ 44{
45 unsigned long flags; 45 unsigned long flags;
46 46
@@ -54,4 +54,4 @@ unsigned long notrace __raw_local_save_flags(void)
54 54
55 return flags; 55 return flags;
56} 56}
57EXPORT_SYMBOL(__raw_local_save_flags); 57EXPORT_SYMBOL(arch_local_save_flags);
diff --git a/arch/sh/kernel/irq_64.c b/arch/sh/kernel/irq_64.c
index 32365ba0e039..8fc05b997b6d 100644
--- a/arch/sh/kernel/irq_64.c
+++ b/arch/sh/kernel/irq_64.c
@@ -11,17 +11,17 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <cpu/registers.h> 12#include <cpu/registers.h>
13 13
14void notrace raw_local_irq_restore(unsigned long flags) 14void notrace arch_local_irq_restore(unsigned long flags)
15{ 15{
16 unsigned long long __dummy; 16 unsigned long long __dummy;
17 17
18 if (flags == RAW_IRQ_DISABLED) { 18 if (flags == ARCH_IRQ_DISABLED) {
19 __asm__ __volatile__ ( 19 __asm__ __volatile__ (
20 "getcon " __SR ", %0\n\t" 20 "getcon " __SR ", %0\n\t"
21 "or %0, %1, %0\n\t" 21 "or %0, %1, %0\n\t"
22 "putcon %0, " __SR "\n\t" 22 "putcon %0, " __SR "\n\t"
23 : "=&r" (__dummy) 23 : "=&r" (__dummy)
24 : "r" (RAW_IRQ_DISABLED) 24 : "r" (ARCH_IRQ_DISABLED)
25 ); 25 );
26 } else { 26 } else {
27 __asm__ __volatile__ ( 27 __asm__ __volatile__ (
@@ -29,13 +29,13 @@ void notrace raw_local_irq_restore(unsigned long flags)
29 "and %0, %1, %0\n\t" 29 "and %0, %1, %0\n\t"
30 "putcon %0, " __SR "\n\t" 30 "putcon %0, " __SR "\n\t"
31 : "=&r" (__dummy) 31 : "=&r" (__dummy)
32 : "r" (~RAW_IRQ_DISABLED) 32 : "r" (~ARCH_IRQ_DISABLED)
33 ); 33 );
34 } 34 }
35} 35}
36EXPORT_SYMBOL(raw_local_irq_restore); 36EXPORT_SYMBOL(arch_local_irq_restore);
37 37
38unsigned long notrace __raw_local_save_flags(void) 38unsigned long notrace arch_local_save_flags(void)
39{ 39{
40 unsigned long flags; 40 unsigned long flags;
41 41
@@ -43,9 +43,9 @@ unsigned long notrace __raw_local_save_flags(void)
43 "getcon " __SR ", %0\n\t" 43 "getcon " __SR ", %0\n\t"
44 "and %0, %1, %0" 44 "and %0, %1, %0"
45 : "=&r" (flags) 45 : "=&r" (flags)
46 : "r" (RAW_IRQ_DISABLED) 46 : "r" (ARCH_IRQ_DISABLED)
47 ); 47 );
48 48
49 return flags; 49 return flags;
50} 50}
51EXPORT_SYMBOL(__raw_local_save_flags); 51EXPORT_SYMBOL(arch_local_save_flags);
diff --git a/arch/sh/kernel/kdebugfs.c b/arch/sh/kernel/kdebugfs.c
new file mode 100644
index 000000000000..e11c30bb100c
--- /dev/null
+++ b/arch/sh/kernel/kdebugfs.c
@@ -0,0 +1,16 @@
1#include <linux/module.h>
2#include <linux/init.h>
3#include <linux/debugfs.h>
4
5struct dentry *arch_debugfs_dir;
6EXPORT_SYMBOL(arch_debugfs_dir);
7
8static int __init arch_kdebugfs_init(void)
9{
10 arch_debugfs_dir = debugfs_create_dir("sh", NULL);
11 if (!arch_debugfs_dir)
12 return -ENOMEM;
13
14 return 0;
15}
16arch_initcall(arch_kdebugfs_init);
diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c
index 4049d99f76e1..1208b09e95c3 100644
--- a/arch/sh/kernel/kprobes.c
+++ b/arch/sh/kernel/kprobes.c
@@ -20,9 +20,9 @@
20DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; 20DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
21DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); 21DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
22 22
23static struct kprobe saved_current_opcode; 23static DEFINE_PER_CPU(struct kprobe, saved_current_opcode);
24static struct kprobe saved_next_opcode; 24static DEFINE_PER_CPU(struct kprobe, saved_next_opcode);
25static struct kprobe saved_next_opcode2; 25static DEFINE_PER_CPU(struct kprobe, saved_next_opcode2);
26 26
27#define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b) 27#define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b)
28#define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b) 28#define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b)
@@ -102,16 +102,21 @@ int __kprobes kprobe_handle_illslot(unsigned long pc)
102 102
103void __kprobes arch_remove_kprobe(struct kprobe *p) 103void __kprobes arch_remove_kprobe(struct kprobe *p)
104{ 104{
105 if (saved_next_opcode.addr != 0x0) { 105 struct kprobe *saved = &__get_cpu_var(saved_next_opcode);
106
107 if (saved->addr) {
106 arch_disarm_kprobe(p); 108 arch_disarm_kprobe(p);
107 arch_disarm_kprobe(&saved_next_opcode); 109 arch_disarm_kprobe(saved);
108 saved_next_opcode.addr = 0x0; 110
109 saved_next_opcode.opcode = 0x0; 111 saved->addr = NULL;
110 112 saved->opcode = 0;
111 if (saved_next_opcode2.addr != 0x0) { 113
112 arch_disarm_kprobe(&saved_next_opcode2); 114 saved = &__get_cpu_var(saved_next_opcode2);
113 saved_next_opcode2.addr = 0x0; 115 if (saved->addr) {
114 saved_next_opcode2.opcode = 0x0; 116 arch_disarm_kprobe(saved);
117
118 saved->addr = NULL;
119 saved->opcode = 0;
115 } 120 }
116 } 121 }
117} 122}
@@ -141,57 +146,59 @@ static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
141 */ 146 */
142static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) 147static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
143{ 148{
144 kprobe_opcode_t *addr = NULL; 149 __get_cpu_var(saved_current_opcode).addr = (kprobe_opcode_t *)regs->pc;
145 saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc);
146 addr = saved_current_opcode.addr;
147 150
148 if (p != NULL) { 151 if (p != NULL) {
152 struct kprobe *op1, *op2;
153
149 arch_disarm_kprobe(p); 154 arch_disarm_kprobe(p);
150 155
156 op1 = &__get_cpu_var(saved_next_opcode);
157 op2 = &__get_cpu_var(saved_next_opcode2);
158
151 if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) { 159 if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) {
152 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); 160 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
153 saved_next_opcode.addr = 161 op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr];
154 (kprobe_opcode_t *) regs->regs[reg_nr];
155 } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) { 162 } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) {
156 unsigned long disp = (p->opcode & 0x0FFF); 163 unsigned long disp = (p->opcode & 0x0FFF);
157 saved_next_opcode.addr = 164 op1->addr =
158 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); 165 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
159 166
160 } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) { 167 } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) {
161 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); 168 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
162 saved_next_opcode.addr = 169 op1->addr =
163 (kprobe_opcode_t *) (regs->pc + 4 + 170 (kprobe_opcode_t *) (regs->pc + 4 +
164 regs->regs[reg_nr]); 171 regs->regs[reg_nr]);
165 172
166 } else if (OPCODE_RTS(p->opcode)) { 173 } else if (OPCODE_RTS(p->opcode)) {
167 saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr; 174 op1->addr = (kprobe_opcode_t *) regs->pr;
168 175
169 } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) { 176 } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) {
170 unsigned long disp = (p->opcode & 0x00FF); 177 unsigned long disp = (p->opcode & 0x00FF);
171 /* case 1 */ 178 /* case 1 */
172 saved_next_opcode.addr = p->addr + 1; 179 op1->addr = p->addr + 1;
173 /* case 2 */ 180 /* case 2 */
174 saved_next_opcode2.addr = 181 op2->addr =
175 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); 182 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
176 saved_next_opcode2.opcode = *(saved_next_opcode2.addr); 183 op2->opcode = *(op2->addr);
177 arch_arm_kprobe(&saved_next_opcode2); 184 arch_arm_kprobe(op2);
178 185
179 } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) { 186 } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) {
180 unsigned long disp = (p->opcode & 0x00FF); 187 unsigned long disp = (p->opcode & 0x00FF);
181 /* case 1 */ 188 /* case 1 */
182 saved_next_opcode.addr = p->addr + 2; 189 op1->addr = p->addr + 2;
183 /* case 2 */ 190 /* case 2 */
184 saved_next_opcode2.addr = 191 op2->addr =
185 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); 192 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
186 saved_next_opcode2.opcode = *(saved_next_opcode2.addr); 193 op2->opcode = *(op2->addr);
187 arch_arm_kprobe(&saved_next_opcode2); 194 arch_arm_kprobe(op2);
188 195
189 } else { 196 } else {
190 saved_next_opcode.addr = p->addr + 1; 197 op1->addr = p->addr + 1;
191 } 198 }
192 199
193 saved_next_opcode.opcode = *(saved_next_opcode.addr); 200 op1->opcode = *(op1->addr);
194 arch_arm_kprobe(&saved_next_opcode); 201 arch_arm_kprobe(op1);
195 } 202 }
196} 203}
197 204
@@ -376,21 +383,23 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs)
376 cur->post_handler(cur, regs, 0); 383 cur->post_handler(cur, regs, 0);
377 } 384 }
378 385
379 if (saved_next_opcode.addr != 0x0) { 386 p = &__get_cpu_var(saved_next_opcode);
380 arch_disarm_kprobe(&saved_next_opcode); 387 if (p->addr) {
381 saved_next_opcode.addr = 0x0; 388 arch_disarm_kprobe(p);
382 saved_next_opcode.opcode = 0x0; 389 p->addr = NULL;
390 p->opcode = 0;
383 391
384 addr = saved_current_opcode.addr; 392 addr = __get_cpu_var(saved_current_opcode).addr;
385 saved_current_opcode.addr = 0x0; 393 __get_cpu_var(saved_current_opcode).addr = NULL;
386 394
387 p = get_kprobe(addr); 395 p = get_kprobe(addr);
388 arch_arm_kprobe(p); 396 arch_arm_kprobe(p);
389 397
390 if (saved_next_opcode2.addr != 0x0) { 398 p = &__get_cpu_var(saved_next_opcode2);
391 arch_disarm_kprobe(&saved_next_opcode2); 399 if (p->addr) {
392 saved_next_opcode2.addr = 0x0; 400 arch_disarm_kprobe(p);
393 saved_next_opcode2.opcode = 0x0; 401 p->addr = NULL;
402 p->opcode = 0;
394 } 403 }
395 } 404 }
396 405
@@ -572,14 +581,5 @@ static struct kprobe trampoline_p = {
572 581
573int __init arch_init_kprobes(void) 582int __init arch_init_kprobes(void)
574{ 583{
575 saved_next_opcode.addr = 0x0;
576 saved_next_opcode.opcode = 0x0;
577
578 saved_current_opcode.addr = 0x0;
579 saved_current_opcode.opcode = 0x0;
580
581 saved_next_opcode2.addr = 0x0;
582 saved_next_opcode2.opcode = 0x0;
583
584 return register_kprobe(&trampoline_p); 584 return register_kprobe(&trampoline_p);
585} 585}
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 9f9bb63616ad..3d722e49db08 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -118,28 +118,6 @@ void __init sh_mv_setup(void)
118 sh_mv.mv_##elem = generic_##elem; \ 118 sh_mv.mv_##elem = generic_##elem; \
119} while (0) 119} while (0)
120 120
121#ifdef CONFIG_HAS_IOPORT
122
123#ifdef P2SEG
124 __set_io_port_base(P2SEG);
125#else
126 __set_io_port_base(0);
127#endif
128
129 mv_set(inb); mv_set(inw); mv_set(inl);
130 mv_set(outb); mv_set(outw); mv_set(outl);
131
132 mv_set(inb_p); mv_set(inw_p); mv_set(inl_p);
133 mv_set(outb_p); mv_set(outw_p); mv_set(outl_p);
134
135 mv_set(insb); mv_set(insw); mv_set(insl);
136 mv_set(outsb); mv_set(outsw); mv_set(outsl);
137
138 mv_set(ioport_map);
139 mv_set(ioport_unmap);
140
141#endif
142
143 mv_set(irq_demux); 121 mv_set(irq_demux);
144 mv_set(mode_pins); 122 mv_set(mode_pins);
145 mv_set(mem_init); 123 mv_set(mem_init);
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index ae0be697a89e..19b1f8826aef 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -93,6 +93,8 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
93#endif 93#endif
94 94
95 switch (ELF32_R_TYPE(rel[i].r_info)) { 95 switch (ELF32_R_TYPE(rel[i].r_info)) {
96 case R_SH_NONE:
97 break;
96 case R_SH_DIR32: 98 case R_SH_DIR32:
97 value = get_unaligned(location); 99 value = get_unaligned(location);
98 value += relocation; 100 value += relocation;
diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c
index a9dd3abde28e..cc80b614b5fa 100644
--- a/arch/sh/kernel/perf_callchain.c
+++ b/arch/sh/kernel/perf_callchain.c
@@ -14,21 +14,6 @@
14#include <asm/unwinder.h> 14#include <asm/unwinder.h>
15#include <asm/ptrace.h> 15#include <asm/ptrace.h>
16 16
17static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
18{
19 if (entry->nr < PERF_MAX_STACK_DEPTH)
20 entry->ip[entry->nr++] = ip;
21}
22
23static void callchain_warning(void *data, char *msg)
24{
25}
26
27static void
28callchain_warning_symbol(void *data, char *msg, unsigned long symbol)
29{
30}
31
32static int callchain_stack(void *data, char *name) 17static int callchain_stack(void *data, char *name)
33{ 18{
34 return 0; 19 return 0;
@@ -39,57 +24,18 @@ static void callchain_address(void *data, unsigned long addr, int reliable)
39 struct perf_callchain_entry *entry = data; 24 struct perf_callchain_entry *entry = data;
40 25
41 if (reliable) 26 if (reliable)
42 callchain_store(entry, addr); 27 perf_callchain_store(entry, addr);
43} 28}
44 29
45static const struct stacktrace_ops callchain_ops = { 30static const struct stacktrace_ops callchain_ops = {
46 .warning = callchain_warning,
47 .warning_symbol = callchain_warning_symbol,
48 .stack = callchain_stack, 31 .stack = callchain_stack,
49 .address = callchain_address, 32 .address = callchain_address,
50}; 33};
51 34
52static void 35void
53perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) 36perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
54{ 37{
55 callchain_store(entry, PERF_CONTEXT_KERNEL); 38 perf_callchain_store(entry, regs->pc);
56 callchain_store(entry, regs->pc);
57 39
58 unwind_stack(NULL, regs, NULL, &callchain_ops, entry); 40 unwind_stack(NULL, regs, NULL, &callchain_ops, entry);
59} 41}
60
61static void
62perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
63{
64 int is_user;
65
66 if (!regs)
67 return;
68
69 is_user = user_mode(regs);
70
71 if (is_user && current->state != TASK_RUNNING)
72 return;
73
74 /*
75 * Only the kernel side is implemented for now.
76 */
77 if (!is_user)
78 perf_callchain_kernel(regs, entry);
79}
80
81/*
82 * No need for separate IRQ and NMI entries.
83 */
84static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
85
86struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
87{
88 struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
89
90 entry->nr = 0;
91
92 perf_do_callchain(regs, entry);
93
94 return entry;
95}
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 7a3dc3567258..2ee21a47b5af 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -59,6 +59,24 @@ static inline int sh_pmu_initialized(void)
59 return !!sh_pmu; 59 return !!sh_pmu;
60} 60}
61 61
62const char *perf_pmu_name(void)
63{
64 if (!sh_pmu)
65 return NULL;
66
67 return sh_pmu->name;
68}
69EXPORT_SYMBOL_GPL(perf_pmu_name);
70
71int perf_num_counters(void)
72{
73 if (!sh_pmu)
74 return 0;
75
76 return sh_pmu->num_events;
77}
78EXPORT_SYMBOL_GPL(perf_num_counters);
79
62/* 80/*
63 * Release the PMU if this is the last perf_event. 81 * Release the PMU if this is the last perf_event.
64 */ 82 */
@@ -206,50 +224,80 @@ again:
206 local64_add(delta, &event->count); 224 local64_add(delta, &event->count);
207} 225}
208 226
209static void sh_pmu_disable(struct perf_event *event) 227static void sh_pmu_stop(struct perf_event *event, int flags)
210{ 228{
211 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 229 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
212 struct hw_perf_event *hwc = &event->hw; 230 struct hw_perf_event *hwc = &event->hw;
213 int idx = hwc->idx; 231 int idx = hwc->idx;
214 232
215 clear_bit(idx, cpuc->active_mask); 233 if (!(event->hw.state & PERF_HES_STOPPED)) {
216 sh_pmu->disable(hwc, idx); 234 sh_pmu->disable(hwc, idx);
235 cpuc->events[idx] = NULL;
236 event->hw.state |= PERF_HES_STOPPED;
237 }
238
239 if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
240 sh_perf_event_update(event, &event->hw, idx);
241 event->hw.state |= PERF_HES_UPTODATE;
242 }
243}
244
245static void sh_pmu_start(struct perf_event *event, int flags)
246{
247 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
248 struct hw_perf_event *hwc = &event->hw;
249 int idx = hwc->idx;
250
251 if (WARN_ON_ONCE(idx == -1))
252 return;
253
254 if (flags & PERF_EF_RELOAD)
255 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
217 256
218 barrier(); 257 cpuc->events[idx] = event;
258 event->hw.state = 0;
259 sh_pmu->enable(hwc, idx);
260}
219 261
220 sh_perf_event_update(event, &event->hw, idx); 262static void sh_pmu_del(struct perf_event *event, int flags)
263{
264 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
221 265
222 cpuc->events[idx] = NULL; 266 sh_pmu_stop(event, PERF_EF_UPDATE);
223 clear_bit(idx, cpuc->used_mask); 267 __clear_bit(event->hw.idx, cpuc->used_mask);
224 268
225 perf_event_update_userpage(event); 269 perf_event_update_userpage(event);
226} 270}
227 271
228static int sh_pmu_enable(struct perf_event *event) 272static int sh_pmu_add(struct perf_event *event, int flags)
229{ 273{
230 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 274 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
231 struct hw_perf_event *hwc = &event->hw; 275 struct hw_perf_event *hwc = &event->hw;
232 int idx = hwc->idx; 276 int idx = hwc->idx;
277 int ret = -EAGAIN;
278
279 perf_pmu_disable(event->pmu);
233 280
234 if (test_and_set_bit(idx, cpuc->used_mask)) { 281 if (__test_and_set_bit(idx, cpuc->used_mask)) {
235 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); 282 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
236 if (idx == sh_pmu->num_events) 283 if (idx == sh_pmu->num_events)
237 return -EAGAIN; 284 goto out;
238 285
239 set_bit(idx, cpuc->used_mask); 286 __set_bit(idx, cpuc->used_mask);
240 hwc->idx = idx; 287 hwc->idx = idx;
241 } 288 }
242 289
243 sh_pmu->disable(hwc, idx); 290 sh_pmu->disable(hwc, idx);
244 291
245 cpuc->events[idx] = event; 292 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
246 set_bit(idx, cpuc->active_mask); 293 if (flags & PERF_EF_START)
247 294 sh_pmu_start(event, PERF_EF_RELOAD);
248 sh_pmu->enable(hwc, idx);
249 295
250 perf_event_update_userpage(event); 296 perf_event_update_userpage(event);
251 297 ret = 0;
252 return 0; 298out:
299 perf_pmu_enable(event->pmu);
300 return ret;
253} 301}
254 302
255static void sh_pmu_read(struct perf_event *event) 303static void sh_pmu_read(struct perf_event *event)
@@ -257,24 +305,56 @@ static void sh_pmu_read(struct perf_event *event)
257 sh_perf_event_update(event, &event->hw, event->hw.idx); 305 sh_perf_event_update(event, &event->hw, event->hw.idx);
258} 306}
259 307
260static const struct pmu pmu = { 308static int sh_pmu_event_init(struct perf_event *event)
261 .enable = sh_pmu_enable,
262 .disable = sh_pmu_disable,
263 .read = sh_pmu_read,
264};
265
266const struct pmu *hw_perf_event_init(struct perf_event *event)
267{ 309{
268 int err = __hw_perf_event_init(event); 310 int err;
311
312 switch (event->attr.type) {
313 case PERF_TYPE_RAW:
314 case PERF_TYPE_HW_CACHE:
315 case PERF_TYPE_HARDWARE:
316 err = __hw_perf_event_init(event);
317 break;
318
319 default:
320 return -ENOENT;
321 }
322
269 if (unlikely(err)) { 323 if (unlikely(err)) {
270 if (event->destroy) 324 if (event->destroy)
271 event->destroy(event); 325 event->destroy(event);
272 return ERR_PTR(err);
273 } 326 }
274 327
275 return &pmu; 328 return err;
329}
330
331static void sh_pmu_enable(struct pmu *pmu)
332{
333 if (!sh_pmu_initialized())
334 return;
335
336 sh_pmu->enable_all();
337}
338
339static void sh_pmu_disable(struct pmu *pmu)
340{
341 if (!sh_pmu_initialized())
342 return;
343
344 sh_pmu->disable_all();
276} 345}
277 346
347static struct pmu pmu = {
348 .pmu_enable = sh_pmu_enable,
349 .pmu_disable = sh_pmu_disable,
350 .event_init = sh_pmu_event_init,
351 .add = sh_pmu_add,
352 .del = sh_pmu_del,
353 .start = sh_pmu_start,
354 .stop = sh_pmu_stop,
355 .read = sh_pmu_read,
356};
357
278static void sh_pmu_setup(int cpu) 358static void sh_pmu_setup(int cpu)
279{ 359{
280 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 360 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
@@ -299,32 +379,17 @@ sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
299 return NOTIFY_OK; 379 return NOTIFY_OK;
300} 380}
301 381
302void hw_perf_enable(void) 382int __cpuinit register_sh_pmu(struct sh_pmu *_pmu)
303{
304 if (!sh_pmu_initialized())
305 return;
306
307 sh_pmu->enable_all();
308}
309
310void hw_perf_disable(void)
311{
312 if (!sh_pmu_initialized())
313 return;
314
315 sh_pmu->disable_all();
316}
317
318int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
319{ 383{
320 if (sh_pmu) 384 if (sh_pmu)
321 return -EBUSY; 385 return -EBUSY;
322 sh_pmu = pmu; 386 sh_pmu = _pmu;
323 387
324 pr_info("Performance Events: %s support registered\n", pmu->name); 388 pr_info("Performance Events: %s support registered\n", _pmu->name);
325 389
326 WARN_ON(pmu->num_events > MAX_HWEVENTS); 390 WARN_ON(_pmu->num_events > MAX_HWEVENTS);
327 391
392 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
328 perf_cpu_notifier(sh_pmu_notifier); 393 perf_cpu_notifier(sh_pmu_notifier);
329 return 0; 394 return 0;
330} 395}
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index dcb126dc76fd..325f98b1736d 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -32,16 +32,16 @@ void free_thread_xstate(struct task_struct *tsk)
32#if THREAD_SHIFT < PAGE_SHIFT 32#if THREAD_SHIFT < PAGE_SHIFT
33static struct kmem_cache *thread_info_cache; 33static struct kmem_cache *thread_info_cache;
34 34
35struct thread_info *alloc_thread_info(struct task_struct *tsk) 35struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
36{ 36{
37 struct thread_info *ti; 37 struct thread_info *ti;
38
39 ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
40 if (unlikely(ti == NULL))
41 return NULL;
42#ifdef CONFIG_DEBUG_STACK_USAGE 38#ifdef CONFIG_DEBUG_STACK_USAGE
43 memset(ti, 0, THREAD_SIZE); 39 gfp_t mask = GFP_KERNEL | __GFP_ZERO;
40#else
41 gfp_t mask = GFP_KERNEL;
44#endif 42#endif
43
44 ti = kmem_cache_alloc_node(thread_info_cache, mask, node);
45 return ti; 45 return ti;
46} 46}
47 47
@@ -57,14 +57,16 @@ void thread_info_cache_init(void)
57 THREAD_SIZE, SLAB_PANIC, NULL); 57 THREAD_SIZE, SLAB_PANIC, NULL);
58} 58}
59#else 59#else
60struct thread_info *alloc_thread_info(struct task_struct *tsk) 60struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
61{ 61{
62#ifdef CONFIG_DEBUG_STACK_USAGE 62#ifdef CONFIG_DEBUG_STACK_USAGE
63 gfp_t mask = GFP_KERNEL | __GFP_ZERO; 63 gfp_t mask = GFP_KERNEL | __GFP_ZERO;
64#else 64#else
65 gfp_t mask = GFP_KERNEL; 65 gfp_t mask = GFP_KERNEL;
66#endif 66#endif
67 return (struct thread_info *)__get_free_pages(mask, THREAD_SIZE_ORDER); 67 struct page *page = alloc_pages_node(node, mask, THREAD_SIZE_ORDER);
68
69 return page ? page_address(page) : NULL;
68} 70}
69 71
70void free_thread_info(struct thread_info *ti) 72void free_thread_info(struct thread_info *ti)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 762a13984bbd..aaf6d59c2012 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -21,6 +21,7 @@
21#include <linux/fs.h> 21#include <linux/fs.h>
22#include <linux/ftrace.h> 22#include <linux/ftrace.h>
23#include <linux/hw_breakpoint.h> 23#include <linux/hw_breakpoint.h>
24#include <linux/prefetch.h>
24#include <asm/uaccess.h> 25#include <asm/uaccess.h>
25#include <asm/mmu_context.h> 26#include <asm/mmu_context.h>
26#include <asm/system.h> 27#include <asm/system.h>
@@ -101,8 +102,6 @@ EXPORT_SYMBOL(kernel_thread);
101void start_thread(struct pt_regs *regs, unsigned long new_pc, 102void start_thread(struct pt_regs *regs, unsigned long new_pc,
102 unsigned long new_sp) 103 unsigned long new_sp)
103{ 104{
104 set_fs(USER_DS);
105
106 regs->pr = 0; 105 regs->pr = 0;
107 regs->sr = SR_FD; 106 regs->sr = SR_FD;
108 regs->pc = new_pc; 107 regs->pc = new_pc;
diff --git a/arch/sh/kernel/ptrace.c b/arch/sh/kernel/ptrace.c
new file mode 100644
index 000000000000..0a05983633ca
--- /dev/null
+++ b/arch/sh/kernel/ptrace.c
@@ -0,0 +1,33 @@
1#include <linux/ptrace.h>
2
3/**
4 * regs_query_register_offset() - query register offset from its name
5 * @name: the name of a register
6 *
7 * regs_query_register_offset() returns the offset of a register in struct
8 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
9 */
10int regs_query_register_offset(const char *name)
11{
12 const struct pt_regs_offset *roff;
13 for (roff = regoffset_table; roff->name != NULL; roff++)
14 if (!strcmp(roff->name, name))
15 return roff->offset;
16 return -EINVAL;
17}
18
19/**
20 * regs_query_register_name() - query register name from its offset
21 * @offset: the offset of a register in struct pt_regs.
22 *
23 * regs_query_register_name() returns the name of a register from its
24 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
25 */
26const char *regs_query_register_name(unsigned int offset)
27{
28 const struct pt_regs_offset *roff;
29 for (roff = regoffset_table; roff->name != NULL; roff++)
30 if (roff->offset == offset)
31 return roff->name;
32 return NULL;
33}
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 6c4bbba2a675..3d7b209b2178 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -101,6 +101,8 @@ static int set_single_step(struct task_struct *tsk, unsigned long addr)
101 101
102 attr = bp->attr; 102 attr = bp->attr;
103 attr.bp_addr = addr; 103 attr.bp_addr = addr;
104 /* reenable breakpoint */
105 attr.disabled = false;
104 err = modify_user_hw_breakpoint(bp, &attr); 106 err = modify_user_hw_breakpoint(bp, &attr);
105 if (unlikely(err)) 107 if (unlikely(err))
106 return err; 108 return err;
@@ -115,7 +117,11 @@ void user_enable_single_step(struct task_struct *child)
115 117
116 set_tsk_thread_flag(child, TIF_SINGLESTEP); 118 set_tsk_thread_flag(child, TIF_SINGLESTEP);
117 119
120 if (ptrace_get_breakpoints(child) < 0)
121 return;
122
118 set_single_step(child, pc); 123 set_single_step(child, pc);
124 ptrace_put_breakpoints(child);
119} 125}
120 126
121void user_disable_single_step(struct task_struct *child) 127void user_disable_single_step(struct task_struct *child)
@@ -274,6 +280,33 @@ static int dspregs_active(struct task_struct *target,
274} 280}
275#endif 281#endif
276 282
283const struct pt_regs_offset regoffset_table[] = {
284 REGS_OFFSET_NAME(0),
285 REGS_OFFSET_NAME(1),
286 REGS_OFFSET_NAME(2),
287 REGS_OFFSET_NAME(3),
288 REGS_OFFSET_NAME(4),
289 REGS_OFFSET_NAME(5),
290 REGS_OFFSET_NAME(6),
291 REGS_OFFSET_NAME(7),
292 REGS_OFFSET_NAME(8),
293 REGS_OFFSET_NAME(9),
294 REGS_OFFSET_NAME(10),
295 REGS_OFFSET_NAME(11),
296 REGS_OFFSET_NAME(12),
297 REGS_OFFSET_NAME(13),
298 REGS_OFFSET_NAME(14),
299 REGS_OFFSET_NAME(15),
300 REG_OFFSET_NAME(pc),
301 REG_OFFSET_NAME(pr),
302 REG_OFFSET_NAME(sr),
303 REG_OFFSET_NAME(gbr),
304 REG_OFFSET_NAME(mach),
305 REG_OFFSET_NAME(macl),
306 REG_OFFSET_NAME(tra),
307 REG_OFFSET_END,
308};
309
277/* 310/*
278 * These are our native regset flavours. 311 * These are our native regset flavours.
279 */ 312 */
@@ -338,9 +371,9 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
338 return &user_sh_native_view; 371 return &user_sh_native_view;
339} 372}
340 373
341long arch_ptrace(struct task_struct *child, long request, long addr, long data) 374long arch_ptrace(struct task_struct *child, long request,
375 unsigned long addr, unsigned long data)
342{ 376{
343 struct user * dummy = NULL;
344 unsigned long __user *datap = (unsigned long __user *)data; 377 unsigned long __user *datap = (unsigned long __user *)data;
345 int ret; 378 int ret;
346 379
@@ -356,17 +389,23 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
356 389
357 if (addr < sizeof(struct pt_regs)) 390 if (addr < sizeof(struct pt_regs))
358 tmp = get_stack_long(child, addr); 391 tmp = get_stack_long(child, addr);
359 else if (addr >= (long) &dummy->fpu && 392 else if (addr >= offsetof(struct user, fpu) &&
360 addr < (long) &dummy->u_fpvalid) { 393 addr < offsetof(struct user, u_fpvalid)) {
361 if (!tsk_used_math(child)) { 394 if (!tsk_used_math(child)) {
362 if (addr == (long)&dummy->fpu.fpscr) 395 if (addr == offsetof(struct user, fpu.fpscr))
363 tmp = FPSCR_INIT; 396 tmp = FPSCR_INIT;
364 else 397 else
365 tmp = 0; 398 tmp = 0;
366 } else 399 } else {
367 tmp = ((long *)child->thread.xstate) 400 unsigned long index;
368 [(addr - (long)&dummy->fpu) >> 2]; 401 ret = init_fpu(child);
369 } else if (addr == (long) &dummy->u_fpvalid) 402 if (ret)
403 break;
404 index = addr - offsetof(struct user, fpu);
405 tmp = ((unsigned long *)child->thread.xstate)
406 [index >> 2];
407 }
408 } else if (addr == offsetof(struct user, u_fpvalid))
370 tmp = !!tsk_used_math(child); 409 tmp = !!tsk_used_math(child);
371 else if (addr == PT_TEXT_ADDR) 410 else if (addr == PT_TEXT_ADDR)
372 tmp = child->mm->start_code; 411 tmp = child->mm->start_code;
@@ -390,13 +429,18 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
390 429
391 if (addr < sizeof(struct pt_regs)) 430 if (addr < sizeof(struct pt_regs))
392 ret = put_stack_long(child, addr, data); 431 ret = put_stack_long(child, addr, data);
393 else if (addr >= (long) &dummy->fpu && 432 else if (addr >= offsetof(struct user, fpu) &&
394 addr < (long) &dummy->u_fpvalid) { 433 addr < offsetof(struct user, u_fpvalid)) {
434 unsigned long index;
435 ret = init_fpu(child);
436 if (ret)
437 break;
438 index = addr - offsetof(struct user, fpu);
395 set_stopped_child_used_math(child); 439 set_stopped_child_used_math(child);
396 ((long *)child->thread.xstate) 440 ((unsigned long *)child->thread.xstate)
397 [(addr - (long)&dummy->fpu) >> 2] = data; 441 [index >> 2] = data;
398 ret = 0; 442 ret = 0;
399 } else if (addr == (long) &dummy->u_fpvalid) { 443 } else if (addr == offsetof(struct user, u_fpvalid)) {
400 conditional_stopped_child_used_math(data, child); 444 conditional_stopped_child_used_math(data, child);
401 ret = 0; 445 ret = 0;
402 } 446 }
@@ -406,35 +450,35 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
406 return copy_regset_to_user(child, &user_sh_native_view, 450 return copy_regset_to_user(child, &user_sh_native_view,
407 REGSET_GENERAL, 451 REGSET_GENERAL,
408 0, sizeof(struct pt_regs), 452 0, sizeof(struct pt_regs),
409 (void __user *)data); 453 datap);
410 case PTRACE_SETREGS: 454 case PTRACE_SETREGS:
411 return copy_regset_from_user(child, &user_sh_native_view, 455 return copy_regset_from_user(child, &user_sh_native_view,
412 REGSET_GENERAL, 456 REGSET_GENERAL,
413 0, sizeof(struct pt_regs), 457 0, sizeof(struct pt_regs),
414 (const void __user *)data); 458 datap);
415#ifdef CONFIG_SH_FPU 459#ifdef CONFIG_SH_FPU
416 case PTRACE_GETFPREGS: 460 case PTRACE_GETFPREGS:
417 return copy_regset_to_user(child, &user_sh_native_view, 461 return copy_regset_to_user(child, &user_sh_native_view,
418 REGSET_FPU, 462 REGSET_FPU,
419 0, sizeof(struct user_fpu_struct), 463 0, sizeof(struct user_fpu_struct),
420 (void __user *)data); 464 datap);
421 case PTRACE_SETFPREGS: 465 case PTRACE_SETFPREGS:
422 return copy_regset_from_user(child, &user_sh_native_view, 466 return copy_regset_from_user(child, &user_sh_native_view,
423 REGSET_FPU, 467 REGSET_FPU,
424 0, sizeof(struct user_fpu_struct), 468 0, sizeof(struct user_fpu_struct),
425 (const void __user *)data); 469 datap);
426#endif 470#endif
427#ifdef CONFIG_SH_DSP 471#ifdef CONFIG_SH_DSP
428 case PTRACE_GETDSPREGS: 472 case PTRACE_GETDSPREGS:
429 return copy_regset_to_user(child, &user_sh_native_view, 473 return copy_regset_to_user(child, &user_sh_native_view,
430 REGSET_DSP, 474 REGSET_DSP,
431 0, sizeof(struct pt_dspregs), 475 0, sizeof(struct pt_dspregs),
432 (void __user *)data); 476 datap);
433 case PTRACE_SETDSPREGS: 477 case PTRACE_SETDSPREGS:
434 return copy_regset_from_user(child, &user_sh_native_view, 478 return copy_regset_from_user(child, &user_sh_native_view,
435 REGSET_DSP, 479 REGSET_DSP,
436 0, sizeof(struct pt_dspregs), 480 0, sizeof(struct pt_dspregs),
437 (const void __user *)data); 481 datap);
438#endif 482#endif
439 default: 483 default:
440 ret = ptrace_request(child, request, addr, data); 484 ret = ptrace_request(child, request, addr, data);
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 5fd644da7f02..c8f97649f354 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -20,7 +20,7 @@
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/smp_lock.h> 23#include <linux/bitops.h>
24#include <linux/errno.h> 24#include <linux/errno.h>
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/user.h> 26#include <linux/user.h>
@@ -252,6 +252,85 @@ static int fpregs_active(struct task_struct *target,
252} 252}
253#endif 253#endif
254 254
255const struct pt_regs_offset regoffset_table[] = {
256 REG_OFFSET_NAME(pc),
257 REG_OFFSET_NAME(sr),
258 REG_OFFSET_NAME(syscall_nr),
259 REGS_OFFSET_NAME(0),
260 REGS_OFFSET_NAME(1),
261 REGS_OFFSET_NAME(2),
262 REGS_OFFSET_NAME(3),
263 REGS_OFFSET_NAME(4),
264 REGS_OFFSET_NAME(5),
265 REGS_OFFSET_NAME(6),
266 REGS_OFFSET_NAME(7),
267 REGS_OFFSET_NAME(8),
268 REGS_OFFSET_NAME(9),
269 REGS_OFFSET_NAME(10),
270 REGS_OFFSET_NAME(11),
271 REGS_OFFSET_NAME(12),
272 REGS_OFFSET_NAME(13),
273 REGS_OFFSET_NAME(14),
274 REGS_OFFSET_NAME(15),
275 REGS_OFFSET_NAME(16),
276 REGS_OFFSET_NAME(17),
277 REGS_OFFSET_NAME(18),
278 REGS_OFFSET_NAME(19),
279 REGS_OFFSET_NAME(20),
280 REGS_OFFSET_NAME(21),
281 REGS_OFFSET_NAME(22),
282 REGS_OFFSET_NAME(23),
283 REGS_OFFSET_NAME(24),
284 REGS_OFFSET_NAME(25),
285 REGS_OFFSET_NAME(26),
286 REGS_OFFSET_NAME(27),
287 REGS_OFFSET_NAME(28),
288 REGS_OFFSET_NAME(29),
289 REGS_OFFSET_NAME(30),
290 REGS_OFFSET_NAME(31),
291 REGS_OFFSET_NAME(32),
292 REGS_OFFSET_NAME(33),
293 REGS_OFFSET_NAME(34),
294 REGS_OFFSET_NAME(35),
295 REGS_OFFSET_NAME(36),
296 REGS_OFFSET_NAME(37),
297 REGS_OFFSET_NAME(38),
298 REGS_OFFSET_NAME(39),
299 REGS_OFFSET_NAME(40),
300 REGS_OFFSET_NAME(41),
301 REGS_OFFSET_NAME(42),
302 REGS_OFFSET_NAME(43),
303 REGS_OFFSET_NAME(44),
304 REGS_OFFSET_NAME(45),
305 REGS_OFFSET_NAME(46),
306 REGS_OFFSET_NAME(47),
307 REGS_OFFSET_NAME(48),
308 REGS_OFFSET_NAME(49),
309 REGS_OFFSET_NAME(50),
310 REGS_OFFSET_NAME(51),
311 REGS_OFFSET_NAME(52),
312 REGS_OFFSET_NAME(53),
313 REGS_OFFSET_NAME(54),
314 REGS_OFFSET_NAME(55),
315 REGS_OFFSET_NAME(56),
316 REGS_OFFSET_NAME(57),
317 REGS_OFFSET_NAME(58),
318 REGS_OFFSET_NAME(59),
319 REGS_OFFSET_NAME(60),
320 REGS_OFFSET_NAME(61),
321 REGS_OFFSET_NAME(62),
322 REGS_OFFSET_NAME(63),
323 TREGS_OFFSET_NAME(0),
324 TREGS_OFFSET_NAME(1),
325 TREGS_OFFSET_NAME(2),
326 TREGS_OFFSET_NAME(3),
327 TREGS_OFFSET_NAME(4),
328 TREGS_OFFSET_NAME(5),
329 TREGS_OFFSET_NAME(6),
330 TREGS_OFFSET_NAME(7),
331 REG_OFFSET_END,
332};
333
255/* 334/*
256 * These are our native regset flavours. 335 * These are our native regset flavours.
257 */ 336 */
@@ -304,9 +383,11 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
304 return &user_sh64_native_view; 383 return &user_sh64_native_view;
305} 384}
306 385
307long arch_ptrace(struct task_struct *child, long request, long addr, long data) 386long arch_ptrace(struct task_struct *child, long request,
387 unsigned long addr, unsigned long data)
308{ 388{
309 int ret; 389 int ret;
390 unsigned long __user *datap = (unsigned long __user *) data;
310 391
311 switch (request) { 392 switch (request) {
312 /* read the word at location addr in the USER area. */ 393 /* read the word at location addr in the USER area. */
@@ -321,13 +402,18 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
321 tmp = get_stack_long(child, addr); 402 tmp = get_stack_long(child, addr);
322 else if ((addr >= offsetof(struct user, fpu)) && 403 else if ((addr >= offsetof(struct user, fpu)) &&
323 (addr < offsetof(struct user, u_fpvalid))) { 404 (addr < offsetof(struct user, u_fpvalid))) {
324 tmp = get_fpu_long(child, addr - offsetof(struct user, fpu)); 405 unsigned long index;
406 ret = init_fpu(child);
407 if (ret)
408 break;
409 index = addr - offsetof(struct user, fpu);
410 tmp = get_fpu_long(child, index);
325 } else if (addr == offsetof(struct user, u_fpvalid)) { 411 } else if (addr == offsetof(struct user, u_fpvalid)) {
326 tmp = !!tsk_used_math(child); 412 tmp = !!tsk_used_math(child);
327 } else { 413 } else {
328 break; 414 break;
329 } 415 }
330 ret = put_user(tmp, (unsigned long *)data); 416 ret = put_user(tmp, datap);
331 break; 417 break;
332 } 418 }
333 419
@@ -358,7 +444,12 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
358 } 444 }
359 else if ((addr >= offsetof(struct user, fpu)) && 445 else if ((addr >= offsetof(struct user, fpu)) &&
360 (addr < offsetof(struct user, u_fpvalid))) { 446 (addr < offsetof(struct user, u_fpvalid))) {
361 ret = put_fpu_long(child, addr - offsetof(struct user, fpu), data); 447 unsigned long index;
448 ret = init_fpu(child);
449 if (ret)
450 break;
451 index = addr - offsetof(struct user, fpu);
452 ret = put_fpu_long(child, index, data);
362 } 453 }
363 break; 454 break;
364 455
@@ -366,23 +457,23 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
366 return copy_regset_to_user(child, &user_sh64_native_view, 457 return copy_regset_to_user(child, &user_sh64_native_view,
367 REGSET_GENERAL, 458 REGSET_GENERAL,
368 0, sizeof(struct pt_regs), 459 0, sizeof(struct pt_regs),
369 (void __user *)data); 460 datap);
370 case PTRACE_SETREGS: 461 case PTRACE_SETREGS:
371 return copy_regset_from_user(child, &user_sh64_native_view, 462 return copy_regset_from_user(child, &user_sh64_native_view,
372 REGSET_GENERAL, 463 REGSET_GENERAL,
373 0, sizeof(struct pt_regs), 464 0, sizeof(struct pt_regs),
374 (const void __user *)data); 465 datap);
375#ifdef CONFIG_SH_FPU 466#ifdef CONFIG_SH_FPU
376 case PTRACE_GETFPREGS: 467 case PTRACE_GETFPREGS:
377 return copy_regset_to_user(child, &user_sh64_native_view, 468 return copy_regset_to_user(child, &user_sh64_native_view,
378 REGSET_FPU, 469 REGSET_FPU,
379 0, sizeof(struct user_fpu_struct), 470 0, sizeof(struct user_fpu_struct),
380 (void __user *)data); 471 datap);
381 case PTRACE_SETFPREGS: 472 case PTRACE_SETFPREGS:
382 return copy_regset_from_user(child, &user_sh64_native_view, 473 return copy_regset_from_user(child, &user_sh64_native_view,
383 REGSET_FPU, 474 REGSET_FPU,
384 0, sizeof(struct user_fpu_struct), 475 0, sizeof(struct user_fpu_struct),
385 (const void __user *)data); 476 datap);
386#endif 477#endif
387 default: 478 default:
388 ret = ptrace_request(child, request, addr, data); 479 ret = ptrace_request(child, request, addr, data);
@@ -392,13 +483,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
392 return ret; 483 return ret;
393} 484}
394 485
395asmlinkage int sh64_ptrace(long request, long pid, long addr, long data) 486asmlinkage int sh64_ptrace(long request, long pid,
487 unsigned long addr, unsigned long data)
396{ 488{
397#define WPC_DBRMODE 0x0d104008 489#define WPC_DBRMODE 0x0d104008
398 static int first_call = 1; 490 static unsigned long first_call;
399 491
400 lock_kernel(); 492 if (!test_and_set_bit(0, &first_call)) {
401 if (first_call) {
402 /* Set WPC.DBRMODE to 0. This makes all debug events get 493 /* Set WPC.DBRMODE to 0. This makes all debug events get
403 * delivered through RESVEC, i.e. into the handlers in entry.S. 494 * delivered through RESVEC, i.e. into the handlers in entry.S.
404 * (If the kernel was downloaded using a remote gdb, WPC.DBRMODE 495 * (If the kernel was downloaded using a remote gdb, WPC.DBRMODE
@@ -408,9 +499,7 @@ asmlinkage int sh64_ptrace(long request, long pid, long addr, long data)
408 * the remote gdb.) */ 499 * the remote gdb.) */
409 printk("DBRMODE set to 0 to permit native debugging\n"); 500 printk("DBRMODE set to 0 to permit native debugging\n");
410 poke_real_address_q(WPC_DBRMODE, 0); 501 poke_real_address_q(WPC_DBRMODE, 0);
411 first_call = 0;
412 } 502 }
413 unlock_kernel();
414 503
415 return sys_ptrace(request, pid, addr, data); 504 return sys_ptrace(request, pid, addr, data);
416} 505}
diff --git a/arch/sh/kernel/reboot.c b/arch/sh/kernel/reboot.c
index b1fca66bb92e..ca6a5ca64015 100644
--- a/arch/sh/kernel/reboot.c
+++ b/arch/sh/kernel/reboot.c
@@ -9,6 +9,7 @@
9#include <asm/addrspace.h> 9#include <asm/addrspace.h>
10#include <asm/reboot.h> 10#include <asm/reboot.h>
11#include <asm/system.h> 11#include <asm/system.h>
12#include <asm/tlbflush.h>
12 13
13void (*pm_power_off)(void); 14void (*pm_power_off)(void);
14EXPORT_SYMBOL(pm_power_off); 15EXPORT_SYMBOL(pm_power_off);
@@ -25,6 +26,9 @@ static void native_machine_restart(char * __unused)
25{ 26{
26 local_irq_disable(); 27 local_irq_disable();
27 28
29 /* Destroy all of the TLBs in preparation for reset by MMU */
30 __flush_tlb_global();
31
28 /* Address error with SR.BL=1 first. */ 32 /* Address error with SR.BL=1 first. */
29 trigger_address_error(); 33 trigger_address_error();
30 34
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index e769401a78ba..58bff45d1156 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -12,7 +12,6 @@
12#include <linux/initrd.h> 12#include <linux/initrd.h>
13#include <linux/bootmem.h> 13#include <linux/bootmem.h>
14#include <linux/console.h> 14#include <linux/console.h>
15#include <linux/seq_file.h>
16#include <linux/root_dev.h> 15#include <linux/root_dev.h>
17#include <linux/utsname.h> 16#include <linux/utsname.h>
18#include <linux/nodemask.h> 17#include <linux/nodemask.h>
@@ -24,7 +23,6 @@
24#include <linux/module.h> 23#include <linux/module.h>
25#include <linux/smp.h> 24#include <linux/smp.h>
26#include <linux/err.h> 25#include <linux/err.h>
27#include <linux/debugfs.h>
28#include <linux/crash_dump.h> 26#include <linux/crash_dump.h>
29#include <linux/mmzone.h> 27#include <linux/mmzone.h>
30#include <linux/clk.h> 28#include <linux/clk.h>
@@ -42,6 +40,7 @@
42#include <asm/smp.h> 40#include <asm/smp.h>
43#include <asm/mmu_context.h> 41#include <asm/mmu_context.h>
44#include <asm/mmzone.h> 42#include <asm/mmzone.h>
43#include <asm/sparsemem.h>
45 44
46/* 45/*
47 * Initialize loops_per_jiffy as 10000000 (1000MIPS). 46 * Initialize loops_per_jiffy as 10000000 (1000MIPS).
@@ -53,6 +52,7 @@ struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
53 .type = CPU_SH_NONE, 52 .type = CPU_SH_NONE,
54 .family = CPU_FAMILY_UNKNOWN, 53 .family = CPU_FAMILY_UNKNOWN,
55 .loops_per_jiffy = 10000000, 54 .loops_per_jiffy = 10000000,
55 .phys_bits = MAX_PHYSMEM_BITS,
56 }, 56 },
57}; 57};
58EXPORT_SYMBOL(cpu_data); 58EXPORT_SYMBOL(cpu_data);
@@ -136,8 +136,9 @@ void __init check_for_initrd(void)
136 goto disable; 136 goto disable;
137 } 137 }
138 138
139 if (unlikely(start < PAGE_OFFSET)) { 139 if (unlikely(start < __MEMORY_START)) {
140 pr_err("initrd start < PAGE_OFFSET\n"); 140 pr_err("initrd start (%08lx) < __MEMORY_START(%x)\n",
141 start, __MEMORY_START);
141 goto disable; 142 goto disable;
142 } 143 }
143 144
@@ -149,7 +150,7 @@ void __init check_for_initrd(void)
149 } 150 }
150 151
151 /* 152 /*
152 * If we got this far inspite of the boot loader's best efforts 153 * If we got this far in spite of the boot loader's best efforts
153 * to the contrary, assume we actually have a valid initrd and 154 * to the contrary, assume we actually have a valid initrd and
154 * fix up the root dev. 155 * fix up the root dev.
155 */ 156 */
@@ -158,7 +159,7 @@ void __init check_for_initrd(void)
158 /* 159 /*
159 * Address sanitization 160 * Address sanitization
160 */ 161 */
161 initrd_start = (unsigned long)__va(__pa(start)); 162 initrd_start = (unsigned long)__va(start);
162 initrd_end = initrd_start + INITRD_SIZE; 163 initrd_end = initrd_start + INITRD_SIZE;
163 164
164 memblock_reserve(__pa(initrd_start), INITRD_SIZE); 165 memblock_reserve(__pa(initrd_start), INITRD_SIZE);
@@ -317,158 +318,3 @@ int test_mode_pin(int pin)
317{ 318{
318 return sh_mv.mv_mode_pins() & pin; 319 return sh_mv.mv_mode_pins() & pin;
319} 320}
320
321static const char *cpu_name[] = {
322 [CPU_SH7201] = "SH7201",
323 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
324 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
325 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
326 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
327 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
328 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
329 [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
330 [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
331 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
332 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
333 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
334 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
335 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
336 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
337 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
338 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
339 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
340 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
341 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
342 [CPU_SH_NONE] = "Unknown"
343};
344
345const char *get_cpu_subtype(struct sh_cpuinfo *c)
346{
347 return cpu_name[c->type];
348}
349EXPORT_SYMBOL(get_cpu_subtype);
350
351#ifdef CONFIG_PROC_FS
352/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
353static const char *cpu_flags[] = {
354 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
355 "ptea", "llsc", "l2", "op32", "pteaex", NULL
356};
357
358static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
359{
360 unsigned long i;
361
362 seq_printf(m, "cpu flags\t:");
363
364 if (!c->flags) {
365 seq_printf(m, " %s\n", cpu_flags[0]);
366 return;
367 }
368
369 for (i = 0; cpu_flags[i]; i++)
370 if ((c->flags & (1 << i)))
371 seq_printf(m, " %s", cpu_flags[i+1]);
372
373 seq_printf(m, "\n");
374}
375
376static void show_cacheinfo(struct seq_file *m, const char *type,
377 struct cache_info info)
378{
379 unsigned int cache_size;
380
381 cache_size = info.ways * info.sets * info.linesz;
382
383 seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
384 type, cache_size >> 10, info.ways);
385}
386
387/*
388 * Get CPU information for use by the procfs.
389 */
390static int show_cpuinfo(struct seq_file *m, void *v)
391{
392 struct sh_cpuinfo *c = v;
393 unsigned int cpu = c - cpu_data;
394
395 if (!cpu_online(cpu))
396 return 0;
397
398 if (cpu == 0)
399 seq_printf(m, "machine\t\t: %s\n", get_system_type());
400 else
401 seq_printf(m, "\n");
402
403 seq_printf(m, "processor\t: %d\n", cpu);
404 seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
405 seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
406 if (c->cut_major == -1)
407 seq_printf(m, "cut\t\t: unknown\n");
408 else if (c->cut_minor == -1)
409 seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
410 else
411 seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
412
413 show_cpuflags(m, c);
414
415 seq_printf(m, "cache type\t: ");
416
417 /*
418 * Check for what type of cache we have, we support both the
419 * unified cache on the SH-2 and SH-3, as well as the harvard
420 * style cache on the SH-4.
421 */
422 if (c->icache.flags & SH_CACHE_COMBINED) {
423 seq_printf(m, "unified\n");
424 show_cacheinfo(m, "cache", c->icache);
425 } else {
426 seq_printf(m, "split (harvard)\n");
427 show_cacheinfo(m, "icache", c->icache);
428 show_cacheinfo(m, "dcache", c->dcache);
429 }
430
431 /* Optional secondary cache */
432 if (c->flags & CPU_HAS_L2_CACHE)
433 show_cacheinfo(m, "scache", c->scache);
434
435 seq_printf(m, "bogomips\t: %lu.%02lu\n",
436 c->loops_per_jiffy/(500000/HZ),
437 (c->loops_per_jiffy/(5000/HZ)) % 100);
438
439 return 0;
440}
441
442static void *c_start(struct seq_file *m, loff_t *pos)
443{
444 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
445}
446static void *c_next(struct seq_file *m, void *v, loff_t *pos)
447{
448 ++*pos;
449 return c_start(m, pos);
450}
451static void c_stop(struct seq_file *m, void *v)
452{
453}
454const struct seq_operations cpuinfo_op = {
455 .start = c_start,
456 .next = c_next,
457 .stop = c_stop,
458 .show = show_cpuinfo,
459};
460#endif /* CONFIG_PROC_FS */
461
462struct dentry *sh_debugfs_root;
463
464static int __init sh_debugfs_init(void)
465{
466 sh_debugfs_root = debugfs_create_dir("sh", NULL);
467 if (!sh_debugfs_root)
468 return -ENOMEM;
469 if (IS_ERR(sh_debugfs_root))
470 return PTR_ERR(sh_debugfs_root);
471
472 return 0;
473}
474arch_initcall(sh_debugfs_init);
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 509b36b45115..6207561ea34a 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -20,6 +20,7 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/cpu.h> 21#include <linux/cpu.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/sched.h>
23#include <asm/atomic.h> 24#include <asm/atomic.h>
24#include <asm/processor.h> 25#include <asm/processor.h>
25#include <asm/system.h> 26#include <asm/system.h>
@@ -323,6 +324,7 @@ void smp_message_recv(unsigned int msg)
323 generic_smp_call_function_interrupt(); 324 generic_smp_call_function_interrupt();
324 break; 325 break;
325 case SMP_MSG_RESCHEDULE: 326 case SMP_MSG_RESCHEDULE:
327 scheduler_ipi();
326 break; 328 break;
327 case SMP_MSG_FUNCTION_SINGLE: 329 case SMP_MSG_FUNCTION_SINGLE:
328 generic_smp_call_function_single_interrupt(); 330 generic_smp_call_function_single_interrupt();
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index c2e45c48409c..bf989e063a0c 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -17,15 +17,6 @@
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18#include <asm/stacktrace.h> 18#include <asm/stacktrace.h>
19 19
20static void save_stack_warning(void *data, char *msg)
21{
22}
23
24static void
25save_stack_warning_symbol(void *data, char *msg, unsigned long symbol)
26{
27}
28
29static int save_stack_stack(void *data, char *name) 20static int save_stack_stack(void *data, char *name)
30{ 21{
31 return 0; 22 return 0;
@@ -51,8 +42,6 @@ static void save_stack_address(void *data, unsigned long addr, int reliable)
51} 42}
52 43
53static const struct stacktrace_ops save_stack_ops = { 44static const struct stacktrace_ops save_stack_ops = {
54 .warning = save_stack_warning,
55 .warning_symbol = save_stack_warning_symbol,
56 .stack = save_stack_stack, 45 .stack = save_stack_stack,
57 .address = save_stack_address, 46 .address = save_stack_address,
58}; 47};
@@ -88,8 +77,6 @@ save_stack_address_nosched(void *data, unsigned long addr, int reliable)
88} 77}
89 78
90static const struct stacktrace_ops save_stack_ops_nosched = { 79static const struct stacktrace_ops save_stack_ops_nosched = {
91 .warning = save_stack_warning,
92 .warning_symbol = save_stack_warning_symbol,
93 .stack = save_stack_stack, 80 .stack = save_stack_stack,
94 .address = save_stack_address_nosched, 81 .address = save_stack_address_nosched,
95}; 82};
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 81f58371613d..8c6a350df751 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -88,7 +88,7 @@ asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op)
88 } 88 }
89 89
90 if (op & CACHEFLUSH_I) 90 if (op & CACHEFLUSH_I)
91 flush_cache_all(); 91 flush_icache_range(addr, addr+len);
92 92
93 up_read(&current->mm->mmap_sem); 93 up_read(&current->mm->mmap_sem);
94 return 0; 94 return 0;
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 19fd11dd9871..39b051de4c7c 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -353,3 +353,32 @@ ENTRY(sys_call_table)
353 .long sys_pwritev 353 .long sys_pwritev
354 .long sys_rt_tgsigqueueinfo /* 335 */ 354 .long sys_rt_tgsigqueueinfo /* 335 */
355 .long sys_perf_event_open 355 .long sys_perf_event_open
356 .long sys_fanotify_init
357 .long sys_fanotify_mark
358 .long sys_prlimit64
359 /* Broken-out socket family */
360 .long sys_socket /* 340 */
361 .long sys_bind
362 .long sys_connect
363 .long sys_listen
364 .long sys_accept
365 .long sys_getsockname /* 345 */
366 .long sys_getpeername
367 .long sys_socketpair
368 .long sys_send
369 .long sys_sendto
370 .long sys_recv /* 350 */
371 .long sys_recvfrom
372 .long sys_shutdown
373 .long sys_setsockopt
374 .long sys_getsockopt
375 .long sys_sendmsg /* 355 */
376 .long sys_recvmsg
377 .long sys_recvmmsg
378 .long sys_accept4
379 .long sys_name_to_handle_at
380 .long sys_open_by_handle_at /* 360 */
381 .long sys_clock_adjtime
382 .long sys_syncfs
383 .long sys_sendmmsg
384 .long sys_setns
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index 2048a20d7c80..089c4d825d08 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -393,3 +393,12 @@ sys_call_table:
393 .long sys_perf_event_open 393 .long sys_perf_event_open
394 .long sys_recvmmsg /* 365 */ 394 .long sys_recvmmsg /* 365 */
395 .long sys_accept4 395 .long sys_accept4
396 .long sys_fanotify_init
397 .long sys_fanotify_mark
398 .long sys_prlimit64
399 .long sys_name_to_handle_at /* 370 */
400 .long sys_open_by_handle_at
401 .long sys_clock_adjtime
402 .long sys_syncfs
403 .long sys_sendmmsg
404 .long sys_setns /* 375 */
diff --git a/arch/sh/kernel/topology.c b/arch/sh/kernel/topology.c
index 948fdb656933..38e862852dd0 100644
--- a/arch/sh/kernel/topology.c
+++ b/arch/sh/kernel/topology.c
@@ -17,6 +17,7 @@
17static DEFINE_PER_CPU(struct cpu, cpu_devices); 17static DEFINE_PER_CPU(struct cpu, cpu_devices);
18 18
19cpumask_t cpu_core_map[NR_CPUS]; 19cpumask_t cpu_core_map[NR_CPUS];
20EXPORT_SYMBOL(cpu_core_map);
20 21
21static cpumask_t cpu_coregroup_map(unsigned int cpu) 22static cpumask_t cpu_coregroup_map(unsigned int cpu)
22{ 23{
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index c3d86fa71ddf..b51a17104b5f 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -5,7 +5,7 @@
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf 6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells 7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt 8 * Copyright (C) 2002 - 2010 Paul Mundt
9 * 9 *
10 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
@@ -26,6 +26,7 @@
26#include <linux/limits.h> 26#include <linux/limits.h>
27#include <linux/sysfs.h> 27#include <linux/sysfs.h>
28#include <linux/uaccess.h> 28#include <linux/uaccess.h>
29#include <linux/perf_event.h>
29#include <asm/system.h> 30#include <asm/system.h>
30#include <asm/alignment.h> 31#include <asm/alignment.h>
31#include <asm/fpu.h> 32#include <asm/fpu.h>
@@ -86,7 +87,6 @@ void die(const char * str, struct pt_regs * regs, long err)
86 bust_spinlocks(1); 87 bust_spinlocks(1);
87 88
88 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 89 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
89 sysfs_printk_last_file();
90 print_modules(); 90 print_modules();
91 show_regs(regs); 91 show_regs(regs);
92 92
@@ -369,7 +369,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
369#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 369#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
370 370
371int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 371int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
372 struct mem_access *ma, int expected) 372 struct mem_access *ma, int expected,
373 unsigned long address)
373{ 374{
374 u_int rm; 375 u_int rm;
375 int ret, index; 376 int ret, index;
@@ -383,9 +384,18 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
383 index = (instruction>>8)&15; /* 0x0F00 */ 384 index = (instruction>>8)&15; /* 0x0F00 */
384 rm = regs->regs[index]; 385 rm = regs->regs[index];
385 386
386 /* shout about fixups */ 387 /*
387 if (!expected) 388 * Log the unexpected fixups, and then pass them on to perf.
389 *
390 * We intentionally don't report the expected cases to perf as
391 * otherwise the trapped I/O case will skew the results too much
392 * to be useful.
393 */
394 if (!expected) {
388 unaligned_fixups_notify(current, instruction, regs); 395 unaligned_fixups_notify(current, instruction, regs);
396 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0,
397 regs, address);
398 }
389 399
390 ret = -EFAULT; 400 ret = -EFAULT;
391 switch (instruction&0xF000) { 401 switch (instruction&0xF000) {
@@ -574,7 +584,8 @@ fixup:
574 584
575 set_fs(USER_DS); 585 set_fs(USER_DS);
576 tmp = handle_unaligned_access(instruction, regs, 586 tmp = handle_unaligned_access(instruction, regs,
577 &user_mem_access, 0); 587 &user_mem_access, 0,
588 address);
578 set_fs(oldfs); 589 set_fs(oldfs);
579 590
580 if (tmp == 0) 591 if (tmp == 0)
@@ -607,8 +618,8 @@ uspace_segv:
607 618
608 unaligned_fixups_notify(current, instruction, regs); 619 unaligned_fixups_notify(current, instruction, regs);
609 620
610 handle_unaligned_access(instruction, regs, 621 handle_unaligned_access(instruction, regs, &user_mem_access,
611 &user_mem_access, 0); 622 0, address);
612 set_fs(oldfs); 623 set_fs(oldfs);
613 } 624 }
614} 625}
@@ -802,6 +813,9 @@ void __cpuinit per_cpu_trap_init(void)
802 : /* no output */ 813 : /* no output */
803 : "r" (&vbr_base) 814 : "r" (&vbr_base)
804 : "memory"); 815 : "memory");
816
817 /* disable exception blocking now when the vbr has been setup */
818 clear_bl_bit();
805} 819}
806 820
807void *set_exception_table_vec(unsigned int vec, void *handler) 821void *set_exception_table_vec(unsigned int vec, void *handler)
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index e67e140bf1f6..6713ca97e553 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -24,6 +24,7 @@
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/sysctl.h> 25#include <linux/sysctl.h>
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/perf_event.h>
27#include <asm/system.h> 28#include <asm/system.h>
28#include <asm/uaccess.h> 29#include <asm/uaccess.h>
29#include <asm/io.h> 30#include <asm/io.h>
@@ -50,7 +51,7 @@ asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
50 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \ 51 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
51} 52}
52 53
53spinlock_t die_lock; 54static DEFINE_SPINLOCK(die_lock);
54 55
55void die(const char * str, struct pt_regs * regs, long err) 56void die(const char * str, struct pt_regs * regs, long err)
56{ 57{
@@ -433,6 +434,8 @@ static int misaligned_load(struct pt_regs *regs,
433 return error; 434 return error;
434 } 435 }
435 436
437 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
438
436 destreg = (opcode >> 4) & 0x3f; 439 destreg = (opcode >> 4) & 0x3f;
437 if (user_mode(regs)) { 440 if (user_mode(regs)) {
438 __u64 buffer; 441 __u64 buffer;
@@ -509,6 +512,8 @@ static int misaligned_store(struct pt_regs *regs,
509 return error; 512 return error;
510 } 513 }
511 514
515 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
516
512 srcreg = (opcode >> 4) & 0x3f; 517 srcreg = (opcode >> 4) & 0x3f;
513 if (user_mode(regs)) { 518 if (user_mode(regs)) {
514 __u64 buffer; 519 __u64 buffer;
@@ -583,6 +588,8 @@ static int misaligned_fpu_load(struct pt_regs *regs,
583 return error; 588 return error;
584 } 589 }
585 590
591 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
592
586 destreg = (opcode >> 4) & 0x3f; 593 destreg = (opcode >> 4) & 0x3f;
587 if (user_mode(regs)) { 594 if (user_mode(regs)) {
588 __u64 buffer; 595 __u64 buffer;
@@ -658,6 +665,8 @@ static int misaligned_fpu_store(struct pt_regs *regs,
658 return error; 665 return error;
659 } 666 }
660 667
668 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
669
661 srcreg = (opcode >> 4) & 0x3f; 670 srcreg = (opcode >> 4) & 0x3f;
662 if (user_mode(regs)) { 671 if (user_mode(regs)) {
663 __u64 buffer; 672 __u64 buffer;
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 7f8a709c3ada..731c10ce67b5 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -66,7 +66,7 @@ SECTIONS
66 __machvec_end = .; 66 __machvec_end = .;
67 } 67 }
68 68
69 PERCPU(PAGE_SIZE) 69 PERCPU_SECTION(L1_CACHE_BYTES)
70 70
71 /* 71 /*
72 * .exit.text is discarded at runtime, not link time, to deal with 72 * .exit.text is discarded at runtime, not link time, to deal with
diff --git a/arch/sh/kernel/vsyscall/vsyscall-trapa.S b/arch/sh/kernel/vsyscall/vsyscall-trapa.S
index 3b6eb34c43fa..3e70f851cdc6 100644
--- a/arch/sh/kernel/vsyscall/vsyscall-trapa.S
+++ b/arch/sh/kernel/vsyscall/vsyscall-trapa.S
@@ -8,9 +8,9 @@ __kernel_vsyscall:
8 * fill out .eh_frame -- PFM. */ 8 * fill out .eh_frame -- PFM. */
9.LEND_vsyscall: 9.LEND_vsyscall:
10 .size __kernel_vsyscall,.-.LSTART_vsyscall 10 .size __kernel_vsyscall,.-.LSTART_vsyscall
11 .previous
12 11
13 .section .eh_frame,"a",@progbits 12 .section .eh_frame,"a",@progbits
13 .previous
14.LCIE: 14.LCIE:
15 .ualong .LCIE_end - .LCIE_start 15 .ualong .LCIE_end - .LCIE_start
16.LCIE_start: 16.LCIE_start:
diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c
index 242117cbad67..1d6d51a1ce79 100644
--- a/arch/sh/kernel/vsyscall/vsyscall.c
+++ b/arch/sh/kernel/vsyscall/vsyscall.c
@@ -94,17 +94,17 @@ const char *arch_vma_name(struct vm_area_struct *vma)
94 return NULL; 94 return NULL;
95} 95}
96 96
97struct vm_area_struct *get_gate_vma(struct task_struct *task) 97struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
98{ 98{
99 return NULL; 99 return NULL;
100} 100}
101 101
102int in_gate_area(struct task_struct *task, unsigned long address) 102int in_gate_area(struct mm_struct *mm, unsigned long address)
103{ 103{
104 return 0; 104 return 0;
105} 105}
106 106
107int in_gate_area_no_task(unsigned long address) 107int in_gate_area_no_mm(unsigned long address)
108{ 108{
109 return 0; 109 return 0;
110} 110}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-04 04:33:44 -0400