diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-shx3.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-shx3.c | 234 |
1 files changed, 218 insertions, 16 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 704c064f70dc..c6cdd7e3b049 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
@@ -11,6 +11,7 @@ | |||
11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
12 | #include <linux/serial.h> | 12 | #include <linux/serial.h> |
13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
14 | #include <asm/mmzone.h> | ||
14 | #include <asm/sci.h> | 15 | #include <asm/sci.h> |
15 | 16 | ||
16 | static struct plat_sci_port sci_platform_data[] = { | 17 | static struct plat_sci_port sci_platform_data[] = { |
@@ -58,28 +59,229 @@ static int __init shx3_devices_setup(void) | |||
58 | } | 59 | } |
59 | __initcall(shx3_devices_setup); | 60 | __initcall(shx3_devices_setup); |
60 | 61 | ||
61 | static struct intc2_data intc2_irq_table[] = { | 62 | enum { |
62 | { 16, 0, 0, 0, 1, 2 }, /* TMU0 */ | 63 | UNUSED = 0, |
63 | { 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */ | 64 | |
64 | { 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */ | 65 | /* interrupt sources */ |
65 | { 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */ | 66 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
66 | { 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */ | 67 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
68 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | ||
69 | IRL_HHLL, IRL_HHLH, IRL_HHHL, | ||
70 | IRQ0, IRQ1, IRQ2, IRQ3, | ||
71 | HUDII, | ||
72 | TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, | ||
73 | PCII0, PCII1, PCII2, PCII3, PCII4, | ||
74 | PCII5, PCII6, PCII7, PCII8, PCII9, | ||
75 | SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, | ||
76 | SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, | ||
77 | SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, | ||
78 | SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI, | ||
79 | DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, | ||
80 | DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE, | ||
81 | DU, | ||
82 | DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, | ||
83 | DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, | ||
84 | IIC, VIN0, VIN1, VCORE0, ATAPI, | ||
85 | DTU0_TEND, DTU0_AE, DTU0_TMISS, | ||
86 | DTU1_TEND, DTU1_AE, DTU1_TMISS, | ||
87 | DTU2_TEND, DTU2_AE, DTU2_TMISS, | ||
88 | DTU3_TEND, DTU3_AE, DTU3_TMISS, | ||
89 | FE0, FE1, | ||
90 | GPIO0, GPIO1, GPIO2, GPIO3, | ||
91 | PAM, IRM, | ||
92 | INTICI0, INTICI1, INTICI2, INTICI3, | ||
93 | INTICI4, INTICI5, INTICI6, INTICI7, | ||
94 | |||
95 | /* interrupt groups */ | ||
96 | IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, | ||
97 | DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, | ||
98 | }; | ||
99 | |||
100 | static struct intc_vect vectors[] __initdata = { | ||
101 | INTC_VECT(HUDII, 0x3e0), | ||
102 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | ||
103 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460), | ||
104 | INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0), | ||
105 | INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520), | ||
106 | INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560), | ||
107 | INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0), | ||
108 | INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0), | ||
109 | INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620), | ||
110 | INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), | ||
111 | INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), | ||
112 | INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), | ||
113 | INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), | ||
114 | INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820), | ||
115 | INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860), | ||
116 | INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0), | ||
117 | INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0), | ||
118 | INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920), | ||
119 | INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960), | ||
120 | INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0), | ||
121 | INTC_VECT(DMAC0_DMAE, 0x9c0), | ||
122 | INTC_VECT(DU, 0x9e0), | ||
123 | INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20), | ||
124 | INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60), | ||
125 | INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0), | ||
126 | INTC_VECT(DMAC1_DMAE, 0xac0), | ||
127 | INTC_VECT(IIC, 0xae0), | ||
128 | INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), | ||
129 | INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), | ||
130 | INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20), | ||
131 | INTC_VECT(DTU0_TMISS, 0xc40), | ||
132 | INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80), | ||
133 | INTC_VECT(DTU1_TMISS, 0xca0), | ||
134 | INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0), | ||
135 | INTC_VECT(DTU2_TMISS, 0xd00), | ||
136 | INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40), | ||
137 | INTC_VECT(DTU3_TMISS, 0xd60), | ||
138 | INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), | ||
139 | INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), | ||
140 | INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), | ||
141 | INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0), | ||
142 | INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), | ||
143 | INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), | ||
144 | INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), | ||
145 | INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), | ||
67 | }; | 146 | }; |
68 | 147 | ||
69 | static struct intc2_desc intc2_irq_desc __read_mostly = { | 148 | static struct intc_group groups[] __initdata = { |
70 | .prio_base = 0xfe410000, | 149 | INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
71 | .msk_base = 0xfe410820, | 150 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
72 | .mskclr_base = 0xfe410850, | 151 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, |
152 | IRL_HHLL, IRL_HHLH, IRL_HHHL), | ||
153 | INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), | ||
154 | INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), | ||
155 | INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), | ||
156 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), | ||
157 | INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI), | ||
158 | INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, | ||
159 | DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), | ||
160 | INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, | ||
161 | DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), | ||
162 | INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS), | ||
163 | INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS), | ||
164 | INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS), | ||
165 | INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS), | ||
166 | }; | ||
73 | 167 | ||
74 | .intc2_data = intc2_irq_table, | 168 | static struct intc_prio priorities[] __initdata = { |
75 | .nr_irqs = ARRAY_SIZE(intc2_irq_table), | 169 | INTC_PRIO(SCIF0, 3), |
170 | INTC_PRIO(SCIF1, 3), | ||
171 | INTC_PRIO(SCIF2, 3), | ||
172 | INTC_PRIO(SCIF3, 3), | ||
173 | }; | ||
76 | 174 | ||
77 | .chip = { | 175 | static struct intc_mask_reg mask_registers[] __initdata = { |
78 | .name = "INTC2-SHX3", | 176 | { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ |
79 | }, | 177 | { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
178 | { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */ | ||
179 | { IRL } }, | ||
180 | { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */ | ||
181 | { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, | ||
182 | DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, | ||
183 | 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ | ||
184 | 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, | ||
185 | { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ | ||
186 | { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ | ||
187 | PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, | ||
188 | PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, | ||
189 | DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, | ||
190 | DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, | ||
191 | DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, | ||
192 | { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ | ||
193 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
194 | SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, | ||
195 | SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, | ||
196 | SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, | ||
197 | SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, | ||
198 | }; | ||
199 | |||
200 | static struct intc_prio_reg prio_registers[] __initdata = { | ||
201 | { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | ||
202 | |||
203 | { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, | ||
204 | TMU3, TMU2, TMU1, TMU0 } }, | ||
205 | { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0, | ||
206 | SCIF3, SCIF2, | ||
207 | SCIF1, SCIF0 } }, | ||
208 | { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, | ||
209 | PCII56789, PCII4, | ||
210 | PCII3, PCII2, | ||
211 | PCII1, PCII0 } }, | ||
212 | { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0, | ||
213 | VIN1, VIN0, IIC, DU} }, | ||
214 | { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3, | ||
215 | GPIO2, GPIO1, GPIO0, IRM } }, | ||
216 | { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ | ||
217 | { INTICI7, INTICI6, INTICI5, INTICI4, | ||
218 | INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) }, | ||
219 | }; | ||
220 | |||
221 | static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities, | ||
222 | mask_registers, prio_registers, NULL); | ||
223 | |||
224 | /* Support for external interrupt pins in IRQ mode */ | ||
225 | static struct intc_vect vectors_irq[] __initdata = { | ||
226 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | ||
227 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | ||
228 | }; | ||
229 | |||
230 | static struct intc_sense_reg sense_registers[] __initdata = { | ||
231 | { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | ||
80 | }; | 232 | }; |
81 | 233 | ||
234 | static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups, | ||
235 | priorities, mask_registers, prio_registers, | ||
236 | sense_registers); | ||
237 | |||
238 | /* External interrupt pins in IRL mode */ | ||
239 | static struct intc_vect vectors_irl[] __initdata = { | ||
240 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), | ||
241 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), | ||
242 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), | ||
243 | INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), | ||
244 | INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), | ||
245 | INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), | ||
246 | INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), | ||
247 | INTC_VECT(IRL_HHHL, 0x3c0), | ||
248 | }; | ||
249 | |||
250 | static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, | ||
251 | priorities, mask_registers, prio_registers, NULL); | ||
252 | |||
253 | void __init plat_irq_setup_pins(int mode) | ||
254 | { | ||
255 | switch (mode) { | ||
256 | case IRQ_MODE_IRQ: | ||
257 | register_intc_controller(&intc_desc_irq); | ||
258 | break; | ||
259 | case IRQ_MODE_IRL3210: | ||
260 | register_intc_controller(&intc_desc_irl); | ||
261 | break; | ||
262 | default: | ||
263 | BUG(); | ||
264 | } | ||
265 | } | ||
266 | |||
82 | void __init plat_irq_setup(void) | 267 | void __init plat_irq_setup(void) |
83 | { | 268 | { |
84 | register_intc2_controller(&intc2_irq_desc); | 269 | register_intc_controller(&intc_desc); |
270 | } | ||
271 | |||
272 | void __init plat_mem_setup(void) | ||
273 | { | ||
274 | unsigned int nid = 1; | ||
275 | |||
276 | /* Register CPU#0 URAM space as Node 1 */ | ||
277 | setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */ | ||
278 | |||
279 | #if 0 | ||
280 | /* XXX: Not yet.. */ | ||
281 | setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */ | ||
282 | setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */ | ||
283 | setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */ | ||
284 | #endif | ||
285 | |||
286 | setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */ | ||
85 | } | 287 | } |