aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7724.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index b9e84b1d3aa7..ea5780b3c7f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -36,122 +36,122 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
36 { 36 {
37 .slave_id = SHDMA_SLAVE_SCIF0_TX, 37 .slave_id = SHDMA_SLAVE_SCIF0_TX,
38 .addr = 0xffe0000c, 38 .addr = 0xffe0000c,
39 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
40 .mid_rid = 0x21, 40 .mid_rid = 0x21,
41 }, { 41 }, {
42 .slave_id = SHDMA_SLAVE_SCIF0_RX, 42 .slave_id = SHDMA_SLAVE_SCIF0_RX,
43 .addr = 0xffe00014, 43 .addr = 0xffe00014,
44 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
45 .mid_rid = 0x22, 45 .mid_rid = 0x22,
46 }, { 46 }, {
47 .slave_id = SHDMA_SLAVE_SCIF1_TX, 47 .slave_id = SHDMA_SLAVE_SCIF1_TX,
48 .addr = 0xffe1000c, 48 .addr = 0xffe1000c,
49 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
50 .mid_rid = 0x25, 50 .mid_rid = 0x25,
51 }, { 51 }, {
52 .slave_id = SHDMA_SLAVE_SCIF1_RX, 52 .slave_id = SHDMA_SLAVE_SCIF1_RX,
53 .addr = 0xffe10014, 53 .addr = 0xffe10014,
54 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
55 .mid_rid = 0x26, 55 .mid_rid = 0x26,
56 }, { 56 }, {
57 .slave_id = SHDMA_SLAVE_SCIF2_TX, 57 .slave_id = SHDMA_SLAVE_SCIF2_TX,
58 .addr = 0xffe2000c, 58 .addr = 0xffe2000c,
59 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
60 .mid_rid = 0x29, 60 .mid_rid = 0x29,
61 }, { 61 }, {
62 .slave_id = SHDMA_SLAVE_SCIF2_RX, 62 .slave_id = SHDMA_SLAVE_SCIF2_RX,
63 .addr = 0xffe20014, 63 .addr = 0xffe20014,
64 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 64 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
65 .mid_rid = 0x2a, 65 .mid_rid = 0x2a,
66 }, { 66 }, {
67 .slave_id = SHDMA_SLAVE_SCIF3_TX, 67 .slave_id = SHDMA_SLAVE_SCIF3_TX,
68 .addr = 0xa4e30020, 68 .addr = 0xa4e30020,
69 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 69 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
70 .mid_rid = 0x2d, 70 .mid_rid = 0x2d,
71 }, { 71 }, {
72 .slave_id = SHDMA_SLAVE_SCIF3_RX, 72 .slave_id = SHDMA_SLAVE_SCIF3_RX,
73 .addr = 0xa4e30024, 73 .addr = 0xa4e30024,
74 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 74 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
75 .mid_rid = 0x2e, 75 .mid_rid = 0x2e,
76 }, { 76 }, {
77 .slave_id = SHDMA_SLAVE_SCIF4_TX, 77 .slave_id = SHDMA_SLAVE_SCIF4_TX,
78 .addr = 0xa4e40020, 78 .addr = 0xa4e40020,
79 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 79 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
80 .mid_rid = 0x31, 80 .mid_rid = 0x31,
81 }, { 81 }, {
82 .slave_id = SHDMA_SLAVE_SCIF4_RX, 82 .slave_id = SHDMA_SLAVE_SCIF4_RX,
83 .addr = 0xa4e40024, 83 .addr = 0xa4e40024,
84 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 84 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
85 .mid_rid = 0x32, 85 .mid_rid = 0x32,
86 }, { 86 }, {
87 .slave_id = SHDMA_SLAVE_SCIF5_TX, 87 .slave_id = SHDMA_SLAVE_SCIF5_TX,
88 .addr = 0xa4e50020, 88 .addr = 0xa4e50020,
89 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 89 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
90 .mid_rid = 0x35, 90 .mid_rid = 0x35,
91 }, { 91 }, {
92 .slave_id = SHDMA_SLAVE_SCIF5_RX, 92 .slave_id = SHDMA_SLAVE_SCIF5_RX,
93 .addr = 0xa4e50024, 93 .addr = 0xa4e50024,
94 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 94 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
95 .mid_rid = 0x36, 95 .mid_rid = 0x36,
96 }, { 96 }, {
97 .slave_id = SHDMA_SLAVE_USB0D0_TX, 97 .slave_id = SHDMA_SLAVE_USB0D0_TX,
98 .addr = 0xA4D80100, 98 .addr = 0xA4D80100,
99 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 99 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
100 .mid_rid = 0x73, 100 .mid_rid = 0x73,
101 }, { 101 }, {
102 .slave_id = SHDMA_SLAVE_USB0D0_RX, 102 .slave_id = SHDMA_SLAVE_USB0D0_RX,
103 .addr = 0xA4D80100, 103 .addr = 0xA4D80100,
104 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 104 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
105 .mid_rid = 0x73, 105 .mid_rid = 0x73,
106 }, { 106 }, {
107 .slave_id = SHDMA_SLAVE_USB0D1_TX, 107 .slave_id = SHDMA_SLAVE_USB0D1_TX,
108 .addr = 0xA4D80120, 108 .addr = 0xA4D80120,
109 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 109 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
110 .mid_rid = 0x77, 110 .mid_rid = 0x77,
111 }, { 111 }, {
112 .slave_id = SHDMA_SLAVE_USB0D1_RX, 112 .slave_id = SHDMA_SLAVE_USB0D1_RX,
113 .addr = 0xA4D80120, 113 .addr = 0xA4D80120,
114 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 114 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
115 .mid_rid = 0x77, 115 .mid_rid = 0x77,
116 }, { 116 }, {
117 .slave_id = SHDMA_SLAVE_USB1D0_TX, 117 .slave_id = SHDMA_SLAVE_USB1D0_TX,
118 .addr = 0xA4D90100, 118 .addr = 0xA4D90100,
119 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 119 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
120 .mid_rid = 0xab, 120 .mid_rid = 0xab,
121 }, { 121 }, {
122 .slave_id = SHDMA_SLAVE_USB1D0_RX, 122 .slave_id = SHDMA_SLAVE_USB1D0_RX,
123 .addr = 0xA4D90100, 123 .addr = 0xA4D90100,
124 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 124 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
125 .mid_rid = 0xab, 125 .mid_rid = 0xab,
126 }, { 126 }, {
127 .slave_id = SHDMA_SLAVE_USB1D1_TX, 127 .slave_id = SHDMA_SLAVE_USB1D1_TX,
128 .addr = 0xA4D90120, 128 .addr = 0xA4D90120,
129 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 129 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
130 .mid_rid = 0xaf, 130 .mid_rid = 0xaf,
131 }, { 131 }, {
132 .slave_id = SHDMA_SLAVE_USB1D1_RX, 132 .slave_id = SHDMA_SLAVE_USB1D1_RX,
133 .addr = 0xA4D90120, 133 .addr = 0xA4D90120,
134 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 134 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
135 .mid_rid = 0xaf, 135 .mid_rid = 0xaf,
136 }, { 136 }, {
137 .slave_id = SHDMA_SLAVE_SDHI0_TX, 137 .slave_id = SHDMA_SLAVE_SDHI0_TX,
138 .addr = 0x04ce0030, 138 .addr = 0x04ce0030,
139 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 139 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
140 .mid_rid = 0xc1, 140 .mid_rid = 0xc1,
141 }, { 141 }, {
142 .slave_id = SHDMA_SLAVE_SDHI0_RX, 142 .slave_id = SHDMA_SLAVE_SDHI0_RX,
143 .addr = 0x04ce0030, 143 .addr = 0x04ce0030,
144 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 144 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
145 .mid_rid = 0xc2, 145 .mid_rid = 0xc2,
146 }, { 146 }, {
147 .slave_id = SHDMA_SLAVE_SDHI1_TX, 147 .slave_id = SHDMA_SLAVE_SDHI1_TX,
148 .addr = 0x04cf0030, 148 .addr = 0x04cf0030,
149 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 149 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc9, 150 .mid_rid = 0xc9,
151 }, { 151 }, {
152 .slave_id = SHDMA_SLAVE_SDHI1_RX, 152 .slave_id = SHDMA_SLAVE_SDHI1_RX,
153 .addr = 0x04cf0030, 153 .addr = 0x04cf0030,
154 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 154 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
155 .mid_rid = 0xca, 155 .mid_rid = 0xca,
156 }, 156 },
157}; 157};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 02:43:44 -0500