diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7722.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 57f83a92a505..7aa733307afc 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
@@ -30,62 +30,62 @@ static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { | |||
30 | { | 30 | { |
31 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | 31 | .slave_id = SHDMA_SLAVE_SCIF0_TX, |
32 | .addr = 0xffe0000c, | 32 | .addr = 0xffe0000c, |
33 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 33 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
34 | .mid_rid = 0x21, | 34 | .mid_rid = 0x21, |
35 | }, { | 35 | }, { |
36 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | 36 | .slave_id = SHDMA_SLAVE_SCIF0_RX, |
37 | .addr = 0xffe00014, | 37 | .addr = 0xffe00014, |
38 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 38 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
39 | .mid_rid = 0x22, | 39 | .mid_rid = 0x22, |
40 | }, { | 40 | }, { |
41 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | 41 | .slave_id = SHDMA_SLAVE_SCIF1_TX, |
42 | .addr = 0xffe1000c, | 42 | .addr = 0xffe1000c, |
43 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 43 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
44 | .mid_rid = 0x25, | 44 | .mid_rid = 0x25, |
45 | }, { | 45 | }, { |
46 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | 46 | .slave_id = SHDMA_SLAVE_SCIF1_RX, |
47 | .addr = 0xffe10014, | 47 | .addr = 0xffe10014, |
48 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 48 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
49 | .mid_rid = 0x26, | 49 | .mid_rid = 0x26, |
50 | }, { | 50 | }, { |
51 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | 51 | .slave_id = SHDMA_SLAVE_SCIF2_TX, |
52 | .addr = 0xffe2000c, | 52 | .addr = 0xffe2000c, |
53 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 53 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
54 | .mid_rid = 0x29, | 54 | .mid_rid = 0x29, |
55 | }, { | 55 | }, { |
56 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | 56 | .slave_id = SHDMA_SLAVE_SCIF2_RX, |
57 | .addr = 0xffe20014, | 57 | .addr = 0xffe20014, |
58 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), | 58 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
59 | .mid_rid = 0x2a, | 59 | .mid_rid = 0x2a, |
60 | }, { | 60 | }, { |
61 | .slave_id = SHDMA_SLAVE_SIUA_TX, | 61 | .slave_id = SHDMA_SLAVE_SIUA_TX, |
62 | .addr = 0xa454c098, | 62 | .addr = 0xa454c098, |
63 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 63 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
64 | .mid_rid = 0xb1, | 64 | .mid_rid = 0xb1, |
65 | }, { | 65 | }, { |
66 | .slave_id = SHDMA_SLAVE_SIUA_RX, | 66 | .slave_id = SHDMA_SLAVE_SIUA_RX, |
67 | .addr = 0xa454c090, | 67 | .addr = 0xa454c090, |
68 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 68 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
69 | .mid_rid = 0xb2, | 69 | .mid_rid = 0xb2, |
70 | }, { | 70 | }, { |
71 | .slave_id = SHDMA_SLAVE_SIUB_TX, | 71 | .slave_id = SHDMA_SLAVE_SIUB_TX, |
72 | .addr = 0xa454c09c, | 72 | .addr = 0xa454c09c, |
73 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 73 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
74 | .mid_rid = 0xb5, | 74 | .mid_rid = 0xb5, |
75 | }, { | 75 | }, { |
76 | .slave_id = SHDMA_SLAVE_SIUB_RX, | 76 | .slave_id = SHDMA_SLAVE_SIUB_RX, |
77 | .addr = 0xa454c094, | 77 | .addr = 0xa454c094, |
78 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | 78 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
79 | .mid_rid = 0xb6, | 79 | .mid_rid = 0xb6, |
80 | }, { | 80 | }, { |
81 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | 81 | .slave_id = SHDMA_SLAVE_SDHI0_TX, |
82 | .addr = 0x04ce0030, | 82 | .addr = 0x04ce0030, |
83 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 83 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), |
84 | .mid_rid = 0xc1, | 84 | .mid_rid = 0xc1, |
85 | }, { | 85 | }, { |
86 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | 86 | .slave_id = SHDMA_SLAVE_SDHI0_RX, |
87 | .addr = 0x04ce0030, | 87 | .addr = 0x04ce0030, |
88 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 88 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), |
89 | .mid_rid = 0xc2, | 89 | .mid_rid = 0xc2, |
90 | }, | 90 | }, |
91 | }; | 91 | }; |