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Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7723.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c113
1 files changed, 58 insertions, 55 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index e67c2678b8ae..20a31c2255a8 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -22,6 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clock.h> 24#include <asm/clock.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
25 27
26/* SH7723 registers */ 28/* SH7723 registers */
27#define FRQCR 0xa4150000 29#define FRQCR 0xa4150000
@@ -30,9 +32,6 @@
30#define SCLKBCR 0xa415000c 32#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018 33#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024 34#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 35#define DLLFRQ 0xa4150050
37 36
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -140,60 +139,64 @@ struct clk div6_clks[] = {
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
141}; 140};
142 141
143#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ 142#define R_CLK (&r_clk)
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) 143#define P_CLK (&div4_clks[DIV4_P])
144#define B_CLK (&div4_clks[DIV4_B])
145#define U_CLK (&div4_clks[DIV4_U])
146#define I_CLK (&div4_clks[DIV4_I])
147#define SH_CLK (&div4_clks[DIV4_SH])
145 148
146static struct clk mstp_clks[] = { 149static struct clk mstp_clks[] = {
147 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 150 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
148 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), 151 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
149 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), 152 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
150 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), 153 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
151 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0), 154 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
152 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), 155 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
153 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), 156 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
154 MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0), 157 SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
155 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), 158 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
156 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), 159 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
157 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), 160 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
158 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), 161 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
159 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), 162 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
160 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), 163 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
161 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), 164 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
162 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), 165 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
163 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0), 166 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), 167 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
165 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), 168 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
166 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), 169 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
167 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), 170 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
168 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), 171 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
169 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), 172 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
170 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), 173 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
171 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), 174 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
172 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), 175 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
173 MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0), 176 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
174 177
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), 178 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
176 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0), 179 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
177 180
178 MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0), 181 SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0),
179 MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0), 182 SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0),
180 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), 183 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
181 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), 184 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
182 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), 185 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
183 MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), 186 SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT),
184 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), 187 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
185 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), 188 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
186 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0), 189 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
187 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0), 190 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
188 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1), 191 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
189 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0), 192 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
190 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), 193 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
191 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), 194 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
192 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), 195 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
193 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), 196 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
194 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), 197 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
195 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), 198 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
196 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), 199 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
197}; 200};
198 201
199int __init arch_clk_init(void) 202int __init arch_clk_init(void)
@@ -216,7 +219,7 @@ int __init arch_clk_init(void)
216 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 219 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
217 220
218 if (!ret) 221 if (!ret)
219 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 222 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
220 223
221 return ret; 224 return ret;
222} 225}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 20:49:44 -0500