diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7722.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index ea38b554dc05..15db6d521c5c 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |||
@@ -110,19 +110,22 @@ struct clk *main_clks[] = { | |||
110 | static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; | 110 | static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; |
111 | static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; | 111 | static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; |
112 | 112 | ||
113 | static struct clk_div_mult_table div4_table = { | 113 | static struct clk_div_mult_table div4_div_mult_table = { |
114 | .divisors = divisors, | 114 | .divisors = divisors, |
115 | .nr_divisors = ARRAY_SIZE(divisors), | 115 | .nr_divisors = ARRAY_SIZE(divisors), |
116 | .multipliers = multipliers, | 116 | .multipliers = multipliers, |
117 | .nr_multipliers = ARRAY_SIZE(multipliers), | 117 | .nr_multipliers = ARRAY_SIZE(multipliers), |
118 | }; | 118 | }; |
119 | 119 | ||
120 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, | 120 | static struct clk_div4_table div4_table = { |
121 | DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; | 121 | .div_mult_table = &div4_div_mult_table, |
122 | }; | ||
122 | 123 | ||
123 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 124 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ |
124 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 125 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) |
125 | 126 | ||
127 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; | ||
128 | |||
126 | struct clk div4_clks[DIV4_NR] = { | 129 | struct clk div4_clks[DIV4_NR] = { |
127 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), | 130 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), |
128 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | 131 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), |
@@ -130,9 +133,19 @@ struct clk div4_clks[DIV4_NR] = { | |||
130 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | 133 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), |
131 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | 134 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), |
132 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | 135 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), |
136 | }; | ||
137 | |||
138 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; | ||
139 | |||
140 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { | ||
141 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), | ||
142 | }; | ||
143 | |||
144 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; | ||
145 | |||
146 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { | ||
133 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), | 147 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), |
134 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | 148 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), |
135 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), | ||
136 | }; | 149 | }; |
137 | 150 | ||
138 | struct clk div6_clks[] = { | 151 | struct clk div6_clks[] = { |
@@ -189,6 +202,14 @@ int __init arch_clk_init(void) | |||
189 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | 202 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); |
190 | 203 | ||
191 | if (!ret) | 204 | if (!ret) |
205 | ret = sh_clk_div4_enable_register(div4_enable_clks, | ||
206 | DIV4_ENABLE_NR, &div4_table); | ||
207 | |||
208 | if (!ret) | ||
209 | ret = sh_clk_div4_reparent_register(div4_reparent_clks, | ||
210 | DIV4_REPARENT_NR, &div4_table); | ||
211 | |||
212 | if (!ret) | ||
192 | ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); | 213 | ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); |
193 | 214 | ||
194 | if (!ret) | 215 | if (!ret) |