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Diffstat (limited to 'arch/sh/kernel/cpu/sh3/setup-sh7720.c')
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c35
1 files changed, 2 insertions, 33 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 8028082527c5..f807a21b066c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -19,10 +19,6 @@
19#include <linux/serial_sci.h> 19#include <linux/serial_sci.h>
20#include <asm/rtc.h> 20#include <asm/rtc.h>
21 21
22#define INTC_ICR1 0xA4140010UL
23#define INTC_ICR_IRLM 0x4000
24#define INTC_ICR_IRQ (~INTC_ICR_IRLM)
25
26static struct resource rtc_resources[] = { 22static struct resource rtc_resources[] = {
27 [0] = { 23 [0] = {
28 .start = 0xa413fec0, 24 .start = 0xa413fec0,
@@ -170,6 +166,7 @@ enum {
170}; 166};
171 167
172static struct intc_vect vectors[] __initdata = { 168static struct intc_vect vectors[] __initdata = {
169 /* IRQ0->5 are handled in setup-sh3.c */
173 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 170 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
174 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 171 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480),
175 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), 172 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0),
@@ -214,11 +211,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
214 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 211 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
215 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 212 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
216 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 213 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
217#if defined(CONFIG_CPU_SUBTYPE_SH7720)
218 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 214 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
219#else
220 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
221#endif
222 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 215 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
223 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 216 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
224 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 217 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
@@ -229,32 +222,8 @@ static struct intc_prio_reg prio_registers[] __initdata = {
229static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 222static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
230 NULL, prio_registers, NULL); 223 NULL, prio_registers, NULL);
231 224
232static struct intc_sense_reg sense_registers[] __initdata = {
233 { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
234};
235
236static struct intc_vect vectors_irq[] __initdata = {
237 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
238 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
239 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
240};
241
242static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
243 NULL, NULL, prio_registers, sense_registers);
244
245void __init plat_irq_setup_pins(int mode)
246{
247 switch (mode) {
248 case IRQ_MODE_IRQ:
249 ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
250 register_intc_controller(&intc_irq_desc);
251 break;
252 default:
253 BUG();
254 }
255}
256
257void __init plat_irq_setup(void) 225void __init plat_irq_setup(void)
258{ 226{
259 register_intc_controller(&intc_desc); 227 register_intc_controller(&intc_desc);
228 plat_irq_setup_sh3();
260} 229}