1 files changed, 58 insertions, 4 deletions

diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index cdfeef49e62e..4b60fcc7d667 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -17,22 +17,22 @@ static struct plat_sci_port sci_platform_data[] = {
                 .mapbase        = 0xfffe8000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           =  { 240, 241, 242, 243},
+                .irqs           =  { 241, 242, 243, 240},
         }, {
                 .mapbase        = 0xfffe8800,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           =  { 244, 245, 246, 247},
+                .irqs           =  { 247, 244, 245, 246},
         }, {
                 .mapbase        = 0xfffe9000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           =  { 248, 249, 250, 251},
+                .irqs           =  { 249, 250, 251, 248},
         }, {
                 .mapbase        = 0xfffe9800,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           =  { 252, 253, 254, 255},
+                .irqs           =  { 253, 254, 255, 252},
         }, {
                 .flags = 0,
         }
@@ -56,3 +56,57 @@ static int __init sh7206_devices_setup(void)
                                     ARRAY_SIZE(sh7206_devices));
 }
 __initcall(sh7206_devices_setup);
+
+#define INTC_IPR08     0xfffe0c04UL
+#define INTC_IPR09     0xfffe0c06UL
+#define INTC_IPR14     0xfffe0c10UL
+
+#define CMI0_IRQ       140
+
+#define MTU1_TGI1A     164
+
+#define SCIF0_BRI_IRQ  240
+#define SCIF0_ERI_IRQ  241
+#define SCIF0_RXI_IRQ  242
+#define SCIF0_TXI_IRQ  243
+
+#define SCIF1_BRI_IRQ  244
+#define SCIF1_ERI_IRQ  245
+#define SCIF1_RXI_IRQ  246
+#define SCIF1_TXI_IRQ  247
+
+#define SCIF2_BRI_IRQ  248
+#define SCIF2_ERI_IRQ  249
+#define SCIF2_RXI_IRQ  250
+#define SCIF2_TXI_IRQ  251
+
+#define SCIF3_BRI_IRQ  252
+#define SCIF3_ERI_IRQ  253
+#define SCIF3_RXI_IRQ  254
+#define SCIF3_TXI_IRQ  255
+
+static struct ipr_data sh7206_ipr_map[] = {
+        { CMI0_IRQ,      INTC_IPR08, 3, 2 },
+        { MTU2_TGI1A,    INTC_IPR09, 1, 2 },
+        { SCIF0_ERI_IRQ, INTC_IPR14, 3, 3 },
+        { SCIF0_RXI_IRQ, INTC_IPR14, 3, 3 },
+        { SCIF0_BRI_IRQ, INTC_IPR14, 3, 3 },
+        { SCIF0_TXI_IRQ, INTC_IPR14, 3, 3 },
+        { SCIF1_ERI_IRQ, INTC_IPR14, 2, 3 },
+        { SCIF1_RXI_IRQ, INTC_IPR14, 2, 3 },
+        { SCIF1_BRI_IRQ, INTC_IPR14, 2, 3 },
+        { SCIF1_TXI_IRQ, INTC_IPR14, 2, 3 },
+        { SCIF2_ERI_IRQ, INTC_IPR14, 1, 3 },
+        { SCIF2_RXI_IRQ, INTC_IPR14, 1, 3 },
+        { SCIF2_BRI_IRQ, INTC_IPR14, 1, 3 },
+        { SCIF2_TXI_IRQ, INTC_IPR14, 1, 3 },
+        { SCIF3_ERI_IRQ, INTC_IPR14, 0, 3 },
+        { SCIF3_RXI_IRQ, INTC_IPR14, 0, 3 },
+        { SCIF3_BRI_IRQ, INTC_IPR14, 0, 3 },
+        { SCIF3_TXI_IRQ, INTC_IPR14, 0, 3 },
+};
+
+void __init init_IRQ_ipr(void)
+{
+        make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map));
+}