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-rw-r--r--arch/sh/kernel/cpu/irq/intc.c405
1 files changed, 405 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
new file mode 100644
index 000000000000..9345a7130e9e
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/intc.c
@@ -0,0 +1,405 @@
1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
23
24#define _INTC_MK(fn, idx, bit, value) \
25 ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
26#define _INTC_FN(h) (h >> 24)
27#define _INTC_VALUE(h) ((h >> 16) & 0xff)
28#define _INTC_IDX(h) ((h >> 8) & 0xff)
29#define _INTC_BIT(h) (h & 0xff)
30
31#define _INTC_PTR(desc, member, data) \
32 (desc->member + _INTC_IDX(data))
33
34static inline struct intc_desc *get_intc_desc(unsigned int irq)
35{
36 struct irq_chip *chip = get_irq_chip(irq);
37 return (void *)((char *)chip - offsetof(struct intc_desc, chip));
38}
39
40static inline unsigned int set_field(unsigned int value,
41 unsigned int field_value,
42 unsigned int width,
43 unsigned int shift)
44{
45 value &= ~(((1 << width) - 1) << shift);
46 value |= field_value << shift;
47 return value;
48}
49
50static inline unsigned int set_prio_field(struct intc_desc *desc,
51 unsigned int value,
52 unsigned int priority,
53 unsigned int data)
54{
55 unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
56
57 return set_field(value, priority, width, _INTC_BIT(data));
58}
59
60static void disable_prio_16(struct intc_desc *desc, unsigned int data)
61{
62 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
63
64 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
65}
66
67static void enable_prio_16(struct intc_desc *desc, unsigned int data)
68{
69 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
70 unsigned int prio = _INTC_VALUE(data);
71
72 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
73}
74
75static void disable_prio_32(struct intc_desc *desc, unsigned int data)
76{
77 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
78
79 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
80}
81
82static void enable_prio_32(struct intc_desc *desc, unsigned int data)
83{
84 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
85 unsigned int prio = _INTC_VALUE(data);
86
87 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
88}
89
90static void disable_mask_8(struct intc_desc *desc, unsigned int data)
91{
92 ctrl_outb(1 << _INTC_BIT(data),
93 _INTC_PTR(desc, mask_regs, data)->set_reg);
94}
95
96static void enable_mask_8(struct intc_desc *desc, unsigned int data)
97{
98 ctrl_outb(1 << _INTC_BIT(data),
99 _INTC_PTR(desc, mask_regs, data)->clr_reg);
100}
101
102static void disable_mask_32(struct intc_desc *desc, unsigned int data)
103{
104 ctrl_outl(1 << _INTC_BIT(data),
105 _INTC_PTR(desc, mask_regs, data)->set_reg);
106}
107
108static void enable_mask_32(struct intc_desc *desc, unsigned int data)
109{
110 ctrl_outl(1 << _INTC_BIT(data),
111 _INTC_PTR(desc, mask_regs, data)->clr_reg);
112}
113
114enum { REG_FN_ERROR=0,
115 REG_FN_MASK_8, REG_FN_MASK_32,
116 REG_FN_PRIO_16, REG_FN_PRIO_32 };
117
118static struct {
119 void (*enable)(struct intc_desc *, unsigned int);
120 void (*disable)(struct intc_desc *, unsigned int);
121} intc_reg_fns[] = {
122 [REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 },
123 [REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 },
124 [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
125 [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
126};
127
128static void intc_enable(unsigned int irq)
129{
130 struct intc_desc *desc = get_intc_desc(irq);
131 unsigned int data = (unsigned int) get_irq_chip_data(irq);
132
133 intc_reg_fns[_INTC_FN(data)].enable(desc, data);
134}
135
136static void intc_disable(unsigned int irq)
137{
138 struct intc_desc *desc = get_intc_desc(irq);
139 unsigned int data = (unsigned int) get_irq_chip_data(irq);
140
141 intc_reg_fns[_INTC_FN(data)].disable(desc, data);
142}
143
144static void set_sense_16(struct intc_desc *desc, unsigned int data)
145{
146 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
147 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
148 unsigned int bit = _INTC_BIT(data);
149 unsigned int value = _INTC_VALUE(data);
150
151 ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
152}
153
154static void set_sense_32(struct intc_desc *desc, unsigned int data)
155{
156 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
157 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
158 unsigned int bit = _INTC_BIT(data);
159 unsigned int value = _INTC_VALUE(data);
160
161 ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
162}
163
164#define VALID(x) (x | 0x80)
165
166static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
167 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
168 [IRQ_TYPE_EDGE_RISING] = VALID(1),
169 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
170 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
171};
172
173static int intc_set_sense(unsigned int irq, unsigned int type)
174{
175 struct intc_desc *desc = get_intc_desc(irq);
176 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
177 unsigned int i, j, data, bit;
178 intc_enum enum_id = 0;
179
180 for (i = 0; i < desc->nr_vectors; i++) {
181 struct intc_vect *vect = desc->vectors + i;
182
183 if (evt2irq(vect->vect) != irq)
184 continue;
185
186 enum_id = vect->enum_id;
187 break;
188 }
189
190 if (!enum_id || !value)
191 return -EINVAL;
192
193 value ^= VALID(0);
194
195 for (i = 0; i < desc->nr_sense_regs; i++) {
196 struct intc_sense_reg *sr = desc->sense_regs + i;
197
198 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
199 if (sr->enum_ids[j] != enum_id)
200 continue;
201
202 bit = sr->reg_width - ((j + 1) * sr->field_width);
203 data = _INTC_MK(0, i, bit, value);
204
205 switch(sr->reg_width) {
206 case 16:
207 set_sense_16(desc, data);
208 break;
209 case 32:
210 set_sense_32(desc, data);
211 break;
212 }
213
214 return 0;
215 }
216 }
217
218 return -EINVAL;
219}
220
221static unsigned int __init intc_find_mask_handler(unsigned int width)
222{
223 switch (width) {
224 case 8:
225 return REG_FN_MASK_8;
226 case 32:
227 return REG_FN_MASK_32;
228 }
229
230 BUG();
231 return REG_FN_ERROR;
232}
233
234static unsigned int __init intc_find_prio_handler(unsigned int width)
235{
236 switch (width) {
237 case 16:
238 return REG_FN_PRIO_16;
239 case 32:
240 return REG_FN_PRIO_32;
241 }
242
243 BUG();
244 return REG_FN_ERROR;
245}
246
247static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
248{
249 struct intc_group *g = desc->groups;
250 unsigned int i, j;
251
252 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
253 g = desc->groups + i;
254
255 for (j = 0; g->enum_ids[j]; j++) {
256 if (g->enum_ids[j] != enum_id)
257 continue;
258
259 return g->enum_id;
260 }
261 }
262
263 return 0;
264}
265
266static unsigned int __init intc_prio_value(struct intc_desc *desc,
267 intc_enum enum_id, int do_grps)
268{
269 struct intc_prio *p = desc->priorities;
270 unsigned int i;
271
272 for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
273 p = desc->priorities + i;
274
275 if (p->enum_id != enum_id)
276 continue;
277
278 return p->priority;
279 }
280
281 if (do_grps)
282 return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
283
284 /* default to the lowest priority possible if no priority is set
285 * - this needs to be at least 2 for 5-bit priorities on 7780
286 */
287
288 return 2;
289}
290
291static unsigned int __init intc_mask_data(struct intc_desc *desc,
292 intc_enum enum_id, int do_grps)
293{
294 struct intc_mask_reg *mr = desc->mask_regs;
295 unsigned int i, j, fn;
296
297 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
298 mr = desc->mask_regs + i;
299
300 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
301 if (mr->enum_ids[j] != enum_id)
302 continue;
303
304 fn = intc_find_mask_handler(mr->reg_width);
305 if (fn == REG_FN_ERROR)
306 return 0;
307
308 return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
309 }
310 }
311
312 if (do_grps)
313 return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
314
315 return 0;
316}
317
318static unsigned int __init intc_prio_data(struct intc_desc *desc,
319 intc_enum enum_id, int do_grps)
320{
321 struct intc_prio_reg *pr = desc->prio_regs;
322 unsigned int i, j, fn, bit, prio;
323
324 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
325 pr = desc->prio_regs + i;
326
327 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
328 if (pr->enum_ids[j] != enum_id)
329 continue;
330
331 fn = intc_find_prio_handler(pr->reg_width);
332 if (fn == REG_FN_ERROR)
333 return 0;
334
335 prio = intc_prio_value(desc, enum_id, 1);
336 bit = pr->reg_width - ((j + 1) * pr->field_width);
337
338 BUG_ON(bit < 0);
339
340 return _INTC_MK(fn, i, bit, prio);
341 }
342 }
343
344 if (do_grps)
345 return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
346
347 return 0;
348}
349
350static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
351 unsigned int irq)
352{
353 unsigned int data[2], primary;
354
355 /* Prefer single interrupt source bitmap over other combinations:
356 * 1. bitmap, single interrupt source
357 * 2. priority, single interrupt source
358 * 3. bitmap, multiple interrupt sources (groups)
359 * 4. priority, multiple interrupt sources (groups)
360 */
361
362 data[0] = intc_mask_data(desc, enum_id, 0);
363 data[1] = intc_prio_data(desc, enum_id, 0);
364
365 primary = 0;
366 if (!data[0] && data[1])
367 primary = 1;
368
369 data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
370 data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
371
372 if (!data[primary])
373 primary ^= 1;
374
375 BUG_ON(!data[primary]); /* must have primary masking method */
376
377 disable_irq_nosync(irq);
378 set_irq_chip_and_handler_name(irq, &desc->chip,
379 handle_level_irq, "level");
380 set_irq_chip_data(irq, (void *)data[primary]);
381
382 /* enable secondary masking method if present */
383 if (data[!primary])
384 intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
385 data[!primary]);
386
387 /* irq should be disabled by default */
388 desc->chip.mask(irq);
389}
390
391void __init register_intc_controller(struct intc_desc *desc)
392{
393 unsigned int i;
394
395 desc->chip.mask = intc_disable;
396 desc->chip.unmask = intc_enable;
397 desc->chip.mask_ack = intc_disable;
398 desc->chip.set_type = intc_set_sense;
399
400 for (i = 0; i < desc->nr_vectors; i++) {
401 struct intc_vect *vect = desc->vectors + i;
402
403 intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
404 }
405}
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