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Diffstat (limited to 'arch/sh/kernel/cpu/clock.c')
-rw-r--r--arch/sh/kernel/cpu/clock.c70
1 files changed, 14 insertions, 56 deletions
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 0a7755cc8a25..033f4662b59d 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -30,54 +30,12 @@
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/proc_fs.h> 31#include <linux/proc_fs.h>
32#include <asm/clock.h> 32#include <asm/clock.h>
33#include <asm/machvec.h>
33 34
34static LIST_HEAD(clock_list); 35static LIST_HEAD(clock_list);
35static DEFINE_SPINLOCK(clock_lock); 36static DEFINE_SPINLOCK(clock_lock);
36static DEFINE_MUTEX(clock_list_sem); 37static DEFINE_MUTEX(clock_list_sem);
37 38
38/*
39 * Each subtype is expected to define the init routines for these clocks,
40 * as each subtype (or processor family) will have these clocks at the
41 * very least. These are all provided through the CPG, which even some of
42 * the more quirky parts (such as ST40, SH4-202, etc.) still have.
43 *
44 * The processor-specific code is expected to register any additional
45 * clock sources that are of interest.
46 */
47static struct clk master_clk = {
48 .name = "master_clk",
49 .flags = CLK_ENABLE_ON_INIT,
50 .rate = CONFIG_SH_PCLK_FREQ,
51};
52
53static struct clk peripheral_clk = {
54 .name = "peripheral_clk",
55 .parent = &master_clk,
56 .flags = CLK_ENABLE_ON_INIT,
57};
58
59static struct clk bus_clk = {
60 .name = "bus_clk",
61 .parent = &master_clk,
62 .flags = CLK_ENABLE_ON_INIT,
63};
64
65static struct clk cpu_clk = {
66 .name = "cpu_clk",
67 .parent = &master_clk,
68 .flags = CLK_ENABLE_ON_INIT,
69};
70
71/*
72 * The ordering of these clocks matters, do not change it.
73 */
74static struct clk *onchip_clocks[] = {
75 &master_clk,
76 &peripheral_clk,
77 &bus_clk,
78 &cpu_clk,
79};
80
81/* Used for clocks that always have same value as the parent clock */ 39/* Used for clocks that always have same value as the parent clock */
82unsigned long followparent_recalc(struct clk *clk) 40unsigned long followparent_recalc(struct clk *clk)
83{ 41{
@@ -443,10 +401,6 @@ void clk_put(struct clk *clk)
443} 401}
444EXPORT_SYMBOL_GPL(clk_put); 402EXPORT_SYMBOL_GPL(clk_put);
445 403
446int __init __weak arch_clk_init(void)
447{
448 return 0;
449}
450 404
451static int show_clocks(char *buf, char **start, off_t off, 405static int show_clocks(char *buf, char **start, off_t off,
452 int len, int *eof, void *data) 406 int len, int *eof, void *data)
@@ -533,18 +487,22 @@ subsys_initcall(clk_sysdev_init);
533 487
534int __init clk_init(void) 488int __init clk_init(void)
535{ 489{
536 int i, ret = 0; 490 int ret;
537
538 BUG_ON(!master_clk.rate);
539
540 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
541 struct clk *clk = onchip_clocks[i];
542 491
543 arch_init_clk_ops(&clk->ops, i); 492 ret = arch_clk_init();
544 ret |= clk_register(clk); 493 if (unlikely(ret)) {
494 pr_err("%s: CPU clock registration failed.\n", __func__);
495 return ret;
545 } 496 }
546 497
547 ret |= arch_clk_init(); 498 if (sh_mv.mv_clk_init) {
499 ret = sh_mv.mv_clk_init();
500 if (unlikely(ret)) {
501 pr_err("%s: machvec clock initialization failed.\n",
502 __func__);
503 return ret;
504 }
505 }
548 506
549 /* Kick the child clocks.. */ 507 /* Kick the child clocks.. */
550 recalculate_root_clocks(); 508 recalculate_root_clocks();