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-rw-r--r--arch/sh/include/asm/sizes.h1
-rw-r--r--arch/sh/include/mach-sdk7786/mach/fpga.h17
2 files changed, 17 insertions, 1 deletions
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h
index 3a1fb97770f1..0b9fe2d5c36d 100644
--- a/arch/sh/include/asm/sizes.h
+++ b/arch/sh/include/asm/sizes.h
@@ -32,6 +32,7 @@
32#define SZ_512 0x00000200 32#define SZ_512 0x00000200
33 33
34#define SZ_1K 0x00000400 34#define SZ_1K 0x00000400
35#define SZ_2K 0x00000800
35#define SZ_4K 0x00001000 36#define SZ_4K 0x00001000
36#define SZ_8K 0x00002000 37#define SZ_8K 0x00002000
37#define SZ_16K 0x00004000 38#define SZ_16K 0x00004000
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index b7d93699b679..40f0c2d3690c 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -43,8 +43,23 @@
43 43
44#define FAER 0x150 44#define FAER 0x150
45#define USRGPIR 0x160 45#define USRGPIR 0x160
46
46/* 0x170 reserved */ 47/* 0x170 reserved */
47#define LCLASR 0x180 48
49#define LCLASR 0x180
50#define LCLASR_FRAMEN BIT(15)
51
52#define LCLASR_FPGA_SEL_SHIFT 12
53#define LCLASR_NAND_SEL_SHIFT 8
54#define LCLASR_NORB_SEL_SHIFT 4
55#define LCLASR_NORA_SEL_SHIFT 0
56
57#define LCLASR_AREA_MASK 0x7
58
59#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
60#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
61#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
62#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
48 63
49#define SBCR 0x190 64#define SBCR 0x190
50#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ 65#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */