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-rw-r--r--arch/sh/include/asm/i2c-sh7760.h2
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h6
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h90
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h11
-rw-r--r--arch/sh/include/mach-common/mach/hp6xx.h7
-rw-r--r--arch/sh/include/mach-common/mach/lboxre2.h13
-rw-r--r--arch/sh/include/mach-common/mach/sdk7780.h5
-rw-r--r--arch/sh/include/mach-common/mach/titan.h12
-rw-r--r--arch/sh/include/mach-landisk/mach/iodata_landisk.h19
-rw-r--r--arch/sh/include/mach-se/mach/se.h19
-rw-r--r--arch/sh/include/mach-se/mach/se7343.h9
-rw-r--r--arch/sh/include/mach-se/mach/se7721.h6
-rw-r--r--arch/sh/include/mach-se/mach/se7722.h9
-rw-r--r--arch/sh/include/mach-se/mach/se7724.h7
-rw-r--r--arch/sh/include/mach-se/mach/se7751.h3
-rw-r--r--arch/sh/include/mach-se/mach/se7780.h7
16 files changed, 122 insertions, 103 deletions
diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h
index 24182116711f..69fee1239b03 100644
--- a/arch/sh/include/asm/i2c-sh7760.h
+++ b/arch/sh/include/asm/i2c-sh7760.h
@@ -9,11 +9,9 @@
9 9
10#define SH7760_I2C0_MMIO 0xFE140000 10#define SH7760_I2C0_MMIO 0xFE140000
11#define SH7760_I2C0_MMIOEND 0xFE14003B 11#define SH7760_I2C0_MMIOEND 0xFE14003B
12#define SH7760_I2C0_IRQ 62
13 12
14#define SH7760_I2C1_MMIO 0xFE150000 13#define SH7760_I2C1_MMIO 0xFE150000
15#define SH7760_I2C1_MMIOEND 0xFE15003B 14#define SH7760_I2C1_MMIOEND 0xFE15003B
16#define SH7760_I2C1_IRQ 63
17 15
18struct sh7760_i2c_platdata { 16struct sh7760_i2c_platdata {
19 unsigned int speed_khz; 17 unsigned int speed_khz;
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 24e28b91c9d5..27a90ad0bcec 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4#include <linux/sh_intc.h>
5
4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 7 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 8 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
@@ -10,8 +12,8 @@
10#define SH_DMAC_BASE0 0xa4000020 12#define SH_DMAC_BASE0 0xa4000020
11#endif 13#endif
12 14
13#define DMTE0_IRQ 48 15#define DMTE0_IRQ evt2irq(0x800)
14#define DMTE4_IRQ 76 16#define DMTE4_IRQ evt2irq(0xb80)
15 17
16/* Definitions for the SuperH DMAC */ 18/* Definitions for the SuperH DMAC */
17#define TM_BURST 0x00000020 19#define TM_BURST 0x00000020
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index 9647e681fd27..f280410c93ae 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -1,75 +1,77 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H 1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H 2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3 3
4#include <linux/sh_intc.h>
5
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 6#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7730) 7 defined(CONFIG_CPU_SUBTYPE_SH7730)
6#define DMTE0_IRQ 48 8#define DMTE0_IRQ evt2irq(0x800)
7#define DMTE4_IRQ 76 9#define DMTE4_IRQ evt2irq(0xb80)
8#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 10#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
9#define SH_DMAC_BASE0 0xFE008020 11#define SH_DMAC_BASE0 0xFE008020
10#define SH_DMARS_BASE0 0xFE009000 12#define SH_DMARS_BASE0 0xFE009000
11#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 13#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
12#define DMTE0_IRQ 48 14#define DMTE0_IRQ evt2irq(0x800)
13#define DMTE4_IRQ 76 15#define DMTE4_IRQ evt2irq(0xb80)
14#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 16#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
15#define SH_DMAC_BASE0 0xFE008020 17#define SH_DMAC_BASE0 0xFE008020
16#define SH_DMARS_BASE0 0xFE009000 18#define SH_DMARS_BASE0 0xFE009000
17#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 19#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
18 defined(CONFIG_CPU_SUBTYPE_SH7764) 20 defined(CONFIG_CPU_SUBTYPE_SH7764)
19#define DMTE0_IRQ 34 21#define DMTE0_IRQ evt2irq(0x640)
20#define DMTE4_IRQ 44 22#define DMTE4_IRQ evt2irq(0x780)
21#define DMAE0_IRQ 38 23#define DMAE0_IRQ evt2irq(0x6c0)
22#define SH_DMAC_BASE0 0xFF608020 24#define SH_DMAC_BASE0 0xFF608020
23#define SH_DMARS_BASE0 0xFF609000 25#define SH_DMARS_BASE0 0xFF609000
24#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 26#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
25#define DMTE0_IRQ 48 /* DMAC0A*/ 27#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
26#define DMTE4_IRQ 76 /* DMAC0B */ 28#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
27#define DMTE6_IRQ 40 29#define DMTE6_IRQ evt2irq(0x700)
28#define DMTE8_IRQ 42 /* DMAC1A */ 30#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
29#define DMTE9_IRQ 43 31#define DMTE9_IRQ evt2irq(0x760)
30#define DMTE10_IRQ 72 /* DMAC1B */ 32#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
31#define DMTE11_IRQ 73 33#define DMTE11_IRQ evt2irq(0xb20)
32#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 34#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
33#define DMAE1_IRQ 74 /* DMA Error IRQ*/ 35#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
34#define SH_DMAC_BASE0 0xFE008020 36#define SH_DMAC_BASE0 0xFE008020
35#define SH_DMAC_BASE1 0xFDC08020 37#define SH_DMAC_BASE1 0xFDC08020
36#define SH_DMARS_BASE0 0xFDC09000 38#define SH_DMARS_BASE0 0xFDC09000
37#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 39#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
38#define DMTE0_IRQ 48 /* DMAC0A*/ 40#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
39#define DMTE4_IRQ 76 /* DMAC0B */ 41#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
40#define DMTE6_IRQ 40 42#define DMTE6_IRQ evt2irq(0x700)
41#define DMTE8_IRQ 42 /* DMAC1A */ 43#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
42#define DMTE9_IRQ 43 44#define DMTE9_IRQ evt2irq(0x760)
43#define DMTE10_IRQ 72 /* DMAC1B */ 45#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
44#define DMTE11_IRQ 73 46#define DMTE11_IRQ evt2irq(0xb20)
45#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 47#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
46#define DMAE1_IRQ 74 /* DMA Error IRQ*/ 48#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
47#define SH_DMAC_BASE0 0xFE008020 49#define SH_DMAC_BASE0 0xFE008020
48#define SH_DMAC_BASE1 0xFDC08020 50#define SH_DMAC_BASE1 0xFDC08020
49#define SH_DMARS_BASE0 0xFE009000 51#define SH_DMARS_BASE0 0xFE009000
50#define SH_DMARS_BASE1 0xFDC09000 52#define SH_DMARS_BASE1 0xFDC09000
51#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 53#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
52#define DMTE0_IRQ 34 54#define DMTE0_IRQ evt2irq(0x640)
53#define DMTE4_IRQ 44 55#define DMTE4_IRQ evt2irq(0x780)
54#define DMTE6_IRQ 46 56#define DMTE6_IRQ evt2irq(0x7c0)
55#define DMTE8_IRQ 92 57#define DMTE8_IRQ evt2irq(0xd80)
56#define DMTE9_IRQ 93 58#define DMTE9_IRQ evt2irq(0xda0)
57#define DMTE10_IRQ 94 59#define DMTE10_IRQ evt2irq(0xdc0)
58#define DMTE11_IRQ 95 60#define DMTE11_IRQ evt2irq(0xde0)
59#define DMAE0_IRQ 38 /* DMA Error IRQ */ 61#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
60#define SH_DMAC_BASE0 0xFC808020 62#define SH_DMAC_BASE0 0xFC808020
61#define SH_DMAC_BASE1 0xFC818020 63#define SH_DMAC_BASE1 0xFC818020
62#define SH_DMARS_BASE0 0xFC809000 64#define SH_DMARS_BASE0 0xFC809000
63#else /* SH7785 */ 65#else /* SH7785 */
64#define DMTE0_IRQ 33 66#define DMTE0_IRQ evt2irq(0x620)
65#define DMTE4_IRQ 37 67#define DMTE4_IRQ evt2irq(0x6a0)
66#define DMTE6_IRQ 52 68#define DMTE6_IRQ evt2irq(0x880)
67#define DMTE8_IRQ 54 69#define DMTE8_IRQ evt2irq(0x8c0)
68#define DMTE9_IRQ 55 70#define DMTE9_IRQ evt2irq(0x8e0)
69#define DMTE10_IRQ 56 71#define DMTE10_IRQ evt2irq(0x900)
70#define DMTE11_IRQ 57 72#define DMTE11_IRQ evt2irq(0x920)
71#define DMAE0_IRQ 39 /* DMA Error IRQ0 */ 73#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
72#define DMAE1_IRQ 58 /* DMA Error IRQ1 */ 74#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
73#define SH_DMAC_BASE0 0xFC808020 75#define SH_DMAC_BASE0 0xFC808020
74#define SH_DMAC_BASE1 0xFCC08020 76#define SH_DMAC_BASE1 0xFCC08020
75#define SH_DMARS_BASE0 0xFC809000 77#define SH_DMARS_BASE0 0xFC809000
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index ca747e93c2ed..9d32e2dd2554 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -8,13 +8,16 @@
8#include <cpu/dma-sh4a.h> 8#include <cpu/dma-sh4a.h>
9 9
10#else /* CONFIG_CPU_SH4A */ 10#else /* CONFIG_CPU_SH4A */
11
12#include <linux/sh_intc.h>
13
11/* 14/*
12 * SH7750/SH7751/SH7760 15 * SH7750/SH7751/SH7760
13 */ 16 */
14#define DMTE0_IRQ 34 17#define DMTE0_IRQ evt2irq(0x640)
15#define DMTE4_IRQ 44 18#define DMTE4_IRQ evt2irq(0x780)
16#define DMTE6_IRQ 46 19#define DMTE6_IRQ evt2irq(0x7c0)
17#define DMAE0_IRQ 38 20#define DMAE0_IRQ evt2irq(0x6c0)
18 21
19#define SH_DMAC_BASE0 0xffa00000 22#define SH_DMAC_BASE0 0xffa00000
20#define SH_DMAC_BASE1 0xffa00070 23#define SH_DMAC_BASE1 0xffa00070
diff --git a/arch/sh/include/mach-common/mach/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h
index bcc301ac12f4..6aaaf8596e6a 100644
--- a/arch/sh/include/mach-common/mach/hp6xx.h
+++ b/arch/sh/include/mach-common/mach/hp6xx.h
@@ -9,10 +9,11 @@
9 * for more details. 9 * for more details.
10 * 10 *
11 */ 11 */
12#include <linux/sh_intc.h>
12 13
13#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */ 14#define HP680_BTN_IRQ evt2irq(0x600) /* IRQ0_IRQ */
14#define HP680_TS_IRQ 35 /* IRQ3_IRQ */ 15#define HP680_TS_IRQ evt2irq(0x660) /* IRQ3_IRQ */
15#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */ 16#define HP680_HD64461_IRQ evt2irq(0x680) /* IRQ4_IRQ */
16 17
17#define DAC_LCD_BRIGHTNESS 0 18#define DAC_LCD_BRIGHTNESS 0
18#define DAC_SPEAKER_VOLUME 1 19#define DAC_SPEAKER_VOLUME 1
diff --git a/arch/sh/include/mach-common/mach/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h
index e6d160504923..3a4dcc5c74ee 100644
--- a/arch/sh/include/mach-common/mach/lboxre2.h
+++ b/arch/sh/include/mach-common/mach/lboxre2.h
@@ -11,13 +11,14 @@
11 * for more details. 11 * for more details.
12 * 12 *
13 */ 13 */
14#include <linux/sh_intc.h>
14 15
15#define IRQ_CF1 9 /* CF1 */ 16#define IRQ_CF1 evt2irq(0x320) /* CF1 */
16#define IRQ_CF0 10 /* CF0 */ 17#define IRQ_CF0 evt2irq(0x340) /* CF0 */
17#define IRQ_INTD 11 /* INTD */ 18#define IRQ_INTD evt2irq(0x360) /* INTD */
18#define IRQ_ETH1 12 /* Ether1 */ 19#define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
19#define IRQ_ETH0 13 /* Ether0 */ 20#define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
20#define IRQ_INTA 14 /* INTA */ 21#define IRQ_INTA evt2irq(0x3c0) /* INTA */
21 22
22void init_lboxre2_IRQ(void); 23void init_lboxre2_IRQ(void);
23 24
diff --git a/arch/sh/include/mach-common/mach/sdk7780.h b/arch/sh/include/mach-common/mach/sdk7780.h
index 697dc865f21b..ce64e02e9b50 100644
--- a/arch/sh/include/mach-common/mach/sdk7780.h
+++ b/arch/sh/include/mach-common/mach/sdk7780.h
@@ -11,6 +11,7 @@
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details. 12 * for more details.
13 */ 13 */
14#include <linux/sh_intc.h>
14#include <asm/addrspace.h> 15#include <asm/addrspace.h>
15 16
16/* Box specific addresses. */ 17/* Box specific addresses. */
@@ -67,9 +68,9 @@
67 68
68#define SDK7780_NR_IRL 15 69#define SDK7780_NR_IRL 15
69/* IDE/ATA interrupt */ 70/* IDE/ATA interrupt */
70#define IRQ_CFCARD 14 71#define IRQ_CFCARD evt2irq(0x3c0)
71/* SMC interrupt */ 72/* SMC interrupt */
72#define IRQ_ETHERNET 6 73#define IRQ_ETHERNET evt2irq(0x2c0)
73 74
74 75
75/* arch/sh/boards/renesas/sdk7780/irq.c */ 76/* arch/sh/boards/renesas/sdk7780/irq.c */
diff --git a/arch/sh/include/mach-common/mach/titan.h b/arch/sh/include/mach-common/mach/titan.h
index 4a674d27cbb8..fa3cd801cf2e 100644
--- a/arch/sh/include/mach-common/mach/titan.h
+++ b/arch/sh/include/mach-common/mach/titan.h
@@ -4,14 +4,16 @@
4#ifndef _ASM_SH_TITAN_H 4#ifndef _ASM_SH_TITAN_H
5#define _ASM_SH_TITAN_H 5#define _ASM_SH_TITAN_H
6 6
7#include <linux/sh_intc.h>
8
7#define __IO_PREFIX titan 9#define __IO_PREFIX titan
8#include <asm/io_generic.h> 10#include <asm/io_generic.h>
9 11
10/* IRQ assignments */ 12/* IRQ assignments */
11#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */ 13#define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */
12#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */ 14#define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */
13#define TITAN_IRQ_MPCIA 8 /* mPCI A */ 15#define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */
14#define TITAN_IRQ_MPCIB 11 /* mPCI B */ 16#define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */
15#define TITAN_IRQ_USB 11 /* USB */ 17#define TITAN_IRQ_USB evt2irq(0x360) /* USB */
16 18
17#endif /* __ASM_SH_TITAN_H */ 19#endif /* __ASM_SH_TITAN_H */
diff --git a/arch/sh/include/mach-landisk/mach/iodata_landisk.h b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
index f432773a9571..ceeea48cc7af 100644
--- a/arch/sh/include/mach-landisk/mach/iodata_landisk.h
+++ b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * IO-DATA LANDISK support 9 * IO-DATA LANDISK support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -25,15 +26,15 @@
25#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */ 26#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
26#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */ 27#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
27 28
28#define IRQ_PCIINTA 5 /* PCI INTA IRQ */ 29#define IRQ_PCIINTA evt2irq(0x2a0) /* PCI INTA IRQ */
29#define IRQ_PCIINTB 6 /* PCI INTB IRQ */ 30#define IRQ_PCIINTB evt2irq(0x2c0) /* PCI INTB IRQ */
30#define IRQ_PCIINTC 7 /* PCI INTC IRQ */ 31#define IRQ_PCIINTC evt2irq(0x2e0) /* PCI INTC IRQ */
31#define IRQ_PCIINTD 8 /* PCI INTD IRQ */ 32#define IRQ_PCIINTD evt2irq(0x300) /* PCI INTD IRQ */
32#define IRQ_ATA 9 /* ATA IRQ */ 33#define IRQ_ATA evt2irq(0x320) /* ATA IRQ */
33#define IRQ_FATA 10 /* FATA IRQ */ 34#define IRQ_FATA evt2irq(0x340) /* FATA IRQ */
34#define IRQ_POWER 11 /* Power Switch IRQ */ 35#define IRQ_POWER evt2irq(0x360) /* Power Switch IRQ */
35#define IRQ_BUTTON 12 /* USL-5P Button IRQ */ 36#define IRQ_BUTTON evt2irq(0x380) /* USL-5P Button IRQ */
36#define IRQ_FAULT 13 /* USL-5P Fault IRQ */ 37#define IRQ_FAULT evt2irq(0x3a0) /* USL-5P Fault IRQ */
37 38
38void init_landisk_IRQ(void); 39void init_landisk_IRQ(void);
39 40
diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h
index 14be91c5a2f0..8a6d44b4987b 100644
--- a/arch/sh/include/mach-se/mach/se.h
+++ b/arch/sh/include/mach-se/mach/se.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * Hitachi SolutionEngine support 9 * Hitachi SolutionEngine support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -82,16 +83,16 @@
82#define INTC_IPRD 0xa4000018UL 83#define INTC_IPRD 0xa4000018UL
83#define INTC_IPRE 0xa400001aUL 84#define INTC_IPRE 0xa400001aUL
84 85
85#define IRQ0_IRQ 32 86#define IRQ0_IRQ evt2irq(0x600)
86#define IRQ1_IRQ 33 87#define IRQ1_IRQ evt2irq(0x620)
87#endif 88#endif
88 89
89#if defined(CONFIG_CPU_SUBTYPE_SH7705) 90#if defined(CONFIG_CPU_SUBTYPE_SH7705)
90#define IRQ_STNIC 12 91#define IRQ_STNIC evt2irq(0x380)
91#define IRQ_CFCARD 14 92#define IRQ_CFCARD evt2irq(0x3c0)
92#else 93#else
93#define IRQ_STNIC 10 94#define IRQ_STNIC evt2irq(0x340)
94#define IRQ_CFCARD 7 95#define IRQ_CFCARD evt2irq(0x2e0)
95#endif 96#endif
96 97
97/* SH Ether support (SH7710/SH7712) */ 98/* SH Ether support (SH7710/SH7712) */
@@ -105,9 +106,9 @@
105# define PHY_ID 0x01 106# define PHY_ID 0x01
106#endif 107#endif
107/* Ether IRQ */ 108/* Ether IRQ */
108#define SH_ETH0_IRQ 80 109#define SH_ETH0_IRQ evt2irq(0xc00)
109#define SH_ETH1_IRQ 81 110#define SH_ETH1_IRQ evt2irq(0xc20)
110#define SH_TSU_IRQ 82 111#define SH_TSU_IRQ evt2irq(0xc40)
111 112
112void init_se_IRQ(void); 113void init_se_IRQ(void);
113 114
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
index 8d8170d6cc43..50b5d575dff0 100644
--- a/arch/sh/include/mach-se/mach/se7343.h
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * SH-Mobile SolutionEngine 7343 support 9 * SH-Mobile SolutionEngine 7343 support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -118,10 +119,10 @@
118#define FPGA_IN 0xb1400000 119#define FPGA_IN 0xb1400000
119#define FPGA_OUT 0xb1400002 120#define FPGA_OUT 0xb1400002
120 121
121#define IRQ0_IRQ 32 122#define IRQ0_IRQ evt2irq(0x600)
122#define IRQ1_IRQ 33 123#define IRQ1_IRQ evt2irq(0x620)
123#define IRQ4_IRQ 36 124#define IRQ4_IRQ evt2irq(0x680)
124#define IRQ5_IRQ 37 125#define IRQ5_IRQ evt2irq(0x6a0)
125 126
126#define SE7343_FPGA_IRQ_MRSHPC0 0 127#define SE7343_FPGA_IRQ_MRSHPC0 0
127#define SE7343_FPGA_IRQ_MRSHPC1 1 128#define SE7343_FPGA_IRQ_MRSHPC1 1
diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h
index b957f6041193..eabd0538de44 100644
--- a/arch/sh/include/mach-se/mach/se7721.h
+++ b/arch/sh/include/mach-se/mach/se7721.h
@@ -11,6 +11,8 @@
11 11
12#ifndef __ASM_SH_SE7721_H 12#ifndef __ASM_SH_SE7721_H
13#define __ASM_SH_SE7721_H 13#define __ASM_SH_SE7721_H
14
15#include <linux/sh_intc.h>
14#include <asm/addrspace.h> 16#include <asm/addrspace.h>
15 17
16/* Box specific addresses. */ 18/* Box specific addresses. */
@@ -49,9 +51,9 @@
49#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
50 52
51#define PA_LED 0xB6800000 /* 8bit LED */ 53#define PA_LED 0xB6800000 /* 8bit LED */
52#define PA_FPGA 0xB7000000 /* FPGA base address */ 54#define PA_FPGA 0xB7000000 /* FPGA base address */
53 55
54#define MRSHPC_IRQ0 10 56#define MRSHPC_IRQ0 evt2irq(0x340)
55 57
56#define FPGA_ILSR1 (PA_FPGA + 0x02) 58#define FPGA_ILSR1 (PA_FPGA + 0x02)
57#define FPGA_ILSR2 (PA_FPGA + 0x03) 59#define FPGA_ILSR2 (PA_FPGA + 0x03)
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
index 16505bfb8a9e..201081ebdbce 100644
--- a/arch/sh/include/mach-se/mach/se7722.h
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -13,6 +13,7 @@
13 * for more details. 13 * for more details.
14 * 14 *
15 */ 15 */
16#include <linux/sh_intc.h>
16#include <asm/addrspace.h> 17#include <asm/addrspace.h>
17 18
18/* Box specific addresses. */ 19/* Box specific addresses. */
@@ -31,7 +32,7 @@
31 32
32#define PA_PERIPHERAL 0xB0000000 33#define PA_PERIPHERAL 0xB0000000
33 34
34#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ 35#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
35#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ 36#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
36#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ 37#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
37#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ 38#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
@@ -51,7 +52,7 @@
51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 52#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
52 53
53#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ 54#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
54#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ 55#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
55 56
56#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ 57#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
57/* GPIO */ 58/* GPIO */
@@ -77,8 +78,8 @@
77#define PORT_HIZCRC 0xA405015CUL 78#define PORT_HIZCRC 0xA405015CUL
78 79
79/* IRQ */ 80/* IRQ */
80#define IRQ0_IRQ 32 81#define IRQ0_IRQ evt2irq(0x600)
81#define IRQ1_IRQ 33 82#define IRQ1_IRQ evt2irq(0x620)
82 83
83#define IRQ01_MODE 0xb1800000 84#define IRQ01_MODE 0xb1800000
84#define IRQ01_STS 0xb1800004 85#define IRQ01_STS 0xb1800004
diff --git a/arch/sh/include/mach-se/mach/se7724.h b/arch/sh/include/mach-se/mach/se7724.h
index 29514a39d0f5..be842dd1ca02 100644
--- a/arch/sh/include/mach-se/mach/se7724.h
+++ b/arch/sh/include/mach-se/mach/se7724.h
@@ -18,6 +18,7 @@
18 * for more details. 18 * for more details.
19 * 19 *
20 */ 20 */
21#include <linux/sh_intc.h>
21#include <asm/addrspace.h> 22#include <asm/addrspace.h>
22 23
23/* SH Eth */ 24/* SH Eth */
@@ -35,9 +36,9 @@
35#define IRQ2_MR (0xba200028) 36#define IRQ2_MR (0xba200028)
36 37
37/* IRQ */ 38/* IRQ */
38#define IRQ0_IRQ 32 39#define IRQ0_IRQ evt2irq(0x600)
39#define IRQ1_IRQ 33 40#define IRQ1_IRQ evt2irq(0x620)
40#define IRQ2_IRQ 34 41#define IRQ2_IRQ evt2irq(0x640)
41 42
42/* Bits in IRQ012 registers */ 43/* Bits in IRQ012 registers */
43#define SE7724_FPGA_IRQ_BASE 220 44#define SE7724_FPGA_IRQ_BASE 220
diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h
index b36792ac5d66..271871793d59 100644
--- a/arch/sh/include/mach-se/mach/se7751.h
+++ b/arch/sh/include/mach-se/mach/se7751.h
@@ -11,6 +11,7 @@
11 * Modified for 7751 Solution Engine by 11 * Modified for 7751 Solution Engine by
12 * Ian da Silva and Jeremy Siegel, 2001. 12 * Ian da Silva and Jeremy Siegel, 2001.
13 */ 13 */
14#include <linux/sh_intc.h>
14 15
15/* Box specific addresses. */ 16/* Box specific addresses. */
16 17
@@ -63,7 +64,7 @@
63#define BCR_ILCRF (PA_BCR + 10) 64#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12) 65#define BCR_ILCRG (PA_BCR + 12)
65 66
66#define IRQ_79C973 13 67#define IRQ_79C973 evt2irq(0x3a0)
67 68
68void init_7751se_IRQ(void); 69void init_7751se_IRQ(void);
69 70
diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h
index 40e9b41458cd..bde357cf81bd 100644
--- a/arch/sh/include/mach-se/mach/se7780.h
+++ b/arch/sh/include/mach-se/mach/se7780.h
@@ -12,6 +12,7 @@
12 * License. See the file "COPYING" in the main directory of this archive 12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details. 13 * for more details.
14 */ 14 */
15#include <linux/sh_intc.h>
15#include <asm/addrspace.h> 16#include <asm/addrspace.h>
16 17
17/* Box specific addresses. */ 18/* Box specific addresses. */
@@ -80,13 +81,13 @@
80#define IRQPOS_PCCPW (0 * 4) 81#define IRQPOS_PCCPW (0 * 4)
81 82
82/* IDE interrupt */ 83/* IDE interrupt */
83#define IRQ_IDE0 67 /* iVDR */ 84#define IRQ_IDE0 evt2irq(0xa60) /* iVDR */
84 85
85/* SMC interrupt */ 86/* SMC interrupt */
86#define SMC_IRQ 8 87#define SMC_IRQ evt2irq(0x300)
87 88
88/* SM501 interrupt */ 89/* SM501 interrupt */
89#define SM501_IRQ 0 90#define SM501_IRQ evt2irq(0x200)
90 91
91/* interrupt pin */ 92/* interrupt pin */
92#define IRQPIN_EXTINT1 0 /* IRQ0 pin */ 93#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 21:18:23 -0500