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-rw-r--r--arch/sh/include/mach-common/mach/edosk7705.h30
-rw-r--r--arch/sh/include/mach-common/mach/highlander.h198
-rw-r--r--arch/sh/include/mach-common/mach/hp6xx.h58
-rw-r--r--arch/sh/include/mach-common/mach/lboxre2.h27
-rw-r--r--arch/sh/include/mach-common/mach/magicpanelr2.h67
-rw-r--r--arch/sh/include/mach-common/mach/microdev.h80
-rw-r--r--arch/sh/include/mach-common/mach/migor.h64
-rw-r--r--arch/sh/include/mach-common/mach/r2d.h70
-rw-r--r--arch/sh/include/mach-common/mach/sdk7780.h81
-rw-r--r--arch/sh/include/mach-common/mach/sh7763rdp.h54
-rw-r--r--arch/sh/include/mach-common/mach/sh7785lcr.h55
-rw-r--r--arch/sh/include/mach-common/mach/shmin.h9
-rw-r--r--arch/sh/include/mach-common/mach/snapgear.h71
-rw-r--r--arch/sh/include/mach-common/mach/systemh7751.h71
-rw-r--r--arch/sh/include/mach-common/mach/titan.h17
15 files changed, 952 insertions, 0 deletions
diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
new file mode 100644
index 000000000000..5bdc9d9be3de
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/edosk7705.h
@@ -0,0 +1,30 @@
1/*
2 * include/asm-sh/edosk7705.h
3 *
4 * Modified version of io_se.h for the EDOSK7705 specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Hitachi EDOSK7705 development board
10 */
11
12#ifndef __ASM_SH_EDOSK7705_IO_H
13#define __ASM_SH_EDOSK7705_IO_H
14
15#include <asm/io_generic.h>
16
17extern unsigned char sh_edosk7705_inb(unsigned long port);
18extern unsigned int sh_edosk7705_inl(unsigned long port);
19
20extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
21extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
22
23extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
24extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
25extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
26extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
27
28extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
29
30#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h
new file mode 100644
index 000000000000..306f7359f7d4
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/highlander.h
@@ -0,0 +1,198 @@
1#ifndef __ASM_SH_RENESAS_R7780RP_H
2#define __ASM_SH_RENESAS_R7780RP_H
3
4/* Box specific addresses. */
5#if defined(CONFIG_SH_R7780MP)
6#define PA_BCR 0xa4000000 /* FPGA */
7#define PA_SDPOW (-1)
8
9#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
10#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
11#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
12#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
13#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
14#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
15#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
16#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
17#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
18#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
19#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
20#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
21#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
22#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
23#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
24#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
25#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
26#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
27#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
28#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
29#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
30#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
31#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
32#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
33#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
34#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
35#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
36#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
37#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
38#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
39#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
40#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
41#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
42#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
43#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
44#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
45#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
46#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
47#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
48#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
49#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
50#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
51#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
52#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
53#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
54#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
55#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
56#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
57#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
58#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
59#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
60#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
61#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
62#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
63#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
64#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
65#define PA_PMR (PA_BCR+0x0900) /* */
66
67#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
68#define IVDR_CK_ON 8 /* iVDR Clock ON */
69
70#elif defined(CONFIG_SH_R7780RP)
71#define PA_POFF (-1)
72
73#define PA_BCR 0xa5000000 /* FPGA */
74#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
75#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
76#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
77#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
78#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
79#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
80#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
81#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
82#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
83#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
84#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
85#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
86#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
87#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
88#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
89#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
90#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
91#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
92#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
93#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
94#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
95#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
96#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
97#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
98#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
99#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
100#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
101#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
102#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
103#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
104#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
105#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
106#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
107#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
108#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
109#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
110#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
111#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
112#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
113#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
114#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
115#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
116
117#define PA_AX88796L 0xa5800400 /* AX88796L Area */
118#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
119#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
120#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
121
122#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
123
124#define IVDR_CK_ON 8 /* iVDR Clock ON */
125
126#elif defined(CONFIG_SH_R7785RP)
127#define PA_BCR 0xa4000000 /* FPGA */
128#define PA_SDPOW (-1)
129
130#define PA_PCISCR (PA_BCR+0x0000)
131#define PA_IRLPRA (PA_BCR+0x0002)
132#define PA_IRLPRB (PA_BCR+0x0004)
133#define PA_IRLPRC (PA_BCR+0x0006)
134#define PA_IRLPRD (PA_BCR+0x0008)
135#define IRLCNTR1 (PA_BCR+0x0010)
136#define PA_IRLPRE (PA_BCR+0x000a)
137#define PA_IRLPRF (PA_BCR+0x000c)
138#define PA_EXIRLCR (PA_BCR+0x000e)
139#define PA_IRLMCR1 (PA_BCR+0x0010)
140#define PA_IRLMCR2 (PA_BCR+0x0012)
141#define PA_IRLSSR1 (PA_BCR+0x0014)
142#define PA_IRLSSR2 (PA_BCR+0x0016)
143#define PA_CFTCR (PA_BCR+0x0100)
144#define PA_CFPCR (PA_BCR+0x0102)
145#define PA_PCICR (PA_BCR+0x0110)
146#define PA_IVDRCTL (PA_BCR+0x0112)
147#define PA_IVDRSR (PA_BCR+0x0114)
148#define PA_PDRSTCR (PA_BCR+0x0116)
149#define PA_POFF (PA_BCR+0x0120)
150#define PA_LCDCR (PA_BCR+0x0130)
151#define PA_TPCR (PA_BCR+0x0140)
152#define PA_TPCKCR (PA_BCR+0x0142)
153#define PA_TPRSTR (PA_BCR+0x0144)
154#define PA_TPXPDR (PA_BCR+0x0146)
155#define PA_TPYPDR (PA_BCR+0x0148)
156#define PA_GPIOPFR (PA_BCR+0x0150)
157#define PA_GPIODR (PA_BCR+0x0152)
158#define PA_OBLED (PA_BCR+0x0154)
159#define PA_SWSR (PA_BCR+0x0156)
160#define PA_VERREG (PA_BCR+0x0158)
161#define PA_SMCR (PA_BCR+0x0200)
162#define PA_SMSMADR (PA_BCR+0x0202)
163#define PA_SMMR (PA_BCR+0x0204)
164#define PA_SMSADR1 (PA_BCR+0x0206)
165#define PA_SMSADR32 (PA_BCR+0x0244)
166#define PA_SMTRDR1 (PA_BCR+0x0246)
167#define PA_SMTRDR16 (PA_BCR+0x0264)
168#define PA_CU3MDR (PA_BCR+0x0300)
169#define PA_CU5MDR (PA_BCR+0x0302)
170#define PA_MMSR (PA_BCR+0x0400)
171
172#define IVDR_CK_ON 4 /* iVDR Clock ON */
173#endif
174
175#define HL_FPGA_IRQ_BASE 200
176#define HL_NR_IRL 15
177
178#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0)
179#define IRQ_CF (HL_FPGA_IRQ_BASE + 1)
180#define IRQ_PSW (HL_FPGA_IRQ_BASE + 2)
181#define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3)
182#define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4)
183#define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5)
184#define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6)
185#define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7)
186#define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8)
187#define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9)
188#define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10)
189#define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11)
190#define IRQ_TP (HL_FPGA_IRQ_BASE + 12)
191#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13)
192#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14)
193#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
194#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
195
196unsigned char *highlander_plat_irq_setup(void);
197
198#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/arch/sh/include/mach-common/mach/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h
new file mode 100644
index 000000000000..0d4165a32dcd
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/hp6xx.h
@@ -0,0 +1,58 @@
1#ifndef __ASM_SH_HP6XX_H
2#define __ASM_SH_HP6XX_H
3
4/*
5 * Copyright (C) 2003, 2004, 2005 Andriy Skulysh
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 */
12
13#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */
14#define HP680_TS_IRQ 35 /* IRQ3_IRQ */
15#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */
16
17#define DAC_LCD_BRIGHTNESS 0
18#define DAC_SPEAKER_VOLUME 1
19
20#define PGDR_OPENED 0x01
21#define PGDR_MAIN_BATTERY_OUT 0x04
22#define PGDR_PLAY_BUTTON 0x08
23#define PGDR_REWIND_BUTTON 0x10
24#define PGDR_RECORD_BUTTON 0x20
25
26#define PHDR_TS_PEN_DOWN 0x08
27
28#define PJDR_LED_BLINK 0x02
29
30#define PKDR_LED_GREEN 0x10
31
32#define SCPDR_TS_SCAN_ENABLE 0x20
33#define SCPDR_TS_SCAN_Y 0x02
34#define SCPDR_TS_SCAN_X 0x01
35
36#define SCPCR_TS_ENABLE 0x405
37#define SCPCR_TS_MASK 0xc0f
38
39#define ADC_CHANNEL_TS_Y 1
40#define ADC_CHANNEL_TS_X 2
41#define ADC_CHANNEL_BATTERY 3
42#define ADC_CHANNEL_BACKUP 4
43#define ADC_CHANNEL_CHARGE 5
44
45#define HD64461_GPADR_SPEAKER 0x01
46#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
47
48#define HD64461_GPBDR_LCDOFF 0x01
49#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
50#define HD64461_GPBDR_LED_RED 0x80
51
52#include <asm/hd64461.h>
53#include <asm/io.h>
54
55#define PJDR 0xa4000130
56#define PKDR 0xa4000132
57
58#endif /* __ASM_SH_HP6XX_H */
diff --git a/arch/sh/include/mach-common/mach/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h
new file mode 100644
index 000000000000..e6d160504923
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/lboxre2.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_SH_LBOXRE2_H
2#define __ASM_SH_LBOXRE2_H
3
4/*
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 *
7 * NTT COMWARE L-BOX RE2 support
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 */
14
15#define IRQ_CF1 9 /* CF1 */
16#define IRQ_CF0 10 /* CF0 */
17#define IRQ_INTD 11 /* INTD */
18#define IRQ_ETH1 12 /* Ether1 */
19#define IRQ_ETH0 13 /* Ether0 */
20#define IRQ_INTA 14 /* INTA */
21
22void init_lboxre2_IRQ(void);
23
24#define __IO_PREFIX lboxre2
25#include <asm/io_generic.h>
26
27#endif /* __ASM_SH_LBOXRE2_H */
diff --git a/arch/sh/include/mach-common/mach/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h
new file mode 100644
index 000000000000..c644a77ee357
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/magicpanelr2.h
@@ -0,0 +1,67 @@
1/*
2 * include/asm-sh/magicpanelr2.h
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * I/O addresses and bitmasks for Magic Panel Release 2 board
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef __ASM_SH_MAGICPANELR2_H
14#define __ASM_SH_MAGICPANELR2_H
15
16#include <asm/gpio.h>
17
18#define __IO_PREFIX mpr2
19#include <asm/io_generic.h>
20
21
22#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg)
23#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg)
24#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg)
25#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg)
26#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg)
27#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg)
28
29
30#define PA_LED PORT_PADR /* LED */
31
32
33/* BSC */
34#define CMNCR 0xA4FD0000UL
35#define CS0BCR 0xA4FD0004UL
36#define CS2BCR 0xA4FD0008UL
37#define CS3BCR 0xA4FD000CUL
38#define CS4BCR 0xA4FD0010UL
39#define CS5ABCR 0xA4FD0014UL
40#define CS5BBCR 0xA4FD0018UL
41#define CS6ABCR 0xA4FD001CUL
42#define CS6BBCR 0xA4FD0020UL
43#define CS0WCR 0xA4FD0024UL
44#define CS2WCR 0xA4FD0028UL
45#define CS3WCR 0xA4FD002CUL
46#define CS4WCR 0xA4FD0030UL
47#define CS5AWCR 0xA4FD0034UL
48#define CS5BWCR 0xA4FD0038UL
49#define CS6AWCR 0xA4FD003CUL
50#define CS6BWCR 0xA4FD0040UL
51
52
53/* usb */
54
55#define PORT_UTRCTL 0xA405012CUL
56#define PORT_UCLKCR_W 0xA40A0008UL
57
58#define INTC_ICR0 0xA414FEE0UL
59#define INTC_ICR1 0xA4140010UL
60#define INTC_ICR2 0xA4140012UL
61
62/* MTD */
63
64#define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL
65#define MPR2_MTD_KERNEL_SIZE 0x00200000UL
66
67#endif /* __ASM_SH_MAGICPANELR2_H */
diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
new file mode 100644
index 000000000000..1aed15856e11
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/microdev.h
@@ -0,0 +1,80 @@
1/*
2 * linux/include/asm-sh/microdev.h
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 *
6 * Definitions for the SuperH SH4-202 MicroDev board.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#ifndef __ASM_SH_MICRODEV_H
12#define __ASM_SH_MICRODEV_H
13
14extern void init_microdev_irq(void);
15extern void microdev_print_fpga_intc_status(void);
16
17/*
18 * The following are useful macros for manipulating the interrupt
19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
21 * these are two different things, both of which need to be prorammed to
22 * correctly route - unfortunately, they have the same name and
23 * abbreviations!
24 */
25#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
29#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
30#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
31#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
32#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
33#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
34
35
36/*
37 * The following are the IRQ numbers for the Linux Kernel for external
38 * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'.
39 */
40#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
41#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */
42#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */
43#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
44#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */
45#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
46#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */
47#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */
48
49/*
50 * The following are the IRQ numbers for the INTC on the FPGA for
51 * external interrupts. i.e. the bits in the INTC registers in the
52 * FPGA.
53 */
54#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
55#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */
56#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
57#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
58#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */
59#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */
60#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */
61#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */
62
63#define MICRODEV_IRQ_PCI_INTA 8
64#define MICRODEV_IRQ_PCI_INTB 9
65#define MICRODEV_IRQ_PCI_INTC 10
66#define MICRODEV_IRQ_PCI_INTD 11
67
68#define __IO_PREFIX microdev
69#include <asm/io_generic.h>
70
71#if defined(CONFIG_PCI)
72unsigned char microdev_pci_inb(unsigned long port);
73unsigned short microdev_pci_inw(unsigned long port);
74unsigned long microdev_pci_inl(unsigned long port);
75void microdev_pci_outb(unsigned char data, unsigned long port);
76void microdev_pci_outw(unsigned short data, unsigned long port);
77void microdev_pci_outl(unsigned long data, unsigned long port);
78#endif
79
80#endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/mach-common/mach/migor.h b/arch/sh/include/mach-common/mach/migor.h
new file mode 100644
index 000000000000..e451f0229e00
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/migor.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_SH_MIGOR_H
2#define __ASM_SH_MIGOR_H
3
4/*
5 * linux/include/asm-sh/migor.h
6 *
7 * Copyright (C) 2008 Renesas Solutions
8 *
9 * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16#include <asm/addrspace.h>
17
18/* GPIO */
19#define PORT_PACR 0xa4050100
20#define PORT_PDCR 0xa4050106
21#define PORT_PECR 0xa4050108
22#define PORT_PHCR 0xa405010e
23#define PORT_PJCR 0xa4050110
24#define PORT_PKCR 0xa4050112
25#define PORT_PLCR 0xa4050114
26#define PORT_PMCR 0xa4050116
27#define PORT_PRCR 0xa405011c
28#define PORT_PTCR 0xa4050140
29#define PORT_PUCR 0xa4050142
30#define PORT_PVCR 0xa4050144
31#define PORT_PWCR 0xa4050146
32#define PORT_PXCR 0xa4050148
33#define PORT_PYCR 0xa405014a
34#define PORT_PZCR 0xa405014c
35#define PORT_PADR 0xa4050120
36#define PORT_PHDR 0xa405012e
37#define PORT_PTDR 0xa4050160
38#define PORT_PWDR 0xa4050166
39
40#define PORT_HIZCRA 0xa4050158
41#define PORT_HIZCRC 0xa405015c
42
43#define PORT_MSELCRB 0xa4050182
44
45#define PORT_PSELA 0xa405014e
46#define PORT_PSELB 0xa4050150
47#define PORT_PSELC 0xa4050152
48#define PORT_PSELD 0xa4050154
49#define PORT_PSELE 0xa4050156
50
51#define PORT_HIZCRA 0xa4050158
52#define PORT_HIZCRB 0xa405015a
53#define PORT_HIZCRC 0xa405015c
54
55#define BSC_CS4BCR 0xfec10010
56#define BSC_CS6ABCR 0xfec1001c
57#define BSC_CS4WCR 0xfec10030
58
59#include <video/sh_mobile_lcdc.h>
60
61int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
62 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
63
64#endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/include/mach-common/mach/r2d.h b/arch/sh/include/mach-common/mach/r2d.h
new file mode 100644
index 000000000000..0a800157b826
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/r2d.h
@@ -0,0 +1,70 @@
1#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
2#define __ASM_SH_RENESAS_RTS7751R2D_H
3
4/*
5 * linux/include/asm-sh/renesas_rts7751r2d.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Technology Sales RTS7751R2D support
10 */
11
12/* Board specific addresses. */
13
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
16#define PA_CFCTL 0xa4000004 /* CF Timing control */
17#define PA_CFPOW 0xa4000006 /* CF Power control */
18#define PA_DISPCTL 0xa4000008 /* Display Timing control */
19#define PA_SDMPOW 0xa400000a /* SD Power control */
20#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
21#define PA_PCICD 0xa400000e /* PCI Extention detect control */
22#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
23
24#define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
25#define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
26#define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */
27#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */
28#define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
29
30#define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */
31#define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */
32#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */
33#define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
34#define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
35
36#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
37#define PA_VERREG 0xa4000032 /* FPGA Version Register */
38#define PA_INPORT 0xa4000034 /* KEY Input Port control */
39#define PA_OUTPORT 0xa4000036 /* LED control */
40#define PA_BVERREG 0xa4000038 /* Board Revision Register */
41
42#define PA_AX88796L 0xaa000400 /* AX88796L Area */
43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
44#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
45#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
46
47#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
48
49#define R2D_FPGA_IRQ_BASE 100
50
51#define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0)
52#define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1)
53#define IRQ_TP (R2D_FPGA_IRQ_BASE + 2)
54#define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3)
55#define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4)
56#define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5)
57#define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6)
58#define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7)
59#define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8)
60#define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9)
61#define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10)
62#define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11)
63#define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12)
64#define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13)
65
66/* arch/sh/boards/renesas/rts7751r2d/irq.c */
67void init_rts7751r2d_IRQ(void);
68int rts7751r2d_irq_demux(int);
69
70#endif /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/arch/sh/include/mach-common/mach/sdk7780.h b/arch/sh/include/mach-common/mach/sdk7780.h
new file mode 100644
index 000000000000..697dc865f21b
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sdk7780.h
@@ -0,0 +1,81 @@
1#ifndef __ASM_SH_RENESAS_SDK7780_H
2#define __ASM_SH_RENESAS_SDK7780_H
3
4/*
5 * linux/include/asm-sh/sdk7780.h
6 *
7 * Renesas Solutions SH7780 SDK Support
8 * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <asm/addrspace.h>
15
16/* Box specific addresses. */
17#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
18#define PA_ROM 0xa0000000 /* EPROM */
19#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
20#define PA_FROM 0xa0800000 /* Flash-ROM */
21#define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
22#define PA_EXT1 0xa4000000
23#define PA_EXT1_SIZE 0x04000000
24#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
25#define PA_SDRAM_SIZE 0x08000000
26
27#define PA_EXT4 0xb0000000
28#define PA_EXT4_SIZE 0x04000000
29#define PA_EXT_USER PA_EXT4 /* User Expansion Space */
30
31#define PA_PERIPHERAL PA_AREA5_IO
32
33/* SRAM/Reserved */
34#define PA_RESERVED (PA_PERIPHERAL + 0)
35/* FPGA base address */
36#define PA_FPGA (PA_PERIPHERAL + 0x01000000)
37/* SMC LAN91C111 */
38#define PA_LAN (PA_PERIPHERAL + 0x01800000)
39
40
41#define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
42#define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
43#define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
44#define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
45#define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
46#define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
47#define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
48#define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
49#define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */
50#define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */
51#define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */
52#define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */
53#define PA_LED FPGA_SLEDR
54#define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */
55#define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
56#define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
57#define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
58#define FPGA_EASR (PA_FPGA + 0x110) /* External area select */
59#define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */
60#define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */
61#define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */
62#define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */
63#define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */
64#define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */
65#define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */
66
67
68#define SDK7780_NR_IRL 15
69/* IDE/ATA interrupt */
70#define IRQ_CFCARD 14
71/* SMC interrupt */
72#define IRQ_ETHERNET 6
73
74
75/* arch/sh/boards/renesas/sdk7780/irq.c */
76void init_sdk7780_IRQ(void);
77
78#define __IO_PREFIX sdk7780
79#include <asm/io_generic.h>
80
81#endif /* __ASM_SH_RENESAS_SDK7780_H */
diff --git a/arch/sh/include/mach-common/mach/sh7763rdp.h b/arch/sh/include/mach-common/mach/sh7763rdp.h
new file mode 100644
index 000000000000..8750cc852977
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh7763rdp.h
@@ -0,0 +1,54 @@
1#ifndef __ASM_SH_SH7763RDP_H
2#define __ASM_SH_SH7763RDP_H
3
4/*
5 * linux/include/asm-sh/sh7763drp.h
6 *
7 * Copyright (C) 2008 Renesas Solutions
8 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 *
14 */
15#include <asm/addrspace.h>
16
17/* clock control */
18#define MSTPCR1 0xFFC80038
19
20/* PORT */
21#define PORT_PSEL0 0xFFEF0070
22#define PORT_PSEL1 0xFFEF0072
23#define PORT_PSEL2 0xFFEF0074
24#define PORT_PSEL3 0xFFEF0076
25#define PORT_PSEL4 0xFFEF0078
26
27#define PORT_PACR 0xFFEF0000
28#define PORT_PCCR 0xFFEF0004
29#define PORT_PFCR 0xFFEF000A
30#define PORT_PGCR 0xFFEF000C
31#define PORT_PHCR 0xFFEF000E
32#define PORT_PICR 0xFFEF0010
33#define PORT_PJCR 0xFFEF0012
34#define PORT_PKCR 0xFFEF0014
35#define PORT_PLCR 0xFFEF0016
36#define PORT_PMCR 0xFFEF0018
37#define PORT_PNCR 0xFFEF001A
38
39/* FPGA */
40#define CPLD_BOARD_ID_ERV_REG 0xB1000000
41#define CPLD_CPLD_CMD_REG 0xB1000006
42
43/*
44 * USB SH7763RDP board can use Host only.
45 */
46#define USB_USBHSC 0xFFEC80f0
47
48/* arch/sh/boards/renesas/sh7763rdp/irq.c */
49void init_sh7763rdp_IRQ(void);
50int sh7763rdp_irq_demux(int irq);
51#define __IO_PREFIX sh7763rdp
52#include <asm/io_generic.h>
53
54#endif /* __ASM_SH_SH7763RDP_H */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
new file mode 100644
index 000000000000..1ce27d5c7491
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -0,0 +1,55 @@
1#ifndef __ASM_SH_RENESAS_SH7785LCR_H
2#define __ASM_SH_RENESAS_SH7785LCR_H
3
4/*
5 * This board has 2 physical memory maps.
6 * It can be changed with DIP switch(S2-5).
7 *
8 * phys address | S2-5 = OFF | S2-5 = ON
9 * -----------------------------+---------------+---------------
10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
12 * 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
16 * 0x14000000 - 0x17ffffff(CS5) | I2C | USB
17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
19 *
20 */
21
22#define NOR_FLASH_ADDR 0x00000000
23#define NOR_FLASH_SIZE 0x04000000
24
25#define PLD_BASE_ADDR 0x04000000
26#define PLD_PCICR (PLD_BASE_ADDR + 0x00)
27#define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02)
28#define PLD_LOCALCR (PLD_BASE_ADDR + 0x04)
29#define PLD_POFCR (PLD_BASE_ADDR + 0x06)
30#define PLD_LEDCR (PLD_BASE_ADDR + 0x08)
31#define PLD_SWSR (PLD_BASE_ADDR + 0x0a)
32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
34
35#define SM107_MEM_ADDR 0x10000000
36#define SM107_MEM_SIZE 0x00e00000
37#define SM107_REG_ADDR 0x13e00000
38#define SM107_REG_SIZE 0x00200000
39
40#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
41#define R8A66597_ADDR 0x14000000 /* USB */
42#define CG200_ADDR 0x18000000 /* SD */
43#define PCA9564_ADDR 0x06000000 /* I2C */
44#else
45#define R8A66597_ADDR 0x08000000
46#define CG200_ADDR 0x0c000000
47#define PCA9564_ADDR 0x14000000
48#endif
49
50#define R8A66597_SIZE 0x00000100
51#define CG200_SIZE 0x00010000
52#define PCA9564_SIZE 0x00000100
53
54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */
55
diff --git a/arch/sh/include/mach-common/mach/shmin.h b/arch/sh/include/mach-common/mach/shmin.h
new file mode 100644
index 000000000000..36ba138a81fb
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/shmin.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SH_SHMIN_H
2#define __ASM_SH_SHMIN_H
3
4#define SHMIN_IO_BASE 0xb0000000UL
5
6#define SHMIN_NE_IRQ IRQ2_IRQ
7#define SHMIN_NE_BASE 0x300
8
9#endif
diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/snapgear.h
new file mode 100644
index 000000000000..042d95f51c4d
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/snapgear.h
@@ -0,0 +1,71 @@
1/*
2 * include/asm-sh/snapgear.h
3 *
4 * Modified version of io_se.h for the snapgear-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for a SnapGear
10 */
11
12#ifndef _ASM_SH_IO_SNAPGEAR_H
13#define _ASM_SH_IO_SNAPGEAR_H
14
15#if defined(CONFIG_CPU_SH4)
16/*
17 * The external interrupt lines, these take up ints 0 - 15 inclusive
18 * depending on the priority for the interrupt. In fact the priority
19 * is the interrupt :-)
20 */
21
22#define IRL0_IRQ 2
23#define IRL0_PRIORITY 13
24
25#define IRL1_IRQ 5
26#define IRL1_PRIORITY 10
27
28#define IRL2_IRQ 8
29#define IRL2_PRIORITY 7
30
31#define IRL3_IRQ 11
32#define IRL3_PRIORITY 4
33#endif
34
35#define __IO_PREFIX snapgear
36#include <asm/io_generic.h>
37
38#ifdef CONFIG_SH_SECUREEDGE5410
39/*
40 * We need to remember what was written to the ioport as some bits
41 * are shared with other functions and you cannot read back what was
42 * written :-|
43 *
44 * Bit Read Write
45 * -----------------------------------------------
46 * D0 DCD on ttySC1 power
47 * D1 Reset Switch heatbeat
48 * D2 ttySC0 CTS (7100) LAN
49 * D3 - WAN
50 * D4 ttySC0 DCD (7100) CONSOLE
51 * D5 - ONLINE
52 * D6 - VPN
53 * D7 - DTR on ttySC1
54 * D8 - ttySC0 RTS (7100)
55 * D9 - ttySC0 DTR (7100)
56 * D10 - RTC SCLK
57 * D11 RTC DATA RTC DATA
58 * D12 - RTS RESET
59 */
60
61#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
62extern unsigned short secureedge5410_ioport;
63
64#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
65 (secureedge5410_ioport = \
66 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
67#define SECUREEDGE_READ_IOPORT() \
68 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
69#endif
70
71#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
new file mode 100644
index 000000000000..4161122c84ef
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/systemh7751.h
@@ -0,0 +1,71 @@
1#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
2#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
3
4/*
5 * linux/include/asm-sh/systemh/7751systemh.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SystemH support
10
11 * Modified for 7751 SystemH by
12 * Jonathan Short, 2002.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68#define __IO_PREFIX sh7751systemh
69#include <asm/io_generic.h>
70
71#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/include/mach-common/mach/titan.h b/arch/sh/include/mach-common/mach/titan.h
new file mode 100644
index 000000000000..03f3583c8918
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/titan.h
@@ -0,0 +1,17 @@
1/*
2 * Platform defintions for Titan
3 */
4#ifndef _ASM_SH_TITAN_H
5#define _ASM_SH_TITAN_H
6
7#define __IO_PREFIX titan
8#include <asm/io_generic.h>
9
10/* IRQ assignments */
11#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */
12#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */
13#define TITAN_IRQ_MPCIA 8 /* mPCI A */
14#define TITAN_IRQ_MPCIB 11 /* mPCI B */
15#define TITAN_IRQ_USB 11 /* USB */
16
17#endif /* __ASM_SH_TITAN_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 11:40:33 -0500