diff options
Diffstat (limited to 'arch/sh/drivers/pci/pcie-sh7786.h')
| -rw-r--r-- | arch/sh/drivers/pci/pcie-sh7786.h | 56 |
1 files changed, 54 insertions, 2 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h index 90a6992576b0..1ee054e47eae 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.h +++ b/arch/sh/drivers/pci/pcie-sh7786.h | |||
| @@ -55,8 +55,11 @@ | |||
| 55 | #define BITS_ERRRCV (0) /* 0 ERRRCV 0 */ | 55 | #define BITS_ERRRCV (0) /* 0 ERRRCV 0 */ |
| 56 | #define MASK_ERRRCV (1<<BITS_ERRRCV) | 56 | #define MASK_ERRRCV (1<<BITS_ERRRCV) |
| 57 | 57 | ||
| 58 | /* PCIEENBLR */ | ||
| 59 | #define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */ | ||
| 60 | |||
| 58 | /* PCIEECR */ | 61 | /* PCIEECR */ |
| 59 | #define SH4A_PCIEECR (0x000008) /* R/W - 0x0000 0000 32 */ | 62 | #define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */ |
| 60 | #define BITS_ENBL (0) /* 0 ENBL 0 R/W */ | 63 | #define BITS_ENBL (0) /* 0 ENBL 0 R/W */ |
| 61 | #define MASK_ENBL (1<<BITS_ENBL) | 64 | #define MASK_ENBL (1<<BITS_ENBL) |
| 62 | 65 | ||
| @@ -113,6 +116,27 @@ | |||
| 113 | #define BITS_MDATA (0) | 116 | #define BITS_MDATA (0) |
| 114 | #define MASK_MDATA (0xffffffff<<BITS_MDATA) | 117 | #define MASK_MDATA (0xffffffff<<BITS_MDATA) |
| 115 | 118 | ||
| 119 | /* PCIEUNLOCKCR */ | ||
| 120 | #define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */ | ||
| 121 | |||
| 122 | /* PCIEIDR */ | ||
| 123 | #define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */ | ||
| 124 | |||
| 125 | /* PCIEDBGCTLR */ | ||
| 126 | #define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */ | ||
| 127 | |||
| 128 | /* PCIEINTXR */ | ||
| 129 | #define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */ | ||
| 130 | |||
| 131 | /* PCIERMSGR */ | ||
| 132 | #define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */ | ||
| 133 | |||
| 134 | /* PCIERSTR */ | ||
| 135 | #define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */ | ||
| 136 | |||
| 137 | /* PCIESRSTR */ | ||
| 138 | #define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */ | ||
| 139 | |||
| 116 | /* PCIEPHYCTLR */ | 140 | /* PCIEPHYCTLR */ |
| 117 | #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */ | 141 | #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */ |
| 118 | #define BITS_CKE (0) | 142 | #define BITS_CKE (0) |
| @@ -121,6 +145,9 @@ | |||
| 121 | /* PCIERMSGIER */ | 145 | /* PCIERMSGIER */ |
| 122 | #define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */ | 146 | #define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */ |
| 123 | 147 | ||
| 148 | /* PCIEPHYCTLR */ | ||
| 149 | #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */ | ||
| 150 | |||
| 124 | /* PCIEPHYADRR */ | 151 | /* PCIEPHYADRR */ |
| 125 | #define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */ | 152 | #define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */ |
| 126 | #define BITS_ACK (24) // Rev1.171 | 153 | #define BITS_ACK (24) // Rev1.171 |
| @@ -152,7 +179,7 @@ | |||
| 152 | #define MASK_CFINT (1<<BITS_CFINT) | 179 | #define MASK_CFINT (1<<BITS_CFINT) |
| 153 | 180 | ||
| 154 | /* PCIETSTR */ | 181 | /* PCIETSTR */ |
| 155 | #define SH4A_PCIETSTR (0x020004) /* R/W R/W 0x0000 0000 32 */ | 182 | #define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */ |
| 156 | 183 | ||
| 157 | /* PCIEINTR */ | 184 | /* PCIEINTR */ |
| 158 | #define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */ | 185 | #define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */ |
| @@ -236,6 +263,9 @@ | |||
| 236 | #define BITS_INTPM (8) | 263 | #define BITS_INTPM (8) |
| 237 | #define MASK_INTPM (1<<BITS_INTPM) | 264 | #define MASK_INTPM (1<<BITS_INTPM) |
| 238 | 265 | ||
| 266 | /* PCIEEH0R */ | ||
| 267 | #define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */ | ||
| 268 | |||
| 239 | /* PCIEAIR */ | 269 | /* PCIEAIR */ |
| 240 | #define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */ | 270 | #define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */ |
| 241 | 271 | ||
| @@ -244,6 +274,25 @@ | |||
| 244 | 274 | ||
| 245 | /* PCIEERRFR */ // Rev1.18 | 275 | /* PCIEERRFR */ // Rev1.18 |
| 246 | #define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18 | 276 | #define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18 |
| 277 | |||
| 278 | /* PCIEERRFER */ | ||
| 279 | #define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */ | ||
| 280 | |||
| 281 | /* PCIEERRFR2 */ | ||
| 282 | #define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */ | ||
| 283 | |||
| 284 | /* PCIEMSIR */ | ||
| 285 | #define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */ | ||
| 286 | |||
| 287 | /* PCIEMSIFR */ | ||
| 288 | #define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */ | ||
| 289 | |||
| 290 | /* PCIEPWRCTLR */ | ||
| 291 | #define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */ | ||
| 292 | |||
| 293 | /* PCIEPCCTLR */ | ||
| 294 | #define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */ | ||
| 295 | |||
| 247 | // Rev1.18 | 296 | // Rev1.18 |
| 248 | /* PCIELAR0 */ | 297 | /* PCIELAR0 */ |
| 249 | #define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */ | 298 | #define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */ |
| @@ -352,6 +401,7 @@ | |||
| 352 | #define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */ | 401 | #define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */ |
| 353 | #define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */ | 402 | #define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */ |
| 354 | #define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */ | 403 | #define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */ |
| 404 | #define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */ | ||
| 355 | #define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */ | 405 | #define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */ |
| 356 | #define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */ | 406 | #define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */ |
| 357 | #define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */ | 407 | #define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */ |
| @@ -363,6 +413,7 @@ | |||
| 363 | #define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */ | 413 | #define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */ |
| 364 | #define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */ | 414 | #define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */ |
| 365 | #define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */ | 415 | #define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */ |
| 416 | #define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */ | ||
| 366 | #define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */ | 417 | #define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */ |
| 367 | #define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */ | 418 | #define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */ |
| 368 | #define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */ | 419 | #define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */ |
| @@ -385,6 +436,7 @@ | |||
| 385 | #define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */ | 436 | #define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */ |
| 386 | #define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */ | 437 | #define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */ |
| 387 | #define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */ | 438 | #define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */ |
| 439 | #define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */ | ||
| 388 | #define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */ | 440 | #define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */ |
| 389 | #define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */ | 441 | #define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */ |
| 390 | #define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */ | 442 | #define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */ |