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path: root/arch/sh/drivers/pci/pci-sh7751.h
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Diffstat (limited to 'arch/sh/drivers/pci/pci-sh7751.h')
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.h12
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h
index 68e3cb5e6bec..4983a4d20355 100644
--- a/arch/sh/drivers/pci/pci-sh7751.h
+++ b/arch/sh/drivers/pci/pci-sh7751.h
@@ -26,7 +26,6 @@
26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
27 27
28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ 28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
29#define PCI_REG(n) (SH7751_PCIREG_BASE+ n)
30 29
31#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */ 30#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
32 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */ 31 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
@@ -58,7 +57,7 @@
58 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 57 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
59 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 58 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
60 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 59 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
61#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 60#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
62 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 61 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
63 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 62 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
64 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ 63 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
@@ -73,12 +72,12 @@
73 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
74 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ 73 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
75 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ 74 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
76 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ 75 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
77#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ 76#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
78 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 77 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
79 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ 78 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
80 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ 79 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
81 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ 80 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
82/* PCICONF7 - PCICONF10 are undefined */ 81/* PCICONF7 - PCICONF10 are undefined */
83#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ 82#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
84 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ 83 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
@@ -127,9 +126,4 @@
127#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) 126#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
128#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) 127#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
129 128
130struct sh4_pci_address_map;
131
132/* arch/sh/drivers/pci/pci-sh7751.c */
133int sh7751_pcic_init(struct sh4_pci_address_map *map);
134
135#endif /* _PCI_SH7751_H_ */ 129#endif /* _PCI_SH7751_H_ */