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path: root/arch/sh/drivers/pci/pci-sh4.h
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Diffstat (limited to 'arch/sh/drivers/pci/pci-sh4.h')
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h18
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde622..cbf763b3015e 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -49,6 +49,17 @@
49 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ 49 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
50 #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */ 50 #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
51#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */ 51#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
52 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
53 #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
54 #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
55 #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
56 #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
57 #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
58 #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
59 #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
60 #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
61 #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
62 #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
52#define SH4_PCIALR 0x11C /* Error Address Register */ 63#define SH4_PCIALR 0x11C /* Error Address Register */
53#define SH4_PCICLR 0x120 /* Error Command/Data */ 64#define SH4_PCICLR 0x120 /* Error Command/Data */
54 #define SH4_PCICLR_MPIO 0x80000000 65 #define SH4_PCICLR_MPIO 0x80000000
@@ -61,7 +72,7 @@
61#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */ 72#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
62 #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ 73 #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
63 #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ 74 #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
64 #define SH4_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */ 75 #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
65 #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */ 76 #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
66 #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */ 77 #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
67 #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ 78 #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
@@ -151,7 +162,6 @@
151 162
152/* arch/sh/kernel/drivers/pci/ops-sh4.c */ 163/* arch/sh/kernel/drivers/pci/ops-sh4.c */
153extern struct pci_ops sh4_pci_ops; 164extern struct pci_ops sh4_pci_ops;
154int sh4_pci_check_direct(struct pci_channel *chan);
155int pci_fixup_pcic(struct pci_channel *chan); 165int pci_fixup_pcic(struct pci_channel *chan);
156 166
157struct sh4_pci_address_space { 167struct sh4_pci_address_space {
@@ -167,13 +177,13 @@ struct sh4_pci_address_map {
167static inline void pci_write_reg(struct pci_channel *chan, 177static inline void pci_write_reg(struct pci_channel *chan,
168 unsigned long val, unsigned long reg) 178 unsigned long val, unsigned long reg)
169{ 179{
170 ctrl_outl(val, chan->reg_base + reg); 180 __raw_writel(val, chan->reg_base + reg);
171} 181}
172 182
173static inline unsigned long pci_read_reg(struct pci_channel *chan, 183static inline unsigned long pci_read_reg(struct pci_channel *chan,
174 unsigned long reg) 184 unsigned long reg)
175{ 185{
176 return ctrl_inl(chan->reg_base + reg); 186 return __raw_readl(chan->reg_base + reg);
177} 187}
178 188
179#endif /* __PCI_SH4_H */ 189#endif /* __PCI_SH4_H */