diff options
Diffstat (limited to 'arch/sh/drivers/pci/fixups-r7780rp.c')
-rw-r--r-- | arch/sh/drivers/pci/fixups-r7780rp.c | 41 |
1 files changed, 16 insertions, 25 deletions
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c index 3e321df65d22..15ca65cb667e 100644 --- a/arch/sh/drivers/pci/fixups-r7780rp.c +++ b/arch/sh/drivers/pci/fixups-r7780rp.c | |||
@@ -11,35 +11,26 @@ | |||
11 | * for more details. | 11 | * for more details. |
12 | */ | 12 | */ |
13 | #include <linux/pci.h> | 13 | #include <linux/pci.h> |
14 | #include <linux/io.h> | ||
14 | #include "pci-sh4.h" | 15 | #include "pci-sh4.h" |
15 | #include <asm/io.h> | ||
16 | 16 | ||
17 | int pci_fixup_pcic(void) | 17 | static char irq_tab[] __initdata = { |
18 | { | 18 | 65, 66, 67, 68, |
19 | pci_write_reg(0x000043ff, SH4_PCIINTM); | 19 | }; |
20 | pci_write_reg(0x0000380f, SH4_PCIAINTM); | ||
21 | |||
22 | pci_write_reg(0xfbb00047, SH7780_PCICMD); | ||
23 | pci_write_reg(0x00000000, SH7780_PCIIBAR); | ||
24 | |||
25 | pci_write_reg(0x00011912, SH7780_PCISVID); | ||
26 | pci_write_reg(0x08000000, SH7780_PCICSCR0); | ||
27 | pci_write_reg(0x0000001b, SH7780_PCICSAR0); | ||
28 | pci_write_reg(0xfd000000, SH7780_PCICSCR1); | ||
29 | pci_write_reg(0x0000000f, SH7780_PCICSAR1); | ||
30 | |||
31 | pci_write_reg(0xfd000000, SH7780_PCIMBR0); | ||
32 | pci_write_reg(0x00fc0000, SH7780_PCIMBMR0); | ||
33 | 20 | ||
34 | #ifdef CONFIG_32BIT | 21 | int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) |
35 | pci_write_reg(0xc0000000, SH7780_PCIMBR2); | 22 | { |
36 | pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); | 23 | return irq_tab[slot]; |
37 | #endif | 24 | } |
38 | 25 | ||
39 | /* Set IOBR for windows containing area specified in pci.h */ | 26 | int pci_fixup_pcic(struct pci_channel *chan) |
40 | pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), | 27 | { |
41 | SH7780_PCIIOBR); | 28 | pci_write_reg(chan, 0x000043ff, SH4_PCIINTM); |
42 | pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); | 29 | pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR); |
30 | pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0); | ||
31 | pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0); | ||
32 | pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1); | ||
33 | pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1); | ||
43 | 34 | ||
44 | return 0; | 35 | return 0; |
45 | } | 36 | } |