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-rw-r--r--arch/sh/drivers/dma/dma-pvr2.c10
-rw-r--r--arch/sh/drivers/dma/dma-sh.c31
-rw-r--r--arch/sh/drivers/dma/dmabrg.c22
3 files changed, 33 insertions, 30 deletions
diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c
index 391cbe1c2956..3cee58e7f1e5 100644
--- a/arch/sh/drivers/dma/dma-pvr2.c
+++ b/arch/sh/drivers/dma/dma-pvr2.c
@@ -40,10 +40,10 @@ static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
40 40
41static int pvr2_request_dma(struct dma_channel *chan) 41static int pvr2_request_dma(struct dma_channel *chan)
42{ 42{
43 if (ctrl_inl(PVR2_DMA_MODE) != 0) 43 if (__raw_readl(PVR2_DMA_MODE) != 0)
44 return -EBUSY; 44 return -EBUSY;
45 45
46 ctrl_outl(0, PVR2_DMA_LMMODE0); 46 __raw_writel(0, PVR2_DMA_LMMODE0);
47 47
48 return 0; 48 return 0;
49} 49}
@@ -60,9 +60,9 @@ static int pvr2_xfer_dma(struct dma_channel *chan)
60 60
61 xfer_complete = 0; 61 xfer_complete = 0;
62 62
63 ctrl_outl(chan->dar, PVR2_DMA_ADDR); 63 __raw_writel(chan->dar, PVR2_DMA_ADDR);
64 ctrl_outl(chan->count, PVR2_DMA_COUNT); 64 __raw_writel(chan->count, PVR2_DMA_COUNT);
65 ctrl_outl(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE); 65 __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
66 66
67 return 0; 67 return 0;
68} 68}
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 37fb5b8bbc3f..827208781ed5 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
52 * 52 *
53 * iterations to complete the transfer. 53 * iterations to complete the transfer.
54 */ 54 */
55static unsigned int ts_shift[] = TS_SHIFT;
55static inline unsigned int calc_xmit_shift(struct dma_channel *chan) 56static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
56{ 57{
57 u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 58 u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
59 int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
60 ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
58 61
59 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; 62 return ts_shift[cnt];
60} 63}
61 64
62/* 65/*
@@ -70,13 +73,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
70 struct dma_channel *chan = dev_id; 73 struct dma_channel *chan = dev_id;
71 u32 chcr; 74 u32 chcr;
72 75
73 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 76 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
74 77
75 if (!(chcr & CHCR_TE)) 78 if (!(chcr & CHCR_TE))
76 return IRQ_NONE; 79 return IRQ_NONE;
77 80
78 chcr &= ~(CHCR_IE | CHCR_DE); 81 chcr &= ~(CHCR_IE | CHCR_DE);
79 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 82 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
80 83
81 wake_up(&chan->wait_queue); 84 wake_up(&chan->wait_queue);
82 85
@@ -115,7 +118,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
115 chan->flags &= ~DMA_TEI_CAPABLE; 118 chan->flags &= ~DMA_TEI_CAPABLE;
116 } 119 }
117 120
118 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 121 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
119 122
120 chan->flags |= DMA_CONFIGURED; 123 chan->flags |= DMA_CONFIGURED;
121 return 0; 124 return 0;
@@ -126,13 +129,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
126 int irq; 129 int irq;
127 u32 chcr; 130 u32 chcr;
128 131
129 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 132 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
130 chcr |= CHCR_DE; 133 chcr |= CHCR_DE;
131 134
132 if (chan->flags & DMA_TEI_CAPABLE) 135 if (chan->flags & DMA_TEI_CAPABLE)
133 chcr |= CHCR_IE; 136 chcr |= CHCR_IE;
134 137
135 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 138 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
136 139
137 if (chan->flags & DMA_TEI_CAPABLE) { 140 if (chan->flags & DMA_TEI_CAPABLE) {
138 irq = get_dmte_irq(chan->chan); 141 irq = get_dmte_irq(chan->chan);
@@ -150,9 +153,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
150 disable_irq(irq); 153 disable_irq(irq);
151 } 154 }
152 155
153 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 156 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); 157 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
155 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 158 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
156} 159}
157 160
158static int sh_dmac_xfer_dma(struct dma_channel *chan) 161static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +186,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
183 */ 186 */
184 if (chan->sar || (mach_is_dreamcast() && 187 if (chan->sar || (mach_is_dreamcast() &&
185 chan->chan == PVR2_CASCADE_CHAN)) 188 chan->chan == PVR2_CASCADE_CHAN))
186 ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR)); 189 __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
187 if (chan->dar || (mach_is_dreamcast() && 190 if (chan->dar || (mach_is_dreamcast() &&
188 chan->chan == PVR2_CASCADE_CHAN)) 191 chan->chan == PVR2_CASCADE_CHAN))
189 ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR)); 192 __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
190 193
191 ctrl_outl(chan->count >> calc_xmit_shift(chan), 194 __raw_writel(chan->count >> calc_xmit_shift(chan),
192 (dma_base_addr[chan->chan] + TCR)); 195 (dma_base_addr[chan->chan] + TCR));
193 196
194 sh_dmac_enable_dma(chan); 197 sh_dmac_enable_dma(chan);
@@ -198,10 +201,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
198 201
199static int sh_dmac_get_dma_residue(struct dma_channel *chan) 202static int sh_dmac_get_dma_residue(struct dma_channel *chan)
200{ 203{
201 if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE)) 204 if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
202 return 0; 205 return 0;
203 206
204 return ctrl_inl(dma_base_addr[chan->chan] + TCR) 207 return __raw_readl(dma_base_addr[chan->chan] + TCR)
205 << calc_xmit_shift(chan); 208 << calc_xmit_shift(chan);
206} 209}
207 210
diff --git a/arch/sh/drivers/dma/dmabrg.c b/arch/sh/drivers/dma/dmabrg.c
index 5e22689c2fcf..72622e307613 100644
--- a/arch/sh/drivers/dma/dmabrg.c
+++ b/arch/sh/drivers/dma/dmabrg.c
@@ -86,8 +86,8 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
86 unsigned long dcr; 86 unsigned long dcr;
87 unsigned int i; 87 unsigned int i;
88 88
89 dcr = ctrl_inl(DMABRGCR); 89 dcr = __raw_readl(DMABRGCR);
90 ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ 90 __raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
91 dcr &= dcr >> 8; /* ignore masked */ 91 dcr &= dcr >> 8; /* ignore masked */
92 92
93 /* USB stuff, get it out of the way first */ 93 /* USB stuff, get it out of the way first */
@@ -109,17 +109,17 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
109static void dmabrg_disable_irq(unsigned int dmairq) 109static void dmabrg_disable_irq(unsigned int dmairq)
110{ 110{
111 unsigned long dcr; 111 unsigned long dcr;
112 dcr = ctrl_inl(DMABRGCR); 112 dcr = __raw_readl(DMABRGCR);
113 dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); 113 dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
114 ctrl_outl(dcr, DMABRGCR); 114 __raw_writel(dcr, DMABRGCR);
115} 115}
116 116
117static void dmabrg_enable_irq(unsigned int dmairq) 117static void dmabrg_enable_irq(unsigned int dmairq)
118{ 118{
119 unsigned long dcr; 119 unsigned long dcr;
120 dcr = ctrl_inl(DMABRGCR); 120 dcr = __raw_readl(DMABRGCR);
121 dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); 121 dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
122 ctrl_outl(dcr, DMABRGCR); 122 __raw_writel(dcr, DMABRGCR);
123} 123}
124 124
125int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*), 125int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*),
@@ -165,13 +165,13 @@ static int __init dmabrg_init(void)
165 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n"); 165 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n");
166#endif 166#endif
167 167
168 ctrl_outl(0, DMABRGCR); 168 __raw_writel(0, DMABRGCR);
169 ctrl_outl(0, DMACHCR0); 169 __raw_writel(0, DMACHCR0);
170 ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ 170 __raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
171 171
172 /* enable DMABRG mode, enable the DMAC */ 172 /* enable DMABRG mode, enable the DMAC */
173 or = ctrl_inl(DMAOR); 173 or = __raw_readl(DMAOR);
174 ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR); 174 __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
175 175
176 ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED, 176 ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED,
177 "DMABRG USB address error", NULL); 177 "DMABRG USB address error", NULL);