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-rw-r--r--arch/sh/boards/renesas/hs7751rvoip/pci.c149
1 files changed, 0 insertions, 149 deletions
diff --git a/arch/sh/boards/renesas/hs7751rvoip/pci.c b/arch/sh/boards/renesas/hs7751rvoip/pci.c
deleted file mode 100644
index 1c0ddee30d21..000000000000
--- a/arch/sh/boards/renesas/hs7751rvoip/pci.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * linux/arch/sh/boards/renesas/hs7751rvoip/pci.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Renesas SH7751R HS7751RVoIP board
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/module.h>
20
21#include <asm/io.h>
22#include "../../../drivers/pci/pci-sh7751.h"
23#include <asm/hs7751rvoip/hs7751rvoip.h>
24
25#define PCIMCR_MRSET_OFF 0xBFFFFFFF
26#define PCIMCR_RFSH_OFF 0xFFFFFFFB
27
28/*
29 * Only long word accesses of the PCIC's internal local registers and the
30 * configuration registers from the CPU is supported.
31 */
32#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
33#define PCIC_READ(x) readl(PCI_REG(x))
34
35/*
36 * Description: This function sets up and initializes the pcic, sets
37 * up the BARS, maps the DRAM into the address space etc, etc.
38 */
39int __init pcibios_init_platform(void)
40{
41 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
42 unsigned short bcr2, bcr3;
43
44 /*
45 * Initialize the slave bus controller on the pcic. The values used
46 * here should not be hardcoded, but they should be taken from the bsc
47 * on the processor, to make this function as generic as possible.
48 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
49 * for the pcic to work, its settings need to be exactly the same.)
50 */
51 bcr1 = (*(volatile unsigned long *)(SH7751_BCR1));
52 bcr2 = (*(volatile unsigned short *)(SH7751_BCR2));
53 bcr3 = (*(volatile unsigned short *)(SH7751_BCR3));
54 wcr1 = (*(volatile unsigned long *)(SH7751_WCR1));
55 wcr2 = (*(volatile unsigned long *)(SH7751_WCR2));
56 wcr3 = (*(volatile unsigned long *)(SH7751_WCR3));
57 mcr = (*(volatile unsigned long *)(SH7751_MCR));
58
59 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
60 (*(volatile unsigned long *)(SH7751_BCR1)) = bcr1;
61
62 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
63 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
64 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
65 PCIC_WRITE(SH7751_PCIBCR3, bcr3); /* PCIC BCR3 */
66 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
67 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
68 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
69 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
70 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
71
72 /* Enable all interrupts, so we know what to fix */
73 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
74 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
75
76 /* Set up standard PCI config registers */
77 PCIC_WRITE(SH7751_PCICONF1, 0xFB900047); /* Bus Master, Mem & I/O access */
78 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
79 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
80 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
81 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
82 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
83 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
84 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
85 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
86 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
87
88 /* Now turn it on... */
89 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
90
91 /*
92 * Set PCIMBR and PCIIOBR here, assuming a single window
93 * (16M MEM, 256K IO) is enough. If a larger space is
94 * needed, the readx/writex and inx/outx functions will
95 * have to do more (e.g. setting registers for each call).
96 */
97
98 /*
99 * Set the MBR so PCI address is one-to-one with window,
100 * meaning all calls go straight through... use ifdef to
101 * catch erroneous assumption.
102 */
103 BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
104
105 PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM);
106
107 /* Set IOBR for window containing area specified in pci.h */
108 PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
109
110 /* All done, may as well say so... */
111 printk("SH7751R PCI: Finished initialization of the PCI controller\n");
112
113 return 1;
114}
115
116int __init pcibios_map_platform_irq(u8 slot, u8 pin)
117{
118 switch (slot) {
119 case 0: return IRQ_PCISLOT; /* PCI Extend slot */
120 case 1: return IRQ_PCMCIA; /* PCI Cardbus Bridge */
121 case 2: return IRQ_PCIETH; /* Realtek Ethernet controller */
122 case 3: return IRQ_PCIHUB; /* Realtek Ethernet Hub controller */
123 default:
124 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
125 return -1;
126 }
127}
128
129static struct resource sh7751_io_resource = {
130 .name = "SH7751_IO",
131 .start = 0x4000,
132 .end = 0x4000 + SH7751_PCI_IO_SIZE - 1,
133 .flags = IORESOURCE_IO
134};
135
136static struct resource sh7751_mem_resource = {
137 .name = "SH7751_mem",
138 .start = SH7751_PCI_MEMORY_BASE,
139 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
140 .flags = IORESOURCE_MEM
141};
142
143extern struct pci_ops sh7751_pci_ops;
144
145struct pci_channel board_pci_channels[] = {
146 { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
147 { NULL, NULL, NULL, 0, 0 },
148};
149EXPORT_SYMBOL(board_pci_channels);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 03:14:30 -0500