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-rw-r--r--arch/sh/boards/overdrive/galileo.c587
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diff --git a/arch/sh/boards/overdrive/galileo.c b/arch/sh/boards/overdrive/galileo.c
deleted file mode 100644
index 29e48971bba0..000000000000
--- a/arch/sh/boards/overdrive/galileo.c
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@@ -1,587 +0,0 @@
1/*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * This file contains the PCI routines required for the Galileo GT6411
8 * PCI bridge as used on the Orion and Overdrive boards.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/smp.h>
14#include <linux/smp_lock.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/types.h>
20#include <linux/ioport.h>
21
22#include <asm/overdrive/overdrive.h>
23#include <asm/overdrive/gt64111.h>
24
25
26/* After boot, we shift the Galileo registers so that they appear
27 * in BANK6, along with IO space. This means we can have one contingous
28 * lump of PCI address space without these registers appearing in the
29 * middle of them
30 */
31
32#define GT64111_BASE_ADDRESS 0xbb000000
33#define GT64111_IO_BASE_ADDRESS 0x1000
34/* The GT64111 registers appear at this address to the SH4 after reset */
35#define RESET_GT64111_BASE_ADDRESS 0xb4000000
36
37/* Macros used to access the Galileo registers */
38#define RESET_GT64111_REG(x) (RESET_GT64111_BASE_ADDRESS+x)
39#define GT64111_REG(x) (GT64111_BASE_ADDRESS+x)
40
41#define RESET_GT_WRITE(x,v) writel((v),RESET_GT64111_REG(x))
42
43#define RESET_GT_READ(x) readl(RESET_GT64111_REG(x))
44
45#define GT_WRITE(x,v) writel((v),GT64111_REG(x))
46#define GT_WRITE_BYTE(x,v) writeb((v),GT64111_REG(x))
47#define GT_WRITE_SHORT(x,v) writew((v),GT64111_REG(x))
48
49#define GT_READ(x) readl(GT64111_REG(x))
50#define GT_READ_BYTE(x) readb(GT64111_REG(x))
51#define GT_READ_SHORT(x) readw(GT64111_REG(x))
52
53
54/* Where the various SH banks start at */
55#define SH_BANK4_ADR 0xb0000000
56#define SH_BANK5_ADR 0xb4000000
57#define SH_BANK6_ADR 0xb8000000
58
59/* Masks out everything but lines 28,27,26 */
60#define BANK_SELECT_MASK 0x1c000000
61
62#define SH4_TO_BANK(x) ( (x) & BANK_SELECT_MASK)
63
64/*
65 * Masks used for address conversaion. Bank 6 is used for IO and
66 * has all the address bits zeroed by the FPGA. Special case this
67 */
68#define MEMORY_BANK_MASK 0x1fffffff
69#define IO_BANK_MASK 0x03ffffff
70
71/* Mark bank 6 as the bank used for IO. You can change this in the FPGA code
72 * if you want
73 */
74#define IO_BANK_ADR PCI_GTIO_BASE
75
76/* Will select the correct mask to apply depending on the SH$ address */
77#define SELECT_BANK_MASK(x) \
78 ( (SH4_TO_BANK(x)==SH4_TO_BANK(IO_BANK_ADR)) ? IO_BANK_MASK : MEMORY_BANK_MASK)
79
80/* Converts between PCI space and P2 region */
81#define SH4_TO_PCI(x) ((x)&SELECT_BANK_MASK(x))
82
83/* Various macros for figuring out what to stick in the Galileo registers.
84 * You *really* don't want to figure this stuff out by hand, you always get
85 * it wrong
86 */
87#define GT_MEM_LO_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7ff)
88#define GT_MEM_HI_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7f)
89#define GT_MEM_SUB_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>20)&0xff)
90
91#define PROGRAM_HI_LO(block,a,s) \
92 GT_WRITE(block##_LO_DEC_ADR,GT_MEM_LO_ADR(a));\
93 GT_WRITE(block##_HI_DEC_ADR,GT_MEM_HI_ADR(a+s-1))
94
95#define PROGRAM_SUB_HI_LO(block,a,s) \
96 GT_WRITE(block##_LO_DEC_ADR,GT_MEM_SUB_ADR(a));\
97 GT_WRITE(block##_HI_DEC_ADR,GT_MEM_SUB_ADR(a+s-1))
98
99/* We need to set the size, and the offset register */
100
101#define GT_BAR_MASK(x) ((x)&~0xfff)
102
103/* Macro to set up the BAR in the Galileo. Essentially used for the DRAM */
104#define PROGRAM_GT_BAR(block,a,s) \
105 GT_WRITE(PCI_##block##_BANK_SIZE,GT_BAR_MASK((s-1)));\
106 write_config_to_galileo(PCI_CONFIG_##block##_BASE_ADR,\
107 GT_BAR_MASK(a))
108
109#define DISABLE_GT_BAR(block) \
110 GT_WRITE(PCI_##block##_BANK_SIZE,0),\
111 GT_CONFIG_WRITE(PCI_CONFIG_##block##_BASE_ADR,\
112 0x80000000)
113
114/* Macros to disable things we are not going to use */
115#define DISABLE_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0x7ff);\
116 GT_WRITE(x##_HI_DEC_ADR,0x00)
117
118#define DISABLE_SUB_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0xff);\
119 GT_WRITE(x##_HI_DEC_ADR,0x00)
120
121static void __init reset_pci(void)
122{
123 /* Set RESET_PCI bit high */
124 writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
125 udelay(250);
126
127 /* Set RESET_PCI bit low */
128 writeb(readb(OVERDRIVE_CTRL) & RESET_PCI_MASK, OVERDRIVE_CTRL);
129 udelay(250);
130
131 writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
132 udelay(250);
133}
134
135static int write_config_to_galileo(int where, u32 val);
136#define GT_CONFIG_WRITE(where,val) write_config_to_galileo(where,val)
137
138#define ENABLE_PCI_DRAM
139
140
141#ifdef TEST_DRAM
142/* Test function to check out if the PCI DRAM is working OK */
143static int /* __init */ test_dram(unsigned *base, unsigned size)
144{
145 unsigned *p = base;
146 unsigned *end = (unsigned *) (((unsigned) base) + size);
147 unsigned w;
148
149 for (p = base; p < end; p++) {
150 *p = 0xffffffff;
151 if (*p != 0xffffffff) {
152 printk("AAARGH -write failed!!! at %p is %x\n", p,
153 *p);
154 return 0;
155 }
156 *p = 0x0;
157 if (*p != 0x0) {
158 printk("AAARGH -write failed!!!\n");
159 return 0;
160 }
161 }
162
163 for (p = base; p < end; p++) {
164 *p = (unsigned) p;
165 if (*p != (unsigned) p) {
166 printk("Failed at 0x%p, actually is 0x%x\n", p,
167 *p);
168 return 0;
169 }
170 }
171
172 for (p = base; p < end; p++) {
173 w = ((unsigned) p & 0xffff0000);
174 *p = w | (w >> 16);
175 }
176
177 for (p = base; p < end; p++) {
178 w = ((unsigned) p & 0xffff0000);
179 w |= (w >> 16);
180 if (*p != w) {
181 printk
182 ("Failed at 0x%p, should be 0x%x actually is 0x%x\n",
183 p, w, *p);
184 return 0;
185 }
186 }
187
188 return 1;
189}
190#endif
191
192
193/* Function to set up and initialise the galileo. This sets up the BARS,
194 * maps the DRAM into the address space etc,etc
195 */
196int __init galileo_init(void)
197{
198 reset_pci();
199
200 /* Now shift the galileo regs into this block */
201 RESET_GT_WRITE(INTERNAL_SPACE_DEC,
202 GT_MEM_LO_ADR(GT64111_BASE_ADDRESS));
203
204 /* Should have a sanity check here, that you can read back at the new
205 * address what you just wrote
206 */
207
208 /* Disable decode for all regions */
209 DISABLE_DECODE(RAS10);
210 DISABLE_DECODE(RAS32);
211 DISABLE_DECODE(CS20);
212 DISABLE_DECODE(CS3);
213 DISABLE_DECODE(PCI_IO);
214 DISABLE_DECODE(PCI_MEM0);
215 DISABLE_DECODE(PCI_MEM1);
216
217 /* Disable all BARS */
218 GT_WRITE(BAR_ENABLE_ADR, 0x1ff);
219 DISABLE_GT_BAR(RAS10);
220 DISABLE_GT_BAR(RAS32);
221 DISABLE_GT_BAR(CS20);
222 DISABLE_GT_BAR(CS3);
223
224 /* Tell the BAR where the IO registers now are */
225 GT_CONFIG_WRITE(PCI_CONFIG_INT_REG_IO_ADR,GT_BAR_MASK(
226 (GT64111_IO_BASE_ADDRESS &
227 IO_BANK_MASK)));
228 /* set up a 112 Mb decode */
229 PROGRAM_HI_LO(PCI_MEM0, SH_BANK4_ADR, 112 * 1024 * 1024);
230
231 /* Set up a 32 MB io space decode */
232 PROGRAM_HI_LO(PCI_IO, IO_BANK_ADR, 32 * 1024 * 1024);
233
234#ifdef ENABLE_PCI_DRAM
235 /* Program up the DRAM configuration - there is DRAM only in bank 0 */
236 /* Now set up the DRAM decode */
237 PROGRAM_HI_LO(RAS10, PCI_DRAM_BASE, PCI_DRAM_SIZE);
238 /* And the sub decode */
239 PROGRAM_SUB_HI_LO(RAS0, PCI_DRAM_BASE, PCI_DRAM_SIZE);
240
241 DISABLE_SUB_DECODE(RAS1);
242
243 /* Set refresh rate */
244 GT_WRITE(DRAM_BANK0_PARMS, 0x3f);
245 GT_WRITE(DRAM_CFG, 0x100);
246
247 /* we have to lob off the top bits rememeber!! */
248 PROGRAM_GT_BAR(RAS10, SH4_TO_PCI(PCI_DRAM_BASE), PCI_DRAM_SIZE);
249
250#endif
251
252 /* We are only interested in decoding RAS10 and the Galileo's internal
253 * registers (as IO) on the PCI bus
254 */
255#ifdef ENABLE_PCI_DRAM
256 GT_WRITE(BAR_ENABLE_ADR, (~((1 << 8) | (1 << 3))) & 0x1ff);
257#else
258 GT_WRITE(BAR_ENABLE_ADR, (~(1 << 3)) & 0x1ff);
259#endif
260
261 /* Change the class code to host bridge, it actually powers up
262 * as a memory controller
263 */
264 GT_CONFIG_WRITE(8, 0x06000011);
265
266 /* Allow the galileo to master the PCI bus */
267 GT_CONFIG_WRITE(PCI_COMMAND,
268 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
269 PCI_COMMAND_IO);
270
271
272#if 0
273 printk("Testing PCI DRAM - ");
274 if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
275 printk("Passed\n");
276 }else {
277 printk("FAILED\n");
278 }
279#endif
280 return 0;
281
282}
283
284
285#define SET_CONFIG_BITS(bus,devfn,where)\
286 ((1<<31) | ((bus) << 16) | ((devfn) << 8) | ((where) & ~3))
287
288#define CONFIG_CMD(dev, where) SET_CONFIG_BITS((dev)->bus->number,(dev)->devfn,where)
289
290/* This write to the galileo config registers, unlike the functions below, can
291 * be used before the PCI subsystem has started up
292 */
293static int __init write_config_to_galileo(int where, u32 val)
294{
295 GT_WRITE(PCI_CFG_ADR, SET_CONFIG_BITS(0, 0, where));
296
297 GT_WRITE(PCI_CFG_DATA, val);
298 return 0;
299}
300
301/* We exclude the galileo and slot 31, the galileo because I don't know how to stop
302 * the setup code shagging up the setup I have done on it, and 31 because the whole
303 * thing locks up if you try to access that slot (which doesn't exist of course anyway
304 */
305
306#define EXCLUDED_DEV(dev) ((dev->bus->number==0) && ((PCI_SLOT(dev->devfn)==0) || (PCI_SLOT(dev->devfn) == 31)))
307
308static int galileo_read_config_byte(struct pci_dev *dev, int where,
309 u8 * val)
310{
311
312
313 /* I suspect this doesn't work because this drives a special cycle ? */
314 if (EXCLUDED_DEV(dev)) {
315 *val = 0xff;
316 return PCIBIOS_SUCCESSFUL;
317 }
318 /* Start the config cycle */
319 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
320 /* Read back the result */
321 *val = GT_READ_BYTE(PCI_CFG_DATA + (where & 3));
322
323 return PCIBIOS_SUCCESSFUL;
324}
325
326
327static int galileo_read_config_word(struct pci_dev *dev, int where,
328 u16 * val)
329{
330
331 if (EXCLUDED_DEV(dev)) {
332 *val = 0xffff;
333 return PCIBIOS_SUCCESSFUL;
334 }
335
336 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
337 *val = GT_READ_SHORT(PCI_CFG_DATA + (where & 2));
338
339 return PCIBIOS_SUCCESSFUL;
340}
341
342
343static int galileo_read_config_dword(struct pci_dev *dev, int where,
344 u32 * val)
345{
346 if (EXCLUDED_DEV(dev)) {
347 *val = 0xffffffff;
348 return PCIBIOS_SUCCESSFUL;
349 }
350
351 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
352 *val = GT_READ(PCI_CFG_DATA);
353
354 return PCIBIOS_SUCCESSFUL;
355}
356
357static int galileo_write_config_byte(struct pci_dev *dev, int where,
358 u8 val)
359{
360 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
361
362 GT_WRITE_BYTE(PCI_CFG_DATA + (where & 3), val);
363
364 return PCIBIOS_SUCCESSFUL;
365}
366
367
368static int galileo_write_config_word(struct pci_dev *dev, int where,
369 u16 val)
370{
371 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
372
373 GT_WRITE_SHORT(PCI_CFG_DATA + (where & 2), val);
374
375 return PCIBIOS_SUCCESSFUL;
376}
377
378static int galileo_write_config_dword(struct pci_dev *dev, int where,
379 u32 val)
380{
381 GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
382
383 GT_WRITE(PCI_CFG_DATA, val);
384
385 return PCIBIOS_SUCCESSFUL;
386}
387
388static struct pci_ops pci_config_ops = {
389 galileo_read_config_byte,
390 galileo_read_config_word,
391 galileo_read_config_dword,
392 galileo_write_config_byte,
393 galileo_write_config_word,
394 galileo_write_config_dword
395};
396
397
398/* Everything hangs off this */
399static struct pci_bus *pci_root_bus;
400
401
402static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
403{
404 return PCI_SLOT(dev->devfn);
405}
406
407static int __init map_od_irq(struct pci_dev *dev, u8 slot, u8 pin)
408{
409 /* Slot 1: Galileo
410 * Slot 2: PCI Slot 1
411 * Slot 3: PCI Slot 2
412 * Slot 4: ESS
413 */
414 switch (slot) {
415 case 2:
416 return OVERDRIVE_PCI_IRQ1;
417 case 3:
418 /* Note this assumes you have a hacked card in slot 2 */
419 return OVERDRIVE_PCI_IRQ2;
420 case 4:
421 return OVERDRIVE_ESS_IRQ;
422 default:
423 /* printk("PCI: Unexpected IRQ mapping request for slot %d\n", slot); */
424 return -1;
425 }
426}
427
428
429
430void __init
431pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
432{
433 ranges->io_start -= bus->resource[0]->start;
434 ranges->io_end -= bus->resource[0]->start;
435 ranges->mem_start -= bus->resource[1]->start;
436 ranges->mem_end -= bus->resource[1]->start;
437}
438
439static void __init pci_fixup_ide_bases(struct pci_dev *d)
440{
441 int i;
442
443 /*
444 * PCI IDE controllers use non-standard I/O port decoding, respect it.
445 */
446 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
447 return;
448 printk("PCI: IDE base address fixup for %s\n", pci_name(d));
449 for(i=0; i<4; i++) {
450 struct resource *r = &d->resource[i];
451 if ((r->start & ~0x80) == 0x374) {
452 r->start |= 2;
453 r->end = r->start;
454 }
455 }
456}
457DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
458
459void __init pcibios_init(void)
460{
461 static struct resource galio,galmem;
462
463 /* Allocate the registers used by the Galileo */
464 galio.flags = IORESOURCE_IO;
465 galio.name = "Galileo GT64011";
466 galmem.flags = IORESOURCE_MEM|IORESOURCE_PREFETCH;
467 galmem.name = "Galileo GT64011 DRAM";
468
469 allocate_resource(&ioport_resource, &galio, 256,
470 GT64111_IO_BASE_ADDRESS,GT64111_IO_BASE_ADDRESS+256, 256, NULL, NULL);
471 allocate_resource(&iomem_resource, &galmem,PCI_DRAM_SIZE,
472 PHYSADDR(PCI_DRAM_BASE), PHYSADDR(PCI_DRAM_BASE)+PCI_DRAM_SIZE,
473 PCI_DRAM_SIZE, NULL, NULL);
474
475 /* ok, do the scan man */
476 pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
477
478 pci_assign_unassigned_resources();
479 pci_fixup_irqs(no_swizzle, map_od_irq);
480
481#ifdef TEST_DRAM
482 printk("Testing PCI DRAM - ");
483 if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
484 printk("Passed\n");
485 }else {
486 printk("FAILED\n");
487 }
488#endif
489
490}
491
492char * __init pcibios_setup(char *str)
493{
494 return str;
495}
496
497
498
499int pcibios_enable_device(struct pci_dev *dev)
500{
501
502 u16 cmd, old_cmd;
503 int idx;
504 struct resource *r;
505
506 pci_read_config_word(dev, PCI_COMMAND, &cmd);
507 old_cmd = cmd;
508 for (idx = 0; idx < 6; idx++) {
509 r = dev->resource + idx;
510 if (!r->start && r->end) {
511 printk(KERN_ERR
512 "PCI: Device %s not available because"
513 " of resource collisions\n",
514 pci_name(dev));
515 return -EINVAL;
516 }
517 if (r->flags & IORESOURCE_IO)
518 cmd |= PCI_COMMAND_IO;
519 if (r->flags & IORESOURCE_MEM)
520 cmd |= PCI_COMMAND_MEMORY;
521 }
522 if (cmd != old_cmd) {
523 printk("PCI: enabling device %s (%04x -> %04x)\n",
524 pci_name(dev), old_cmd, cmd);
525 pci_write_config_word(dev, PCI_COMMAND, cmd);
526 }
527 return 0;
528
529}
530
531/* We should do some optimisation work here I think. Ok for now though */
532void __init pcibios_fixup_bus(struct pci_bus *bus)
533{
534
535}
536
537void pcibios_align_resource(void *data, struct resource *res,
538 resource_size_t size)
539{
540}
541
542void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
543 struct resource *res, int resource)
544{
545
546 unsigned long where, size;
547 u32 reg;
548
549
550 printk("PCI: Assigning %3s %08lx to %s\n",
551 res->flags & IORESOURCE_IO ? "IO" : "MEM",
552 res->start, dev->name);
553
554 where = PCI_BASE_ADDRESS_0 + resource * 4;
555 size = res->end - res->start;
556
557 pci_read_config_dword(dev, where, &reg);
558 reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
559 pci_write_config_dword(dev, where, reg);
560}
561
562
563void __init pcibios_update_irq(struct pci_dev *dev, int irq)
564{
565 printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
566 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
567}
568
569/*
570 * If we set up a device for bus mastering, we need to check the latency
571 * timer as certain crappy BIOSes forget to set it properly.
572 */
573unsigned int pcibios_max_latency = 255;
574
575void pcibios_set_master(struct pci_dev *dev)
576{
577 u8 lat;
578 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
579 if (lat < 16)
580 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
581 else if (lat > pcibios_max_latency)
582 lat = pcibios_max_latency;
583 else
584 return;
585 printk("PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
586 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
587}
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