diff options
Diffstat (limited to 'arch/sh/boards/mach-se/7780/irq.c')
-rw-r--r-- | arch/sh/boards/mach-se/7780/irq.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c index 66ad292c9fc3..b8d43b638fcf 100644 --- a/arch/sh/boards/mach-se/7780/irq.c +++ b/arch/sh/boards/mach-se/7780/irq.c | |||
@@ -12,10 +12,13 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | #include <asm/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <asm/io.h> | 16 | #include <linux/io.h> |
17 | #include <mach-se/mach/se7780.h> | 17 | #include <mach-se/mach/se7780.h> |
18 | 18 | ||
19 | #define INTC_BASE 0xffd00000 | ||
20 | #define INTC_ICR1 (INTC_BASE+0x1c) | ||
21 | |||
19 | /* | 22 | /* |
20 | * Initialize IRQ setting | 23 | * Initialize IRQ setting |
21 | */ | 24 | */ |
@@ -43,4 +46,24 @@ void __init init_se7780_IRQ(void) | |||
43 | ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); | 46 | ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); |
44 | 47 | ||
45 | plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ | 48 | plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ |
49 | |||
50 | /* ICR1: detect low level(for 2ndcut) */ | ||
51 | ctrl_outl(0xAAAA0000, INTC_ICR1); | ||
52 | |||
53 | /* | ||
54 | * FPGA PCISEL register initialize | ||
55 | * | ||
56 | * CPU || SLOT1 | SLOT2 | S-ATA | USB | ||
57 | * ------------------------------------- | ||
58 | * INTA || INTA | INTD | -- | INTB | ||
59 | * ------------------------------------- | ||
60 | * INTB || INTB | INTA | -- | INTC | ||
61 | * ------------------------------------- | ||
62 | * INTC || INTC | INTB | INTA | -- | ||
63 | * ------------------------------------- | ||
64 | * INTD || INTD | INTC | -- | INTA | ||
65 | * ------------------------------------- | ||
66 | */ | ||
67 | ctrl_outw(0x0013, FPGA_PCI_INTSEL1); | ||
68 | ctrl_outw(0xE402, FPGA_PCI_INTSEL2); | ||
46 | } | 69 | } |