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-rw-r--r--arch/sh/boards/mach-microdev/Makefile5
-rw-r--r--arch/sh/boards/mach-microdev/fdc37c93xapm.c160
-rw-r--r--arch/sh/boards/mach-microdev/irq.c36
-rw-r--r--arch/sh/boards/mach-microdev/led.c101
-rw-r--r--arch/sh/boards/mach-microdev/setup.c196
5 files changed, 174 insertions, 324 deletions
diff --git a/arch/sh/boards/mach-microdev/Makefile b/arch/sh/boards/mach-microdev/Makefile
index 1387dd6c85eb..4e3588e8806b 100644
--- a/arch/sh/boards/mach-microdev/Makefile
+++ b/arch/sh/boards/mach-microdev/Makefile
@@ -2,7 +2,4 @@
2# Makefile for the SuperH MicroDev specific parts of the kernel 2# Makefile for the SuperH MicroDev specific parts of the kernel
3# 3#
4 4
5obj-y := setup.o irq.o io.o 5obj-y := setup.o irq.o io.o fdc37c93xapm.o
6
7obj-$(CONFIG_HEARTBEAT) += led.o
8
diff --git a/arch/sh/boards/mach-microdev/fdc37c93xapm.c b/arch/sh/boards/mach-microdev/fdc37c93xapm.c
new file mode 100644
index 000000000000..458a7cf5fb46
--- /dev/null
+++ b/arch/sh/boards/mach-microdev/fdc37c93xapm.c
@@ -0,0 +1,160 @@
1/*
2 *
3 * Setup for the SMSC FDC37C93xAPM
4 *
5 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
6 * Copyright (C) 2003, 2004 SuperH, Inc.
7 * Copyright (C) 2004, 2005 Paul Mundt
8 *
9 * SuperH SH4-202 MicroDev board support.
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 */
14#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <mach/microdev.h>
19
20#define SMSC_CONFIG_PORT_ADDR (0x3F0)
21#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
22#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
23
24#define SMSC_ENTER_CONFIG_KEY 0x55
25#define SMSC_EXIT_CONFIG_KEY 0xaa
26
27#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
28#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
29#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
30#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
31#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
32#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
33#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
34#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
35#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
36#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
37
38#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
39#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
40#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
41#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
42#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
43#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
44#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
45
46#define SMSC_READ_INDEXED(index) ({ \
47 outb((index), SMSC_INDEX_PORT_ADDR); \
48 inb(SMSC_DATA_PORT_ADDR); })
49#define SMSC_WRITE_INDEXED(val, index) ({ \
50 outb((index), SMSC_INDEX_PORT_ADDR); \
51 outb((val), SMSC_DATA_PORT_ADDR); })
52
53#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
54#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
55#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
56#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
57
58#define SERIAL1_PRIMARY_BASE 0x03f8
59#define SERIAL2_PRIMARY_BASE 0x02f8
60
61#define MSB(x) ( (x) >> 8 )
62#define LSB(x) ( (x) & 0xff )
63
64 /* General-Purpose base address on CPU-board FPGA */
65#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
66
67static int __init smsc_superio_setup(void)
68{
69
70 unsigned char devid, devrev;
71
72 /* Initially the chip is in run state */
73 /* Put it into configuration state */
74 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
75
76 /* Read device ID info */
77 devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
78 devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
79
80 if ((devid == 0x30) && (devrev == 0x01))
81 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
82 else
83 return -ENODEV;
84
85 /* Select the keyboard device */
86 SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
87 /* enable it */
88 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
89 /* enable the interrupts */
90 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
91 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
92
93 /* Select the Serial #1 device */
94 SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
95 /* enable it */
96 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
97 /* program with port addresses */
98 SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
99 SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
100 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
101 /* enable the interrupts */
102 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
103
104 /* Select the Serial #2 device */
105 SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
106 /* enable it */
107 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
108 /* program with port addresses */
109 SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
110 SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
111 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
112 /* enable the interrupts */
113 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
114
115 /* Select the IDE#1 device */
116 SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
117 /* enable it */
118 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
119 /* program with port addresses */
120 SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
121 SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
122 SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
123 SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
124 SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
125 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
126 /* select the interrupt */
127 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
128
129 /* Select the IDE#2 device */
130 SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
131 /* enable it */
132 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
133 /* program with port addresses */
134 SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
135 SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
136 SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
137 SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
138 /* select the interrupt */
139 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
140
141 /* Select the configuration registers */
142 SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
143 /* enable the appropriate GPIO pins for IDE functionality:
144 * bit[0] In/Out 1==input; 0==output
145 * bit[1] Polarity 1==invert; 0==no invert
146 * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
147 * bit[3:4] Function Select 00==original; 01==Alternate Function #1
148 */
149 SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
150 SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
151 SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
152 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
153 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
154
155 /* Exit the configuration state */
156 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
157
158 return 0;
159}
160device_initcall(smsc_superio_setup);
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index 702753cbd28f..b551963579c1 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -67,27 +67,13 @@ static const struct {
67 67
68static void enable_microdev_irq(unsigned int irq); 68static void enable_microdev_irq(unsigned int irq);
69static void disable_microdev_irq(unsigned int irq); 69static void disable_microdev_irq(unsigned int irq);
70
71 /* shutdown is same as "disable" */
72#define shutdown_microdev_irq disable_microdev_irq
73
74static void mask_and_ack_microdev(unsigned int); 70static void mask_and_ack_microdev(unsigned int);
75static void end_microdev_irq(unsigned int irq);
76
77static unsigned int startup_microdev_irq(unsigned int irq)
78{
79 enable_microdev_irq(irq);
80 return 0; /* never anything pending */
81}
82 71
83static struct hw_interrupt_type microdev_irq_type = { 72static struct irq_chip microdev_irq_type = {
84 .typename = "MicroDev-IRQ", 73 .name = "MicroDev-IRQ",
85 .startup = startup_microdev_irq, 74 .unmask = enable_microdev_irq,
86 .shutdown = shutdown_microdev_irq, 75 .mask = disable_microdev_irq,
87 .enable = enable_microdev_irq,
88 .disable = disable_microdev_irq,
89 .ack = mask_and_ack_microdev, 76 .ack = mask_and_ack_microdev,
90 .end = end_microdev_irq
91}; 77};
92 78
93static void disable_microdev_irq(unsigned int irq) 79static void disable_microdev_irq(unsigned int irq)
@@ -130,11 +116,11 @@ static void enable_microdev_irq(unsigned int irq)
130 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); 116 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
131} 117}
132 118
133 /* This functions sets the desired irq handler to be a MicroDev type */ 119/* This function sets the desired irq handler to be a MicroDev type */
134static void __init make_microdev_irq(unsigned int irq) 120static void __init make_microdev_irq(unsigned int irq)
135{ 121{
136 disable_irq_nosync(irq); 122 disable_irq_nosync(irq);
137 irq_desc[irq].chip = &microdev_irq_type; 123 set_irq_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
138 disable_microdev_irq(irq); 124 disable_microdev_irq(irq);
139} 125}
140 126
@@ -143,17 +129,11 @@ static void mask_and_ack_microdev(unsigned int irq)
143 disable_microdev_irq(irq); 129 disable_microdev_irq(irq);
144} 130}
145 131
146static void end_microdev_irq(unsigned int irq)
147{
148 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
149 enable_microdev_irq(irq);
150}
151
152extern void __init init_microdev_irq(void) 132extern void __init init_microdev_irq(void)
153{ 133{
154 int i; 134 int i;
155 135
156 /* disable interrupts on the FPGA INTC register */ 136 /* disable interrupts on the FPGA INTC register */
157 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG); 137 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
158 138
159 for (i = 0; i < NUM_EXTERNAL_IRQS; i++) 139 for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
@@ -179,5 +159,3 @@ extern void microdev_print_fpga_intc_status(void)
179 printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria); 159 printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
180 printk("-------------------------------------------------------------------------------\n"); 160 printk("-------------------------------------------------------------------------------\n");
181} 161}
182
183
diff --git a/arch/sh/boards/mach-microdev/led.c b/arch/sh/boards/mach-microdev/led.c
deleted file mode 100644
index 36e54b47a752..000000000000
--- a/arch/sh/boards/mach-microdev/led.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * linux/arch/sh/boards/superh/microdev/led.c
3 *
4 * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com>
5 * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 */
11
12#include <asm/io.h>
13
14#define LED_REGISTER 0xa6104d20
15
16static void mach_led_d9(int value)
17{
18 unsigned long reg;
19 reg = ctrl_inl(LED_REGISTER);
20 reg &= ~1;
21 reg |= (value & 1);
22 ctrl_outl(reg, LED_REGISTER);
23 return;
24}
25
26static void mach_led_d10(int value)
27{
28 unsigned long reg;
29 reg = ctrl_inl(LED_REGISTER);
30 reg &= ~2;
31 reg |= ((value & 1) << 1);
32 ctrl_outl(reg, LED_REGISTER);
33 return;
34}
35
36
37#ifdef CONFIG_HEARTBEAT
38#include <linux/sched.h>
39
40static unsigned char banner_table[] = {
41 0x11, 0x01, 0x11, 0x01, 0x11, 0x03,
42 0x11, 0x01, 0x11, 0x01, 0x13, 0x03,
43 0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03,
44 0x11, 0x03,
45 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
46 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07,
47 0x13, 0x01, 0x13, 0x03,
48 0x11, 0x01, 0x11, 0x03,
49 0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
50 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
51 0x13, 0x01, 0x13, 0x01, 0x13, 0x03,
52 0x13, 0x01, 0x11, 0x01, 0x11, 0x03,
53 0x11, 0x03,
54 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07,
55 0xff
56};
57
58static void banner(void)
59{
60 static int pos = 0;
61 static int count = 0;
62
63 if (count) {
64 count--;
65 } else {
66 int val = banner_table[pos];
67 if (val == 0xff) {
68 pos = 0;
69 val = banner_table[pos];
70 }
71 pos++;
72 mach_led_d10((val >> 4) & 1);
73 count = 10 * (val & 0xf);
74 }
75}
76
77/* From heartbeat_harp in the stboards directory */
78/* acts like an actual heart beat -- ie thump-thump-pause... */
79void microdev_heartbeat(void)
80{
81 static unsigned cnt = 0, period = 0, dist = 0;
82
83 if (cnt == 0 || cnt == dist)
84 mach_led_d9(1);
85 else if (cnt == 7 || cnt == dist+7)
86 mach_led_d9(0);
87
88 if (++cnt > period) {
89 cnt = 0;
90 /* The hyperbolic function below modifies the heartbeat period
91 * length in dependency of the current (5min) load. It goes
92 * through the points f(0)=126, f(1)=86, f(5)=51,
93 * f(inf)->30. */
94 period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
95 dist = period / 4;
96 }
97
98 banner();
99}
100
101#endif
diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index a9202fe3cb59..d1df2a4fb9b8 100644
--- a/arch/sh/boards/mach-microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
@@ -17,70 +17,12 @@
17#include <mach/microdev.h> 17#include <mach/microdev.h>
18#include <asm/io.h> 18#include <asm/io.h>
19#include <asm/machvec.h> 19#include <asm/machvec.h>
20 20#include <asm/sizes.h>
21extern void microdev_heartbeat(void);
22
23
24/****************************************************************************/
25
26
27 /*
28 * Setup for the SMSC FDC37C93xAPM
29 */
30#define SMSC_CONFIG_PORT_ADDR (0x3F0)
31#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
32#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
33
34#define SMSC_ENTER_CONFIG_KEY 0x55
35#define SMSC_EXIT_CONFIG_KEY 0xaa
36
37#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
38#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
39#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
40#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
41#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
42#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
43#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
44#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
45#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
46#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
47
48#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
49#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
50#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
51#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
52#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
53#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
54#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
55
56#define SMSC_READ_INDEXED(index) ({ \
57 outb((index), SMSC_INDEX_PORT_ADDR); \
58 inb(SMSC_DATA_PORT_ADDR); })
59#define SMSC_WRITE_INDEXED(val, index) ({ \
60 outb((index), SMSC_INDEX_PORT_ADDR); \
61 outb((val), SMSC_DATA_PORT_ADDR); })
62
63#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
64#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
65#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
66#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
67
68#define SERIAL1_PRIMARY_BASE 0x03f8
69#define SERIAL2_PRIMARY_BASE 0x02f8
70
71#define MSB(x) ( (x) >> 8 )
72#define LSB(x) ( (x) & 0xff )
73
74 /* General-Purpose base address on CPU-board FPGA */
75#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
76
77 /* assume a Keyboard Controller is present */
78int microdev_kbd_controller_present = 1;
79 21
80static struct resource smc91x_resources[] = { 22static struct resource smc91x_resources[] = {
81 [0] = { 23 [0] = {
82 .start = 0x300, 24 .start = 0x300,
83 .end = 0x300 + 0x0001000 - 1, 25 .end = 0x300 + SZ_4K - 1,
84 .flags = IORESOURCE_MEM, 26 .flags = IORESOURCE_MEM,
85 }, 27 },
86 [1] = { 28 [1] = {
@@ -97,7 +39,6 @@ static struct platform_device smc91x_device = {
97 .resource = smc91x_resources, 39 .resource = smc91x_resources,
98}; 40};
99 41
100#ifdef CONFIG_FB_S1D13XXX
101static struct s1d13xxxfb_regval s1d13806_initregs[] = { 42static struct s1d13xxxfb_regval s1d13806_initregs[] = {
102 { S1DREG_MISC, 0x00 }, 43 { S1DREG_MISC, 0x00 },
103 { S1DREG_COM_DISP_MODE, 0x00 }, 44 { S1DREG_COM_DISP_MODE, 0x00 },
@@ -216,12 +157,12 @@ static struct s1d13xxxfb_pdata s1d13806_platform_data = {
216static struct resource s1d13806_resources[] = { 157static struct resource s1d13806_resources[] = {
217 [0] = { 158 [0] = {
218 .start = 0x07200000, 159 .start = 0x07200000,
219 .end = 0x07200000 + 0x00200000 - 1, 160 .end = 0x07200000 + SZ_2M - 1,
220 .flags = IORESOURCE_MEM, 161 .flags = IORESOURCE_MEM,
221 }, 162 },
222 [1] = { 163 [1] = {
223 .start = 0x07000000, 164 .start = 0x07000000,
224 .end = 0x07000000 + 0x00200000 - 1, 165 .end = 0x07000000 + SZ_2M - 1,
225 .flags = IORESOURCE_MEM, 166 .flags = IORESOURCE_MEM,
226 }, 167 },
227}; 168};
@@ -236,145 +177,24 @@ static struct platform_device s1d13806_device = {
236 .platform_data = &s1d13806_platform_data, 177 .platform_data = &s1d13806_platform_data,
237 }, 178 },
238}; 179};
239#endif
240 180
241static struct platform_device *microdev_devices[] __initdata = { 181static struct platform_device *microdev_devices[] __initdata = {
242 &smc91x_device, 182 &smc91x_device,
243#ifdef CONFIG_FB_S1D13XXX
244 &s1d13806_device, 183 &s1d13806_device,
245#endif
246}; 184};
247 185
248static int __init microdev_devices_setup(void) 186static int __init microdev_devices_setup(void)
249{ 187{
250 return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); 188 return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
251} 189}
252 190device_initcall(microdev_devices_setup);
253/*
254 * Setup for the SMSC FDC37C93xAPM
255 */
256static int __init smsc_superio_setup(void)
257{
258
259 unsigned char devid, devrev;
260
261 /* Initially the chip is in run state */
262 /* Put it into configuration state */
263 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
264
265 /* Read device ID info */
266 devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
267 devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
268 if ( (devid==0x30) && (devrev==0x01) )
269 {
270 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
271 }
272 else
273 { /* not the device identity we expected */
274 printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
275 devid, devrev);
276 /* inform the keyboard driver that we have no keyboard controller */
277 microdev_kbd_controller_present = 0;
278 /* little point in doing anything else in this functon */
279 return 0;
280 }
281
282 /* Select the keyboard device */
283 SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
284 /* enable it */
285 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
286 /* enable the interrupts */
287 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
288 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
289
290 /* Select the Serial #1 device */
291 SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
292 /* enable it */
293 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
294 /* program with port addresses */
295 SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
296 SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
297 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
298 /* enable the interrupts */
299 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
300
301 /* Select the Serial #2 device */
302 SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
303 /* enable it */
304 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
305 /* program with port addresses */
306 SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
307 SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
308 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
309 /* enable the interrupts */
310 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
311
312 /* Select the IDE#1 device */
313 SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
314 /* enable it */
315 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
316 /* program with port addresses */
317 SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
318 SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
319 SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
320 SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
321 SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
322 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
323 /* select the interrupt */
324 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
325
326 /* Select the IDE#2 device */
327 SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
328 /* enable it */
329 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
330 /* program with port addresses */
331 SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
332 SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
333 SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
334 SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
335 /* select the interrupt */
336 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
337
338 /* Select the configuration registers */
339 SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
340 /* enable the appropriate GPIO pins for IDE functionality:
341 * bit[0] In/Out 1==input; 0==output
342 * bit[1] Polarity 1==invert; 0==no invert
343 * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
344 * bit[3:4] Function Select 00==original; 01==Alternate Function #1
345 */
346 SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
347 SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
348 SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
349 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
350 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
351
352 /* Exit the configuration state */
353 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
354
355 return 0;
356}
357
358static void __init microdev_setup(char **cmdline_p)
359{
360 int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
361 const int fpgaRevision = *fpgaRevisionRegister;
362 int * const CacheControlRegister = (int*)CCR;
363
364 device_initcall(microdev_devices_setup);
365 device_initcall(smsc_superio_setup);
366
367 printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
368 get_system_type(), fpgaRevision, *CacheControlRegister);
369}
370 191
371/* 192/*
372 * The Machine Vector 193 * The Machine Vector
373 */ 194 */
374static struct sh_machine_vector mv_sh4202_microdev __initmv = { 195static struct sh_machine_vector mv_sh4202_microdev __initmv = {
375 .mv_name = "SH4-202 MicroDev", 196 .mv_name = "SH4-202 MicroDev",
376 .mv_setup = microdev_setup, 197 .mv_nr_irqs = 72,
377 .mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */
378 198
379 .mv_inb = microdev_inb, 199 .mv_inb = microdev_inb,
380 .mv_inw = microdev_inw, 200 .mv_inw = microdev_inw,
@@ -398,8 +218,4 @@ static struct sh_machine_vector mv_sh4202_microdev __initmv = {
398 .mv_outsl = microdev_outsl, 218 .mv_outsl = microdev_outsl,
399 219
400 .mv_init_irq = init_microdev_irq, 220 .mv_init_irq = init_microdev_irq,
401
402#ifdef CONFIG_HEARTBEAT
403 .mv_heartbeat = microdev_heartbeat,
404#endif
405}; 221};
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 15:02:09 -0400