diff options
Diffstat (limited to 'arch/sh/boards/mach-hp6xx/pm.c')
-rw-r--r-- | arch/sh/boards/mach-hp6xx/pm.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c index d936c1af7620..4499a3749d40 100644 --- a/arch/sh/boards/mach-hp6xx/pm.c +++ b/arch/sh/boards/mach-hp6xx/pm.c | |||
@@ -53,17 +53,17 @@ static void pm_enter(void) | |||
53 | sh_wdt_write_cnt(0); | 53 | sh_wdt_write_cnt(0); |
54 | 54 | ||
55 | /* disable PLL1 */ | 55 | /* disable PLL1 */ |
56 | frqcr = ctrl_inw(FRQCR); | 56 | frqcr = __raw_readw(FRQCR); |
57 | frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY); | 57 | frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY); |
58 | ctrl_outw(frqcr, FRQCR); | 58 | __raw_writew(frqcr, FRQCR); |
59 | 59 | ||
60 | /* enable standby */ | 60 | /* enable standby */ |
61 | stbcr = ctrl_inb(STBCR); | 61 | stbcr = __raw_readb(STBCR); |
62 | ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); | 62 | __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); |
63 | 63 | ||
64 | /* set self-refresh */ | 64 | /* set self-refresh */ |
65 | mcr = ctrl_inw(MCR); | 65 | mcr = __raw_readw(MCR); |
66 | ctrl_outw(mcr & ~MCR_RFSH, MCR); | 66 | __raw_writew(mcr & ~MCR_RFSH, MCR); |
67 | 67 | ||
68 | /* set interrupt handler */ | 68 | /* set interrupt handler */ |
69 | asm volatile("stc vbr, %0" : "=r" (vbr_old)); | 69 | asm volatile("stc vbr, %0" : "=r" (vbr_old)); |
@@ -73,8 +73,8 @@ static void pm_enter(void) | |||
73 | &wakeup_start, &wakeup_end - &wakeup_start); | 73 | &wakeup_start, &wakeup_end - &wakeup_start); |
74 | asm volatile("ldc %0, vbr" : : "r" (vbr_new)); | 74 | asm volatile("ldc %0, vbr" : : "r" (vbr_new)); |
75 | 75 | ||
76 | ctrl_outw(0, RTCNT); | 76 | __raw_writew(0, RTCNT); |
77 | ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR); | 77 | __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); |
78 | 78 | ||
79 | cpu_sleep(); | 79 | cpu_sleep(); |
80 | 80 | ||
@@ -83,14 +83,14 @@ static void pm_enter(void) | |||
83 | free_page(vbr_new); | 83 | free_page(vbr_new); |
84 | 84 | ||
85 | /* enable PLL1 */ | 85 | /* enable PLL1 */ |
86 | frqcr = ctrl_inw(FRQCR); | 86 | frqcr = __raw_readw(FRQCR); |
87 | frqcr |= FRQCR_PSTBY; | 87 | frqcr |= FRQCR_PSTBY; |
88 | ctrl_outw(frqcr, FRQCR); | 88 | __raw_writew(frqcr, FRQCR); |
89 | udelay(50); | 89 | udelay(50); |
90 | frqcr |= FRQCR_PLLEN; | 90 | frqcr |= FRQCR_PLLEN; |
91 | ctrl_outw(frqcr, FRQCR); | 91 | __raw_writew(frqcr, FRQCR); |
92 | 92 | ||
93 | ctrl_outb(stbcr, STBCR); | 93 | __raw_writeb(stbcr, STBCR); |
94 | 94 | ||
95 | clear_bl_bit(); | 95 | clear_bl_bit(); |
96 | } | 96 | } |
@@ -115,21 +115,21 @@ static int hp6x0_pm_enter(suspend_state_t state) | |||
115 | outw(hd64461_stbcr, HD64461_STBCR); | 115 | outw(hd64461_stbcr, HD64461_STBCR); |
116 | #endif | 116 | #endif |
117 | 117 | ||
118 | ctrl_outb(0x1f, DACR); | 118 | __raw_writeb(0x1f, DACR); |
119 | 119 | ||
120 | stbcr = ctrl_inb(STBCR); | 120 | stbcr = __raw_readb(STBCR); |
121 | ctrl_outb(0x01, STBCR); | 121 | __raw_writeb(0x01, STBCR); |
122 | 122 | ||
123 | stbcr2 = ctrl_inb(STBCR2); | 123 | stbcr2 = __raw_readb(STBCR2); |
124 | ctrl_outb(0x7f , STBCR2); | 124 | __raw_writeb(0x7f , STBCR2); |
125 | 125 | ||
126 | outw(0xf07f, HD64461_SCPUCR); | 126 | outw(0xf07f, HD64461_SCPUCR); |
127 | 127 | ||
128 | pm_enter(); | 128 | pm_enter(); |
129 | 129 | ||
130 | outw(0, HD64461_SCPUCR); | 130 | outw(0, HD64461_SCPUCR); |
131 | ctrl_outb(stbcr, STBCR); | 131 | __raw_writeb(stbcr, STBCR); |
132 | ctrl_outb(stbcr2, STBCR2); | 132 | __raw_writeb(stbcr2, STBCR2); |
133 | 133 | ||
134 | #ifdef CONFIG_HD64461_ENABLER | 134 | #ifdef CONFIG_HD64461_ENABLER |
135 | hd64461_stbcr = inw(HD64461_STBCR); | 135 | hd64461_stbcr = inw(HD64461_STBCR); |