5 files changed, 41 insertions, 2 deletions

diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c
index aac88c2f3db9..5255bd80aa6b 100644
--- a/arch/ppc/kernel/setup.c
+++ b/arch/ppc/kernel/setup.c
@@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
          * Identify the CPU type and fix up code sections
          * that depend on which cpu we have.
          */
+#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
+        /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
+         * identical PVRs and there is no reliable way to check for the FPU
+         */
+        spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
+#else
         spec = identify_cpu(offset, mfspr(SPRN_PVR));
+#endif
         do_feature_fixups(spec->cpu_features,
                           PTRRELOC(&__start___ftr_fixup),
                           PTRRELOC(&__stop___ftr_fixup));
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index 390dd1995c2a..dd898d32480e 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -561,7 +561,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
                  * That means the zeroed TLB has to be invalidated
                  * whenever a page miss occurs.
                  */
-                _tlbie(address);
+                _tlbie(address, 0 /* 8xx doesn't care about PID */);
 #endif
                 if (!PageReserved(page)
                     && !test_bit(PG_arch_1, &page->flags)) {
diff --git a/arch/ppc/mm/mmu_decl.h b/arch/ppc/mm/mmu_decl.h
index f1d4f2109a99..b298b60c202f 100644
--- a/arch/ppc/mm/mmu_decl.h
+++ b/arch/ppc/mm/mmu_decl.h
@@ -49,7 +49,7 @@ extern unsigned int num_tlbcam_entries;
  * architectures.  -- Dan
  */
 #if defined(CONFIG_8xx)
-#define flush_HPTE(X, va, pg)   _tlbie(va)
+#define flush_HPTE(X, va, pg)   _tlbie(va, 0 /* 8xx doesn't care about PID */)
 #define MMU_init_hw()           do { } while(0)
 #define mmu_mapin_ram()         (0UL)
 
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
index a83b0baea011..66a44ff0d926 100644
--- a/arch/ppc/platforms/4xx/yucca.c
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -211,6 +211,7 @@ static void __init yucca_setup_pcie_fpga_rootpoint(int port)
                 break;
 
         default:
+                iounmap(pcie_reg_fpga_base);
                 return;
         }
 
diff --git a/arch/ppc/syslib/virtex_devices.c b/arch/ppc/syslib/virtex_devices.c
index ace4ec08de51..f658ff3b3890 100644
--- a/arch/ppc/syslib/virtex_devices.c
+++ b/arch/ppc/syslib/virtex_devices.c
@@ -87,6 +87,29 @@
         }, \
 }
 
+#define XPAR_AC97_CONTROLLER_REFERENCE(num) { \
+        .name = "ml403_ac97cr", \
+        .id = num, \
+        .num_resources = 3, \
+        .resource = (struct resource[]) { \
+                { \
+                        .start = XPAR_OPB_AC97_CONTROLLER_REF_##num##_BASEADDR, \
+                        .end = XPAR_OPB_AC97_CONTROLLER_REF_##num##_HIGHADDR, \
+                        .flags = IORESOURCE_MEM, \
+                }, \
+                { \
+                        .start = XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_##num##_PLAYBACK_INTERRUPT_INTR, \
+                        .end = XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_##num##_PLAYBACK_INTERRUPT_INTR, \
+                        .flags = IORESOURCE_IRQ, \
+                }, \
+                { \
+                        .start = XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_##num##_RECORD_INTERRUPT_INTR, \
+                        .end = XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_##num##_RECORD_INTERRUPT_INTR, \
+                        .flags = IORESOURCE_IRQ, \
+                }, \
+        }, \
+}
+
 /* UART 8250 driver platform data table */
 struct plat_serial8250_port virtex_serial_platform_data[] = {
 #if defined(XPAR_UARTNS550_0_BASEADDR)
@@ -173,6 +196,14 @@ struct platform_device virtex_platform_devices[] = {
 #if defined(XPAR_TFT_3_BASEADDR)
         XPAR_TFT(3),
 #endif
+
+        /* AC97 Controller Reference instances */
+#if defined(XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR)
+        XPAR_AC97_CONTROLLER_REFERENCE(0),
+#endif
+#if defined(XPAR_OPB_AC97_CONTROLLER_REF_1_BASEADDR)
+        XPAR_AC97_CONTROLLER_REFERENCE(1),
+#endif
 };
 
 /* Early serial support functions */