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-rw-r--r--arch/ppc/4xx_io/serial_sicc.c17
-rw-r--r--arch/ppc/8260_io/fcc_enet.c3
-rw-r--r--arch/ppc/8xx_io/cs4218_tdm.c3
-rw-r--r--arch/ppc/Kconfig18
-rw-r--r--arch/ppc/boot/simple/Makefile27
-rw-r--r--arch/ppc/boot/simple/misc.c16
-rw-r--r--arch/ppc/boot/simple/openbios.c106
-rw-r--r--arch/ppc/configs/ev64360_defconfig73
-rw-r--r--arch/ppc/configs/stx_gp3_defconfig86
-rw-r--r--arch/ppc/kernel/Makefile1
-rw-r--r--arch/ppc/kernel/head_44x.S4
-rw-r--r--arch/ppc/kernel/rio.c52
-rw-r--r--arch/ppc/platforms/4xx/Kconfig19
-rw-r--r--arch/ppc/platforms/4xx/Makefile2
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c2
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h64
-rw-r--r--arch/ppc/platforms/4xx/ebony.h4
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.c148
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.h66
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c7
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h67
-rw-r--r--arch/ppc/platforms/4xx/walnut.c2
-rw-r--r--arch/ppc/platforms/4xx/walnut.h67
-rw-r--r--arch/ppc/platforms/4xx/yucca.c395
-rw-r--r--arch/ppc/platforms/4xx/yucca.h111
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.c10
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c14
-rw-r--r--arch/ppc/platforms/ev64360.c12
-rw-r--r--arch/ppc/syslib/Makefile4
-rw-r--r--arch/ppc/syslib/ibm440sp_common.c4
-rw-r--r--arch/ppc/syslib/ibm44x_common.c12
-rw-r--r--arch/ppc/syslib/ppc405_pci.c7
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.c442
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.h149
-rw-r--r--arch/ppc/syslib/ppc4xx_pic.c37
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.c938
-rw-r--r--arch/ppc/syslib/ppc85xx_rio.h21
-rw-r--r--arch/ppc/syslib/ppc_sys.c1
-rw-r--r--arch/ppc/syslib/prom.c6
39 files changed, 2789 insertions, 228 deletions
diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c
index e95c48d57571..84d96b857e4a 100644
--- a/arch/ppc/4xx_io/serial_sicc.c
+++ b/arch/ppc/4xx_io/serial_sicc.c
@@ -1145,8 +1145,8 @@ static int set_serial_info(struct SICC_info *info,
1145 info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | 1145 info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) |
1146 (info->flags & ASYNC_INTERNAL_FLAGS)); 1146 (info->flags & ASYNC_INTERNAL_FLAGS));
1147 state->custom_divisor = new_serial.custom_divisor; 1147 state->custom_divisor = new_serial.custom_divisor;
1148 state->close_delay = new_serial.close_delay * HZ / 100; 1148 state->close_delay = msecs_to_jiffies(10 * new_serial.close_delay);
1149 state->closing_wait = new_serial.closing_wait * HZ / 100; 1149 state->closing_wait = msecs_to_jiffies(10 * new_serial.closing_wait);
1150 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; 1150 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1151 port->fifosize = new_serial.xmit_fifo_size; 1151 port->fifosize = new_serial.xmit_fifo_size;
1152 1152
@@ -1465,10 +1465,8 @@ static void siccuart_close(struct tty_struct *tty, struct file *filp)
1465 info->event = 0; 1465 info->event = 0;
1466 info->tty = NULL; 1466 info->tty = NULL;
1467 if (info->blocked_open) { 1467 if (info->blocked_open) {
1468 if (info->state->close_delay) { 1468 if (info->state->close_delay)
1469 set_current_state(TASK_INTERRUPTIBLE); 1469 schedule_timeout_interruptible(info->state->close_delay);
1470 schedule_timeout(info->state->close_delay);
1471 }
1472 wake_up_interruptible(&info->open_wait); 1470 wake_up_interruptible(&info->open_wait);
1473 } 1471 }
1474 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); 1472 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
@@ -1496,7 +1494,7 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout)
1496 * Note: we have to use pretty tight timings here to satisfy 1494 * Note: we have to use pretty tight timings here to satisfy
1497 * the NIST-PCTS. 1495 * the NIST-PCTS.
1498 */ 1496 */
1499 char_time = (info->timeout - HZ/50) / info->port->fifosize; 1497 char_time = (info->timeout - msecs_to_jiffies(20)) / info->port->fifosize;
1500 char_time = char_time / 5; 1498 char_time = char_time / 5;
1501 if (char_time == 0) 1499 if (char_time == 0)
1502 char_time = 1; 1500 char_time = 1;
@@ -1521,8 +1519,7 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout)
1521 tty->index, jiffies, 1519 tty->index, jiffies,
1522 expire, char_time); 1520 expire, char_time);
1523 while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) { 1521 while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) {
1524 set_current_state(TASK_INTERRUPTIBLE); 1522 schedule_timeout_interruptible(char_time);
1525 schedule_timeout(char_time);
1526 if (signal_pending(current)) 1523 if (signal_pending(current))
1527 break; 1524 break;
1528 if (timeout && time_after(jiffies, expire)) 1525 if (timeout && time_after(jiffies, expire))
@@ -1773,7 +1770,7 @@ int __init siccuart_init(void)
1773 for (i = 0; i < SERIAL_SICC_NR; i++) { 1770 for (i = 0; i < SERIAL_SICC_NR; i++) {
1774 struct SICC_state *state = sicc_state + i; 1771 struct SICC_state *state = sicc_state + i;
1775 state->line = i; 1772 state->line = i;
1776 state->close_delay = 5 * HZ / 10; 1773 state->close_delay = msecs_to_jiffies(500);
1777 state->closing_wait = 30 * HZ; 1774 state->closing_wait = 30 * HZ;
1778 spin_lock_init(&state->sicc_lock); 1775 spin_lock_init(&state->sicc_lock);
1779 } 1776 }
diff --git a/arch/ppc/8260_io/fcc_enet.c b/arch/ppc/8260_io/fcc_enet.c
index 2086c6ad1147..4edeede9ccfd 100644
--- a/arch/ppc/8260_io/fcc_enet.c
+++ b/arch/ppc/8260_io/fcc_enet.c
@@ -1309,8 +1309,7 @@ static void mii_dm9161_wait(uint mii_reg, struct net_device *dev)
1309 1309
1310 /* Davicom takes a bit to come up after a reset, 1310 /* Davicom takes a bit to come up after a reset,
1311 * so wait here for a bit */ 1311 * so wait here for a bit */
1312 set_current_state(TASK_UNINTERRUPTIBLE); 1312 schedule_timeout_uninterruptible(timeout);
1313 schedule_timeout(timeout);
1314} 1313}
1315 1314
1316static phy_info_t phy_info_dm9161 = { 1315static phy_info_t phy_info_dm9161 = {
diff --git a/arch/ppc/8xx_io/cs4218_tdm.c b/arch/ppc/8xx_io/cs4218_tdm.c
index 532caa388dc2..49eb2a7e65c0 100644
--- a/arch/ppc/8xx_io/cs4218_tdm.c
+++ b/arch/ppc/8xx_io/cs4218_tdm.c
@@ -1013,8 +1013,7 @@ static void CS_IrqCleanup(void)
1013 */ 1013 */
1014 cpm_free_handler(CPMVEC_SMC2); 1014 cpm_free_handler(CPMVEC_SMC2);
1015 1015
1016 if (beep_buf) 1016 kfree(beep_buf);
1017 kfree(beep_buf);
1018 kd_mksound = orig_mksound; 1017 kd_mksound = orig_mksound;
1019} 1018}
1020#endif /* MODULE */ 1019#endif /* MODULE */
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 114b90fdea24..8fa51b0a32d2 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -746,6 +746,16 @@ config MPC834x
746 bool 746 bool
747 default y if MPC834x_SYS 747 default y if MPC834x_SYS
748 748
749config CPM1
750 bool
751 depends on 8xx
752 default y
753 help
754 The CPM1 (Communications Processor Module) is a coprocessor on
755 embedded CPUs made by Motorola. Selecting this option means that
756 you wish to build a kernel for a machine with a CPM1 coprocessor
757 on it (8xx, 827x, 8560).
758
749config CPM2 759config CPM2
750 bool 760 bool
751 depends on 8260 || MPC8560 || MPC8555 761 depends on 8260 || MPC8560 || MPC8555
@@ -1247,6 +1257,14 @@ source "drivers/pci/Kconfig"
1247 1257
1248source "drivers/pcmcia/Kconfig" 1258source "drivers/pcmcia/Kconfig"
1249 1259
1260config RAPIDIO
1261 bool "RapidIO support" if MPC8540 || MPC8560
1262 help
1263 If you say Y here, the kernel will include drivers and
1264 infrastructure code to support RapidIO interconnect devices.
1265
1266source "drivers/rapidio/Kconfig"
1267
1250endmenu 1268endmenu
1251 1269
1252menu "Advanced setup" 1270menu "Advanced setup"
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
index b7bd8f61a4ad..82df88b01bbe 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -67,6 +67,12 @@ zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
67 entrypoint-$(CONFIG_BAMBOO) := 0x01000000 67 entrypoint-$(CONFIG_BAMBOO) := 0x01000000
68 extra.o-$(CONFIG_BAMBOO) := pibs.o 68 extra.o-$(CONFIG_BAMBOO) := pibs.o
69 69
70 zimage-$(CONFIG_BUBINGA) := zImage-TREE
71zimageinitrd-$(CONFIG_BUBINGA) := zImage.initrd-TREE
72 end-$(CONFIG_BUBINGA) := bubinga
73 entrypoint-$(CONFIG_BUBINGA) := 0x01000000
74 extra.o-$(CONFIG_BUBINGA) := openbios.o
75
70 zimage-$(CONFIG_EBONY) := zImage-TREE 76 zimage-$(CONFIG_EBONY) := zImage-TREE
71zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE 77zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
72 end-$(CONFIG_EBONY) := ebony 78 end-$(CONFIG_EBONY) := ebony
@@ -79,12 +85,30 @@ zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE
79 entrypoint-$(CONFIG_LUAN) := 0x01000000 85 entrypoint-$(CONFIG_LUAN) := 0x01000000
80 extra.o-$(CONFIG_LUAN) := pibs.o 86 extra.o-$(CONFIG_LUAN) := pibs.o
81 87
88 zimage-$(CONFIG_YUCCA) := zImage-TREE
89zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE
90 end-$(CONFIG_YUCCA) := yucca
91 entrypoint-$(CONFIG_YUCCA) := 0x01000000
92 extra.o-$(CONFIG_YUCCA) := pibs.o
93
82 zimage-$(CONFIG_OCOTEA) := zImage-TREE 94 zimage-$(CONFIG_OCOTEA) := zImage-TREE
83zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE 95zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE
84 end-$(CONFIG_OCOTEA) := ocotea 96 end-$(CONFIG_OCOTEA) := ocotea
85 entrypoint-$(CONFIG_OCOTEA) := 0x01000000 97 entrypoint-$(CONFIG_OCOTEA) := 0x01000000
86 extra.o-$(CONFIG_OCOTEA) := pibs.o 98 extra.o-$(CONFIG_OCOTEA) := pibs.o
87 99
100 zimage-$(CONFIG_SYCAMORE) := zImage-TREE
101zimageinitrd-$(CONFIG_SYCAMORE) := zImage.initrd-TREE
102 end-$(CONFIG_SYCAMORE) := sycamore
103 entrypoint-$(CONFIG_SYCAMORE) := 0x01000000
104 extra.o-$(CONFIG_SYCAMORE) := openbios.o
105
106 zimage-$(CONFIG_WALNUT) := zImage-TREE
107zimageinitrd-$(CONFIG_WALNUT) := zImage.initrd-TREE
108 end-$(CONFIG_WALNUT) := walnut
109 entrypoint-$(CONFIG_WALNUT) := 0x01000000
110 extra.o-$(CONFIG_WALNUT) := openbios.o
111
88 extra.o-$(CONFIG_EV64260) := misc-ev64260.o 112 extra.o-$(CONFIG_EV64260) := misc-ev64260.o
89 end-$(CONFIG_EV64260) := ev64260 113 end-$(CONFIG_EV64260) := ev64260
90 cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3) 114 cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3)
@@ -162,7 +186,8 @@ OBJCOPY_ARGS := -O elf32-powerpc
162 186
163# head.o and relocate.o must be at the start. 187# head.o and relocate.o must be at the start.
164boot-y := head.o relocate.o $(extra.o-y) $(misc-y) 188boot-y := head.o relocate.o $(extra.o-y) $(misc-y)
165boot-$(CONFIG_40x) += embed_config.o 189boot-$(CONFIG_REDWOOD_5) += embed_config.o
190boot-$(CONFIG_REDWOOD_6) += embed_config.o
166boot-$(CONFIG_8xx) += embed_config.o 191boot-$(CONFIG_8xx) += embed_config.o
167boot-$(CONFIG_8260) += embed_config.o 192boot-$(CONFIG_8260) += embed_config.o
168boot-$(CONFIG_BSEIP) += iic.o 193boot-$(CONFIG_BSEIP) += iic.o
diff --git a/arch/ppc/boot/simple/misc.c b/arch/ppc/boot/simple/misc.c
index e02de5b467a4..f415d6c62362 100644
--- a/arch/ppc/boot/simple/misc.c
+++ b/arch/ppc/boot/simple/misc.c
@@ -23,7 +23,7 @@
23#include <asm/page.h> 23#include <asm/page.h>
24#include <asm/mmu.h> 24#include <asm/mmu.h>
25#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
26#ifdef CONFIG_44x 26#ifdef CONFIG_4xx
27#include <asm/ibm4xx.h> 27#include <asm/ibm4xx.h>
28#endif 28#endif
29#include <asm/reg.h> 29#include <asm/reg.h>
@@ -88,6 +88,14 @@ get_mem_size(void)
88 return 0; 88 return 0;
89} 89}
90 90
91#if defined(CONFIG_40x)
92#define PPC4xx_EMAC0_MR0 EMAC0_BASE
93#endif
94
95#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0)
96#define PPC4xx_EMAC0_MR0 PPC44x_EMAC0_MR0
97#endif
98
91struct bi_record * 99struct bi_record *
92decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) 100decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
93{ 101{
@@ -103,13 +111,13 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
103 com_port = serial_init(0, NULL); 111 com_port = serial_init(0, NULL);
104#endif 112#endif
105 113
106#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0) 114#if defined(PPC4xx_EMAC0_MR0)
107 /* Reset MAL */ 115 /* Reset MAL */
108 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); 116 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
109 /* Wait for reset */ 117 /* Wait for reset */
110 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; 118 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {};
111 /* Reset EMAC */ 119 /* Reset EMAC */
112 *(volatile unsigned long *)PPC44x_EMAC0_MR0 = 0x20000000; 120 *(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000;
113 __asm__ __volatile__("eieio"); 121 __asm__ __volatile__("eieio");
114#endif 122#endif
115 123
@@ -164,7 +172,9 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
164 puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n"); 172 puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
165 } 173 }
166 174
175#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */
167 avail_ram = (char *)0x00400000; 176 avail_ram = (char *)0x00400000;
177#endif
168 end_avail = (char *)0x00800000; 178 end_avail = (char *)0x00800000;
169 puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" "); 179 puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
170 puthex((unsigned long)end_avail); puts("\n"); 180 puthex((unsigned long)end_avail); puts("\n");
diff --git a/arch/ppc/boot/simple/openbios.c b/arch/ppc/boot/simple/openbios.c
index c732b6d70cfb..81f11d8b30a7 100644
--- a/arch/ppc/boot/simple/openbios.c
+++ b/arch/ppc/boot/simple/openbios.c
@@ -1,19 +1,43 @@
1/* 1/*
2 * arch/ppc/boot/simple/openbios.c 2 * arch/ppc/boot/simple/openbios.c
3 * 3 *
4 * 2005 (c) SYSGO AG - g.jaeger@sysgo.com 4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * 2005 (c) SYSGO AG - g.jaeger@sysgo.com
9 *
5 * This file is licensed under the terms of the GNU General Public 10 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without 11 * License version 2. This program is licensed "as is" without
7 * any warranty of any kind, whether express or implied. 12 * any warranty of any kind, whether express or implied.
8 * 13 *
9 * Derived from arch/ppc/boot/simple/pibs.c (from MontaVista)
10 */ 14 */
11 15
12#include <linux/types.h> 16#include <linux/types.h>
13#include <linux/config.h> 17#include <linux/config.h>
14#include <linux/string.h> 18#include <linux/string.h>
15#include <asm/ppcboot.h> 19#include <asm/ppcboot.h>
16#include <platforms/4xx/ebony.h> 20#include <asm/ibm4xx.h>
21#include <asm/reg.h>
22#ifdef CONFIG_40x
23#include <asm/io.h>
24#endif
25
26#if defined(CONFIG_BUBINGA)
27#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */
28#else
29#define BOARD_INFO_VECTOR 0xFFFE0B50
30#endif
31
32#ifdef CONFIG_40x
33/* Supply a default Ethernet address for those eval boards that don't
34 * ship with one. This is an address from the MBX board I have, so
35 * it is unlikely you will find it on your network.
36 */
37static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };
38
39extern unsigned long timebase_period_ns;
40#endif /* CONFIG_40x */
17 41
18extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, 42extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
19 unsigned long cksum); 43 unsigned long cksum);
@@ -23,15 +47,85 @@ extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
23bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot"))); 47bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
24bd_t *hold_residual = &hold_resid_buf; 48bd_t *hold_residual = &hold_resid_buf;
25 49
50typedef struct openbios_board_info {
51 unsigned char bi_s_version[4]; /* Version of this structure */
52 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
53 unsigned int bi_memsize; /* DRAM installed, in bytes */
54#ifdef CONFIG_405EP
55 unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */
56#else /* CONFIG_405EP */
57 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
58#endif /* CONFIG_405EP */
59 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
60 unsigned int bi_intfreq; /* Processor speed, in Hz */
61 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
62 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
63#ifdef CONFIG_405EP
64 unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
65 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
66#endif /* CONFIG_405EP */
67} openbios_bd_t;
68
26void * 69void *
27load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, 70load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
28 void *ign1, void *ign2) 71 void *ign1, void *ign2)
29{ 72{
30 decompress_kernel(load_addr, num_words, cksum); 73#ifdef CONFIG_40x
74 openbios_bd_t *openbios_bd = NULL;
75 openbios_bd_t *(*get_board_info)(void) =
76 (openbios_bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR);
77
78 /*
79 * On 40x platforms we not only need the MAC-addresses, but also the
80 * clocks and memsize. Now try to get all values using the OpenBIOS
81 * "get_board_info()" callback.
82 */
83 if ((openbios_bd = get_board_info()) != NULL) {
84 /*
85 * Copy bd_info from OpenBIOS struct into U-Boot struct
86 * used by kernel
87 */
88 hold_residual->bi_memsize = openbios_bd->bi_memsize;
89 hold_residual->bi_intfreq = openbios_bd->bi_intfreq;
90 hold_residual->bi_busfreq = openbios_bd->bi_busfreq;
91 hold_residual->bi_pci_busfreq = openbios_bd->bi_pci_busfreq;
92 memcpy(hold_residual->bi_pci_enetaddr, openbios_bd->bi_pci_enetaddr, 6);
93#ifdef CONFIG_405EP
94 memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr[0], 6);
95 memcpy(hold_residual->bi_enet1addr, openbios_bd->bi_enetaddr[1], 6);
96 hold_residual->bi_opbfreq = openbios_bd->bi_opb_busfreq;
97 hold_residual->bi_procfreq = openbios_bd->bi_pllouta_freq;
98#else /* CONFIG_405EP */
99 memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr, 6);
100#endif /* CONFIG_405EP */
101 } else {
102 /* Hmmm...better try to stuff some defaults.
103 */
104 hold_residual->bi_memsize = 16 * 1024 * 1024;
105 hold_residual->bi_intfreq = 200000000;
106 hold_residual->bi_busfreq = 100000000;
107 hold_residual->bi_pci_busfreq = 66666666;
108
109 /*
110 * Only supply one mac-address in this fallback
111 */
112 memcpy(hold_residual->bi_enetaddr, (void *)def_enet_addr, 6);
113#ifdef CONFIG_405EP
114 hold_residual->bi_opbfreq = 50000000;
115 hold_residual->bi_procfreq = 200000000;
116#endif /* CONFIG_405EP */
117 }
31 118
119 timebase_period_ns = 1000000000 / hold_residual->bi_intfreq;
120#endif /* CONFIG_40x */
121
122#ifdef CONFIG_440GP
32 /* simply copy the MAC addresses */ 123 /* simply copy the MAC addresses */
33 memcpy(hold_residual->bi_enetaddr, (char *)EBONY_OPENBIOS_MAC_BASE, 6); 124 memcpy(hold_residual->bi_enetaddr, (char *)OPENBIOS_MAC_BASE, 6);
34 memcpy(hold_residual->bi_enet1addr, (char *)(EBONY_OPENBIOS_MAC_BASE+EBONY_OPENBIOS_MAC_OFFSET), 6); 125 memcpy(hold_residual->bi_enet1addr, (char *)(OPENBIOS_MAC_BASE+OPENBIOS_MAC_OFFSET), 6);
126#endif /* CONFIG_440GP */
127
128 decompress_kernel(load_addr, num_words, cksum);
35 129
36 return (void *)hold_residual; 130 return (void *)hold_residual;
37} 131}
diff --git a/arch/ppc/configs/ev64360_defconfig b/arch/ppc/configs/ev64360_defconfig
index de9bbb791db9..d471e578dcb5 100644
--- a/arch/ppc/configs/ev64360_defconfig
+++ b/arch/ppc/configs/ev64360_defconfig
@@ -1,17 +1,17 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.13-rc5 3# Linux kernel version: 2.6.14
4# Fri Aug 5 15:18:23 2005 4# Fri Oct 28 19:15:34 2005
5# 5#
6CONFIG_MMU=y 6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y 7CONFIG_GENERIC_HARDIRQS=y
8CONFIG_RWSEM_XCHGADD_ALGORITHM=y 8CONFIG_RWSEM_XCHGADD_ALGORITHM=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y 9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_HAVE_DEC_LOCK=y
11CONFIG_PPC=y 10CONFIG_PPC=y
12CONFIG_PPC32=y 11CONFIG_PPC32=y
13CONFIG_GENERIC_NVRAM=y 12CONFIG_GENERIC_NVRAM=y
14CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 13CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
15 15
16# 16#
17# Code maturity level options 17# Code maturity level options
@@ -26,6 +26,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
26# General setup 26# General setup
27# 27#
28CONFIG_LOCALVERSION="" 28CONFIG_LOCALVERSION=""
29CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SWAP=y 30CONFIG_SWAP=y
30CONFIG_SYSVIPC=y 31CONFIG_SYSVIPC=y
31CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
@@ -35,6 +36,7 @@ CONFIG_SYSCTL=y
35CONFIG_HOTPLUG=y 36CONFIG_HOTPLUG=y
36CONFIG_KOBJECT_UEVENT=y 37CONFIG_KOBJECT_UEVENT=y
37# CONFIG_IKCONFIG is not set 38# CONFIG_IKCONFIG is not set
39CONFIG_INITRAMFS_SOURCE=""
38# CONFIG_EMBEDDED is not set 40# CONFIG_EMBEDDED is not set
39CONFIG_KALLSYMS=y 41CONFIG_KALLSYMS=y
40# CONFIG_KALLSYMS_EXTRA_PASS is not set 42# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -74,7 +76,7 @@ CONFIG_TAU=y
74# CONFIG_TAU_AVERAGE is not set 76# CONFIG_TAU_AVERAGE is not set
75# CONFIG_KEXEC is not set 77# CONFIG_KEXEC is not set
76# CONFIG_CPU_FREQ is not set 78# CONFIG_CPU_FREQ is not set
77# CONFIG_PM is not set 79# CONFIG_WANT_EARLY_SERIAL is not set
78CONFIG_PPC_STD_MMU=y 80CONFIG_PPC_STD_MMU=y
79CONFIG_NOT_COHERENT_CACHE=y 81CONFIG_NOT_COHERENT_CACHE=y
80 82
@@ -86,22 +88,18 @@ CONFIG_NOT_COHERENT_CACHE=y
86# CONFIG_KATANA is not set 88# CONFIG_KATANA is not set
87# CONFIG_WILLOW is not set 89# CONFIG_WILLOW is not set
88# CONFIG_CPCI690 is not set 90# CONFIG_CPCI690 is not set
89# CONFIG_PCORE is not set
90# CONFIG_POWERPMC250 is not set 91# CONFIG_POWERPMC250 is not set
91# CONFIG_CHESTNUT is not set 92# CONFIG_CHESTNUT is not set
92# CONFIG_SPRUCE is not set 93# CONFIG_SPRUCE is not set
93# CONFIG_HDPU is not set 94# CONFIG_HDPU is not set
94# CONFIG_EV64260 is not set 95# CONFIG_EV64260 is not set
95# CONFIG_LOPEC is not set 96# CONFIG_LOPEC is not set
96# CONFIG_MCPN765 is not set
97# CONFIG_MVME5100 is not set 97# CONFIG_MVME5100 is not set
98# CONFIG_PPLUS is not set 98# CONFIG_PPLUS is not set
99# CONFIG_PRPMC750 is not set 99# CONFIG_PRPMC750 is not set
100# CONFIG_PRPMC800 is not set 100# CONFIG_PRPMC800 is not set
101# CONFIG_SANDPOINT is not set 101# CONFIG_SANDPOINT is not set
102# CONFIG_RADSTONE_PPC7D is not set 102# CONFIG_RADSTONE_PPC7D is not set
103# CONFIG_ADIR is not set
104# CONFIG_K2 is not set
105# CONFIG_PAL4 is not set 103# CONFIG_PAL4 is not set
106# CONFIG_GEMINI is not set 104# CONFIG_GEMINI is not set
107# CONFIG_EST8260 is not set 105# CONFIG_EST8260 is not set
@@ -138,10 +136,13 @@ CONFIG_FLATMEM_MANUAL=y
138# CONFIG_SPARSEMEM_MANUAL is not set 136# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_FLATMEM=y 137CONFIG_FLATMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y 138CONFIG_FLAT_NODE_MEM_MAP=y
139# CONFIG_SPARSEMEM_STATIC is not set
141CONFIG_BINFMT_ELF=y 140CONFIG_BINFMT_ELF=y
142CONFIG_BINFMT_MISC=y 141CONFIG_BINFMT_MISC=y
143CONFIG_CMDLINE_BOOL=y 142CONFIG_CMDLINE_BOOL=y
144CONFIG_CMDLINE="console=ttyMM0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2" 143CONFIG_CMDLINE="console=ttyMM0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"
144# CONFIG_PM is not set
145# CONFIG_SOFTWARE_SUSPEND is not set
145CONFIG_SECCOMP=y 146CONFIG_SECCOMP=y
146CONFIG_ISA_DMA_API=y 147CONFIG_ISA_DMA_API=y
147 148
@@ -152,7 +153,6 @@ CONFIG_GENERIC_ISA_DMA=y
152CONFIG_PCI=y 153CONFIG_PCI=y
153CONFIG_PCI_DOMAINS=y 154CONFIG_PCI_DOMAINS=y
154# CONFIG_PCI_LEGACY_PROC is not set 155# CONFIG_PCI_LEGACY_PROC is not set
155# CONFIG_PCI_NAMES is not set
156 156
157# 157#
158# PCCARD (PCMCIA/CardBus) support 158# PCCARD (PCMCIA/CardBus) support
@@ -206,14 +206,19 @@ CONFIG_SYN_COOKIES=y
206# CONFIG_INET_ESP is not set 206# CONFIG_INET_ESP is not set
207# CONFIG_INET_IPCOMP is not set 207# CONFIG_INET_IPCOMP is not set
208# CONFIG_INET_TUNNEL is not set 208# CONFIG_INET_TUNNEL is not set
209CONFIG_IP_TCPDIAG=y 209CONFIG_INET_DIAG=y
210# CONFIG_IP_TCPDIAG_IPV6 is not set 210CONFIG_INET_TCP_DIAG=y
211# CONFIG_TCP_CONG_ADVANCED is not set 211# CONFIG_TCP_CONG_ADVANCED is not set
212CONFIG_TCP_CONG_BIC=y 212CONFIG_TCP_CONG_BIC=y
213# CONFIG_IPV6 is not set 213# CONFIG_IPV6 is not set
214# CONFIG_NETFILTER is not set 214# CONFIG_NETFILTER is not set
215 215
216# 216#
217# DCCP Configuration (EXPERIMENTAL)
218#
219# CONFIG_IP_DCCP is not set
220
221#
217# SCTP Configuration (EXPERIMENTAL) 222# SCTP Configuration (EXPERIMENTAL)
218# 223#
219# CONFIG_IP_SCTP is not set 224# CONFIG_IP_SCTP is not set
@@ -239,6 +244,7 @@ CONFIG_TCP_CONG_BIC=y
239# CONFIG_HAMRADIO is not set 244# CONFIG_HAMRADIO is not set
240# CONFIG_IRDA is not set 245# CONFIG_IRDA is not set
241# CONFIG_BT is not set 246# CONFIG_BT is not set
247# CONFIG_IEEE80211 is not set
242 248
243# 249#
244# Device Drivers 250# Device Drivers
@@ -252,6 +258,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
252# CONFIG_FW_LOADER is not set 258# CONFIG_FW_LOADER is not set
253 259
254# 260#
261# Connector - unified userspace <-> kernelspace linker
262#
263# CONFIG_CONNECTOR is not set
264
265#
255# Memory Technology Devices (MTD) 266# Memory Technology Devices (MTD)
256# 267#
257CONFIG_MTD=y 268CONFIG_MTD=y
@@ -358,7 +369,6 @@ CONFIG_BLK_DEV_RAM=y
358CONFIG_BLK_DEV_RAM_COUNT=16 369CONFIG_BLK_DEV_RAM_COUNT=16
359CONFIG_BLK_DEV_RAM_SIZE=32768 370CONFIG_BLK_DEV_RAM_SIZE=32768
360CONFIG_BLK_DEV_INITRD=y 371CONFIG_BLK_DEV_INITRD=y
361CONFIG_INITRAMFS_SOURCE=""
362# CONFIG_LBD is not set 372# CONFIG_LBD is not set
363# CONFIG_CDROM_PKTCDVD is not set 373# CONFIG_CDROM_PKTCDVD is not set
364 374
@@ -379,6 +389,7 @@ CONFIG_IOSCHED_CFQ=y
379# 389#
380# SCSI device support 390# SCSI device support
381# 391#
392# CONFIG_RAID_ATTRS is not set
382# CONFIG_SCSI is not set 393# CONFIG_SCSI is not set
383 394
384# 395#
@@ -420,6 +431,10 @@ CONFIG_NETDEVICES=y
420# CONFIG_ARCNET is not set 431# CONFIG_ARCNET is not set
421 432
422# 433#
434# PHY device support
435#
436
437#
423# Ethernet (10 or 100Mbit) 438# Ethernet (10 or 100Mbit)
424# 439#
425# CONFIG_NET_ETHERNET is not set 440# CONFIG_NET_ETHERNET is not set
@@ -434,6 +449,7 @@ CONFIG_NETDEVICES=y
434# CONFIG_HAMACHI is not set 449# CONFIG_HAMACHI is not set
435# CONFIG_YELLOWFIN is not set 450# CONFIG_YELLOWFIN is not set
436# CONFIG_R8169 is not set 451# CONFIG_R8169 is not set
452# CONFIG_SIS190 is not set
437# CONFIG_SKGE is not set 453# CONFIG_SKGE is not set
438# CONFIG_SK98LIN is not set 454# CONFIG_SK98LIN is not set
439# CONFIG_TIGON3 is not set 455# CONFIG_TIGON3 is not set
@@ -446,6 +462,7 @@ CONFIG_MV643XX_ETH_0=y
446# 462#
447# Ethernet (10000 Mbit) 463# Ethernet (10000 Mbit)
448# 464#
465# CONFIG_CHELSIO_T1 is not set
449# CONFIG_IXGB is not set 466# CONFIG_IXGB is not set
450# CONFIG_S2IO is not set 467# CONFIG_S2IO is not set
451 468
@@ -547,7 +564,20 @@ CONFIG_LEGACY_PTY_COUNT=256
547# 564#
548# Watchdog Cards 565# Watchdog Cards
549# 566#
550# CONFIG_WATCHDOG is not set 567CONFIG_WATCHDOG=y
568# CONFIG_WATCHDOG_NOWAYOUT is not set
569
570#
571# Watchdog Device Drivers
572#
573# CONFIG_SOFT_WATCHDOG is not set
574CONFIG_MV64X60_WDT=y
575
576#
577# PCI-based Watchdog Cards
578#
579# CONFIG_PCIPCWATCHDOG is not set
580# CONFIG_WDTPCI is not set
551# CONFIG_NVRAM is not set 581# CONFIG_NVRAM is not set
552CONFIG_GEN_RTC=y 582CONFIG_GEN_RTC=y
553# CONFIG_GEN_RTC_X is not set 583# CONFIG_GEN_RTC_X is not set
@@ -571,7 +601,6 @@ CONFIG_GEN_RTC=y
571# I2C support 601# I2C support
572# 602#
573# CONFIG_I2C is not set 603# CONFIG_I2C is not set
574# CONFIG_I2C_SENSOR is not set
575 604
576# 605#
577# Dallas's 1-wire bus 606# Dallas's 1-wire bus
@@ -582,6 +611,7 @@ CONFIG_GEN_RTC=y
582# Hardware Monitoring support 611# Hardware Monitoring support
583# 612#
584CONFIG_HWMON=y 613CONFIG_HWMON=y
614# CONFIG_HWMON_VID is not set
585# CONFIG_HWMON_DEBUG_CHIP is not set 615# CONFIG_HWMON_DEBUG_CHIP is not set
586 616
587# 617#
@@ -589,6 +619,10 @@ CONFIG_HWMON=y
589# 619#
590 620
591# 621#
622# Multimedia Capabilities Port drivers
623#
624
625#
592# Multimedia devices 626# Multimedia devices
593# 627#
594# CONFIG_VIDEO_DEV is not set 628# CONFIG_VIDEO_DEV is not set
@@ -651,10 +685,6 @@ CONFIG_EXT2_FS=y
651# CONFIG_REISERFS_FS is not set 685# CONFIG_REISERFS_FS is not set
652# CONFIG_JFS_FS is not set 686# CONFIG_JFS_FS is not set
653# CONFIG_FS_POSIX_ACL is not set 687# CONFIG_FS_POSIX_ACL is not set
654
655#
656# XFS support
657#
658# CONFIG_XFS_FS is not set 688# CONFIG_XFS_FS is not set
659# CONFIG_MINIX_FS is not set 689# CONFIG_MINIX_FS is not set
660# CONFIG_ROMFS_FS is not set 690# CONFIG_ROMFS_FS is not set
@@ -663,6 +693,7 @@ CONFIG_INOTIFY=y
663CONFIG_DNOTIFY=y 693CONFIG_DNOTIFY=y
664# CONFIG_AUTOFS_FS is not set 694# CONFIG_AUTOFS_FS is not set
665# CONFIG_AUTOFS4_FS is not set 695# CONFIG_AUTOFS4_FS is not set
696# CONFIG_FUSE_FS is not set
666 697
667# 698#
668# CD-ROM/DVD Filesystems 699# CD-ROM/DVD Filesystems
@@ -683,11 +714,10 @@ CONFIG_DNOTIFY=y
683CONFIG_PROC_FS=y 714CONFIG_PROC_FS=y
684CONFIG_PROC_KCORE=y 715CONFIG_PROC_KCORE=y
685CONFIG_SYSFS=y 716CONFIG_SYSFS=y
686# CONFIG_DEVPTS_FS_XATTR is not set
687CONFIG_TMPFS=y 717CONFIG_TMPFS=y
688# CONFIG_TMPFS_XATTR is not set
689# CONFIG_HUGETLB_PAGE is not set 718# CONFIG_HUGETLB_PAGE is not set
690CONFIG_RAMFS=y 719CONFIG_RAMFS=y
720# CONFIG_RELAYFS_FS is not set
691 721
692# 722#
693# Miscellaneous filesystems 723# Miscellaneous filesystems
@@ -735,6 +765,7 @@ CONFIG_SUNRPC=y
735# CONFIG_NCP_FS is not set 765# CONFIG_NCP_FS is not set
736# CONFIG_CODA_FS is not set 766# CONFIG_CODA_FS is not set
737# CONFIG_AFS_FS is not set 767# CONFIG_AFS_FS is not set
768# CONFIG_9P_FS is not set
738 769
739# 770#
740# Partition Types 771# Partition Types
@@ -751,6 +782,7 @@ CONFIG_MSDOS_PARTITION=y
751# Library routines 782# Library routines
752# 783#
753# CONFIG_CRC_CCITT is not set 784# CONFIG_CRC_CCITT is not set
785# CONFIG_CRC16 is not set
754CONFIG_CRC32=y 786CONFIG_CRC32=y
755# CONFIG_LIBCRC32C is not set 787# CONFIG_LIBCRC32C is not set
756CONFIG_ZLIB_INFLATE=y 788CONFIG_ZLIB_INFLATE=y
@@ -767,6 +799,7 @@ CONFIG_ZLIB_DEFLATE=y
767# CONFIG_PRINTK_TIME is not set 799# CONFIG_PRINTK_TIME is not set
768# CONFIG_DEBUG_KERNEL is not set 800# CONFIG_DEBUG_KERNEL is not set
769CONFIG_LOG_BUF_SHIFT=14 801CONFIG_LOG_BUF_SHIFT=14
802# CONFIG_SERIAL_TEXT_DEBUG is not set
770 803
771# 804#
772# Security options 805# Security options
diff --git a/arch/ppc/configs/stx_gp3_defconfig b/arch/ppc/configs/stx_gp3_defconfig
index 66dae8367659..3fedc43e44ad 100644
--- a/arch/ppc/configs/stx_gp3_defconfig
+++ b/arch/ppc/configs/stx_gp3_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.12-rc4
4# Wed Jan 26 14:32:58 2005 4# Tue May 24 18:11:04 2005
5# 5#
6CONFIG_MMU=y 6CONFIG_MMU=y
7CONFIG_GENERIC_HARDIRQS=y 7CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y
11CONFIG_PPC=y 11CONFIG_PPC=y
12CONFIG_PPC32=y 12CONFIG_PPC32=y
13CONFIG_GENERIC_NVRAM=y 13CONFIG_GENERIC_NVRAM=y
14CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
14 15
15# 16#
16# Code maturity level options 17# Code maturity level options
@@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
18CONFIG_EXPERIMENTAL=y 19CONFIG_EXPERIMENTAL=y
19CONFIG_CLEAN_COMPILE=y 20CONFIG_CLEAN_COMPILE=y
20CONFIG_BROKEN_ON_SMP=y 21CONFIG_BROKEN_ON_SMP=y
22CONFIG_INIT_ENV_ARG_LIMIT=32
21 23
22# 24#
23# General setup 25# General setup
@@ -29,7 +31,6 @@ CONFIG_SYSVIPC=y
29# CONFIG_BSD_PROCESS_ACCT is not set 31# CONFIG_BSD_PROCESS_ACCT is not set
30CONFIG_SYSCTL=y 32CONFIG_SYSCTL=y
31# CONFIG_AUDIT is not set 33# CONFIG_AUDIT is not set
32CONFIG_LOG_BUF_SHIFT=14
33CONFIG_HOTPLUG=y 34CONFIG_HOTPLUG=y
34CONFIG_KOBJECT_UEVENT=y 35CONFIG_KOBJECT_UEVENT=y
35# CONFIG_IKCONFIG is not set 36# CONFIG_IKCONFIG is not set
@@ -37,6 +38,9 @@ CONFIG_EMBEDDED=y
37CONFIG_KALLSYMS=y 38CONFIG_KALLSYMS=y
38# CONFIG_KALLSYMS_ALL is not set 39# CONFIG_KALLSYMS_ALL is not set
39# CONFIG_KALLSYMS_EXTRA_PASS is not set 40# CONFIG_KALLSYMS_EXTRA_PASS is not set
41CONFIG_PRINTK=y
42CONFIG_BUG=y
43CONFIG_BASE_FULL=y
40CONFIG_FUTEX=y 44CONFIG_FUTEX=y
41CONFIG_EPOLL=y 45CONFIG_EPOLL=y
42# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -46,6 +50,7 @@ CONFIG_CC_ALIGN_LABELS=0
46CONFIG_CC_ALIGN_LOOPS=0 50CONFIG_CC_ALIGN_LOOPS=0
47CONFIG_CC_ALIGN_JUMPS=0 51CONFIG_CC_ALIGN_JUMPS=0
48# CONFIG_TINY_SHMEM is not set 52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
49 54
50# 55#
51# Loadable module support 56# Loadable module support
@@ -69,9 +74,11 @@ CONFIG_KMOD=y
69CONFIG_E500=y 74CONFIG_E500=y
70CONFIG_BOOKE=y 75CONFIG_BOOKE=y
71CONFIG_FSL_BOOKE=y 76CONFIG_FSL_BOOKE=y
77# CONFIG_PHYS_64BIT is not set
72# CONFIG_SPE is not set 78# CONFIG_SPE is not set
73CONFIG_MATH_EMULATION=y 79CONFIG_MATH_EMULATION=y
74# CONFIG_CPU_FREQ is not set 80# CONFIG_CPU_FREQ is not set
81# CONFIG_PM is not set
75CONFIG_85xx=y 82CONFIG_85xx=y
76CONFIG_PPC_INDIRECT_PCI_BE=y 83CONFIG_PPC_INDIRECT_PCI_BE=y
77 84
@@ -96,6 +103,7 @@ CONFIG_HIGHMEM=y
96CONFIG_BINFMT_ELF=y 103CONFIG_BINFMT_ELF=y
97CONFIG_BINFMT_MISC=m 104CONFIG_BINFMT_MISC=m
98# CONFIG_CMDLINE_BOOL is not set 105# CONFIG_CMDLINE_BOOL is not set
106CONFIG_ISA_DMA_API=y
99 107
100# 108#
101# Bus options 109# Bus options
@@ -104,15 +112,15 @@ CONFIG_PCI=y
104CONFIG_PCI_DOMAINS=y 112CONFIG_PCI_DOMAINS=y
105# CONFIG_PCI_LEGACY_PROC is not set 113# CONFIG_PCI_LEGACY_PROC is not set
106# CONFIG_PCI_NAMES is not set 114# CONFIG_PCI_NAMES is not set
115# CONFIG_PCI_DEBUG is not set
107 116
108# 117#
109# PCCARD (PCMCIA/CardBus) support 118# PCCARD (PCMCIA/CardBus) support
110# 119#
111# CONFIG_PCCARD is not set 120# CONFIG_PCCARD is not set
112 121CONFIG_RAPIDIO=y
113# 122CONFIG_RAPIDIO_8_BIT_TRANSPORT=y
114# PC-card bridges 123CONFIG_RAPIDIO_DISC_TIMEOUT=30
115#
116 124
117# 125#
118# Advanced setup 126# Advanced setup
@@ -152,7 +160,7 @@ CONFIG_PARPORT=m
152CONFIG_PARPORT_PC=m 160CONFIG_PARPORT_PC=m
153# CONFIG_PARPORT_PC_FIFO is not set 161# CONFIG_PARPORT_PC_FIFO is not set
154# CONFIG_PARPORT_PC_SUPERIO is not set 162# CONFIG_PARPORT_PC_SUPERIO is not set
155# CONFIG_PARPORT_OTHER is not set 163# CONFIG_PARPORT_GSC is not set
156# CONFIG_PARPORT_1284 is not set 164# CONFIG_PARPORT_1284 is not set
157 165
158# 166#
@@ -264,7 +272,6 @@ CONFIG_SCSI_CONSTANTS=y
264# CONFIG_SCSI_BUSLOGIC is not set 272# CONFIG_SCSI_BUSLOGIC is not set
265# CONFIG_SCSI_DMX3191D is not set 273# CONFIG_SCSI_DMX3191D is not set
266# CONFIG_SCSI_EATA is not set 274# CONFIG_SCSI_EATA is not set
267# CONFIG_SCSI_EATA_PIO is not set
268# CONFIG_SCSI_FUTURE_DOMAIN is not set 275# CONFIG_SCSI_FUTURE_DOMAIN is not set
269# CONFIG_SCSI_GDTH is not set 276# CONFIG_SCSI_GDTH is not set
270# CONFIG_SCSI_IPS is not set 277# CONFIG_SCSI_IPS is not set
@@ -274,7 +281,6 @@ CONFIG_SCSI_CONSTANTS=y
274# CONFIG_SCSI_IMM is not set 281# CONFIG_SCSI_IMM is not set
275# CONFIG_SCSI_SYM53C8XX_2 is not set 282# CONFIG_SCSI_SYM53C8XX_2 is not set
276# CONFIG_SCSI_IPR is not set 283# CONFIG_SCSI_IPR is not set
277# CONFIG_SCSI_QLOGIC_ISP is not set
278# CONFIG_SCSI_QLOGIC_FC is not set 284# CONFIG_SCSI_QLOGIC_FC is not set
279# CONFIG_SCSI_QLOGIC_1280 is not set 285# CONFIG_SCSI_QLOGIC_1280 is not set
280CONFIG_SCSI_QLA2XXX=m 286CONFIG_SCSI_QLA2XXX=m
@@ -283,6 +289,7 @@ CONFIG_SCSI_QLA2XXX=m
283# CONFIG_SCSI_QLA2300 is not set 289# CONFIG_SCSI_QLA2300 is not set
284# CONFIG_SCSI_QLA2322 is not set 290# CONFIG_SCSI_QLA2322 is not set
285# CONFIG_SCSI_QLA6312 is not set 291# CONFIG_SCSI_QLA6312 is not set
292# CONFIG_SCSI_LPFC is not set
286# CONFIG_SCSI_DC395x is not set 293# CONFIG_SCSI_DC395x is not set
287# CONFIG_SCSI_DC390T is not set 294# CONFIG_SCSI_DC390T is not set
288# CONFIG_SCSI_NSP32 is not set 295# CONFIG_SCSI_NSP32 is not set
@@ -322,7 +329,6 @@ CONFIG_NET=y
322# 329#
323CONFIG_PACKET=y 330CONFIG_PACKET=y
324# CONFIG_PACKET_MMAP is not set 331# CONFIG_PACKET_MMAP is not set
325# CONFIG_NETLINK_DEV is not set
326CONFIG_UNIX=y 332CONFIG_UNIX=y
327# CONFIG_NET_KEY is not set 333# CONFIG_NET_KEY is not set
328CONFIG_INET=y 334CONFIG_INET=y
@@ -431,7 +437,7 @@ CONFIG_IP_NF_NAT_FTP=m
431# 437#
432# Network testing 438# Network testing
433# 439#
434# CONFIG_NET_PKTGEN is not set 440CONFIG_NET_PKTGEN=y
435# CONFIG_NETPOLL is not set 441# CONFIG_NETPOLL is not set
436# CONFIG_NET_POLL_CONTROLLER is not set 442# CONFIG_NET_POLL_CONTROLLER is not set
437# CONFIG_HAMRADIO is not set 443# CONFIG_HAMRADIO is not set
@@ -499,6 +505,7 @@ CONFIG_GFAR_NAPI=y
499# Wan interfaces 505# Wan interfaces
500# 506#
501# CONFIG_WAN is not set 507# CONFIG_WAN is not set
508CONFIG_RIONET=y
502# CONFIG_FDDI is not set 509# CONFIG_FDDI is not set
503# CONFIG_HIPPI is not set 510# CONFIG_HIPPI is not set
504# CONFIG_PLIP is not set 511# CONFIG_PLIP is not set
@@ -536,20 +543,6 @@ CONFIG_INPUT_EVDEV=m
536# CONFIG_INPUT_EVBUG is not set 543# CONFIG_INPUT_EVBUG is not set
537 544
538# 545#
539# Input I/O drivers
540#
541# CONFIG_GAMEPORT is not set
542CONFIG_SOUND_GAMEPORT=y
543CONFIG_SERIO=y
544CONFIG_SERIO_I8042=y
545CONFIG_SERIO_SERPORT=y
546# CONFIG_SERIO_CT82C710 is not set
547# CONFIG_SERIO_PARKBD is not set
548# CONFIG_SERIO_PCIPS2 is not set
549CONFIG_SERIO_LIBPS2=y
550# CONFIG_SERIO_RAW is not set
551
552#
553# Input Device Drivers 546# Input Device Drivers
554# 547#
555CONFIG_INPUT_KEYBOARD=y 548CONFIG_INPUT_KEYBOARD=y
@@ -567,6 +560,19 @@ CONFIG_MOUSE_PS2=y
567# CONFIG_INPUT_MISC is not set 560# CONFIG_INPUT_MISC is not set
568 561
569# 562#
563# Hardware I/O ports
564#
565CONFIG_SERIO=y
566CONFIG_SERIO_I8042=y
567CONFIG_SERIO_SERPORT=y
568# CONFIG_SERIO_PARKBD is not set
569# CONFIG_SERIO_PCIPS2 is not set
570CONFIG_SERIO_LIBPS2=y
571# CONFIG_SERIO_RAW is not set
572# CONFIG_GAMEPORT is not set
573CONFIG_SOUND_GAMEPORT=y
574
575#
570# Character devices 576# Character devices
571# 577#
572# CONFIG_VT is not set 578# CONFIG_VT is not set
@@ -590,6 +596,7 @@ CONFIG_SERIAL_CPM_SCC2=y
590# CONFIG_SERIAL_CPM_SCC4 is not set 596# CONFIG_SERIAL_CPM_SCC4 is not set
591# CONFIG_SERIAL_CPM_SMC1 is not set 597# CONFIG_SERIAL_CPM_SMC1 is not set
592# CONFIG_SERIAL_CPM_SMC2 is not set 598# CONFIG_SERIAL_CPM_SMC2 is not set
599# CONFIG_SERIAL_JSM is not set
593CONFIG_UNIX98_PTYS=y 600CONFIG_UNIX98_PTYS=y
594CONFIG_LEGACY_PTYS=y 601CONFIG_LEGACY_PTYS=y
595CONFIG_LEGACY_PTY_COUNT=256 602CONFIG_LEGACY_PTY_COUNT=256
@@ -626,6 +633,11 @@ CONFIG_DRM=m
626# CONFIG_RAW_DRIVER is not set 633# CONFIG_RAW_DRIVER is not set
627 634
628# 635#
636# TPM devices
637#
638# CONFIG_TCG_TPM is not set
639
640#
629# I2C support 641# I2C support
630# 642#
631CONFIG_I2C=m 643CONFIG_I2C=m
@@ -648,12 +660,12 @@ CONFIG_I2C_ALGOBIT=m
648# CONFIG_I2C_AMD8111 is not set 660# CONFIG_I2C_AMD8111 is not set
649# CONFIG_I2C_I801 is not set 661# CONFIG_I2C_I801 is not set
650# CONFIG_I2C_I810 is not set 662# CONFIG_I2C_I810 is not set
663# CONFIG_I2C_PIIX4 is not set
651# CONFIG_I2C_ISA is not set 664# CONFIG_I2C_ISA is not set
652# CONFIG_I2C_MPC is not set 665# CONFIG_I2C_MPC is not set
653# CONFIG_I2C_NFORCE2 is not set 666# CONFIG_I2C_NFORCE2 is not set
654# CONFIG_I2C_PARPORT is not set 667# CONFIG_I2C_PARPORT is not set
655# CONFIG_I2C_PARPORT_LIGHT is not set 668# CONFIG_I2C_PARPORT_LIGHT is not set
656# CONFIG_I2C_PIIX4 is not set
657# CONFIG_I2C_PROSAVAGE is not set 669# CONFIG_I2C_PROSAVAGE is not set
658# CONFIG_I2C_SAVAGE4 is not set 670# CONFIG_I2C_SAVAGE4 is not set
659# CONFIG_SCx200_ACB is not set 671# CONFIG_SCx200_ACB is not set
@@ -677,7 +689,9 @@ CONFIG_I2C_ALGOBIT=m
677# CONFIG_SENSORS_ASB100 is not set 689# CONFIG_SENSORS_ASB100 is not set
678# CONFIG_SENSORS_DS1621 is not set 690# CONFIG_SENSORS_DS1621 is not set
679# CONFIG_SENSORS_FSCHER is not set 691# CONFIG_SENSORS_FSCHER is not set
692# CONFIG_SENSORS_FSCPOS is not set
680# CONFIG_SENSORS_GL518SM is not set 693# CONFIG_SENSORS_GL518SM is not set
694# CONFIG_SENSORS_GL520SM is not set
681# CONFIG_SENSORS_IT87 is not set 695# CONFIG_SENSORS_IT87 is not set
682# CONFIG_SENSORS_LM63 is not set 696# CONFIG_SENSORS_LM63 is not set
683# CONFIG_SENSORS_LM75 is not set 697# CONFIG_SENSORS_LM75 is not set
@@ -688,9 +702,11 @@ CONFIG_I2C_ALGOBIT=m
688# CONFIG_SENSORS_LM85 is not set 702# CONFIG_SENSORS_LM85 is not set
689# CONFIG_SENSORS_LM87 is not set 703# CONFIG_SENSORS_LM87 is not set
690# CONFIG_SENSORS_LM90 is not set 704# CONFIG_SENSORS_LM90 is not set
705# CONFIG_SENSORS_LM92 is not set
691# CONFIG_SENSORS_MAX1619 is not set 706# CONFIG_SENSORS_MAX1619 is not set
692# CONFIG_SENSORS_PC87360 is not set 707# CONFIG_SENSORS_PC87360 is not set
693# CONFIG_SENSORS_SMSC47B397 is not set 708# CONFIG_SENSORS_SMSC47B397 is not set
709# CONFIG_SENSORS_SIS5595 is not set
694# CONFIG_SENSORS_SMSC47M1 is not set 710# CONFIG_SENSORS_SMSC47M1 is not set
695# CONFIG_SENSORS_VIA686A is not set 711# CONFIG_SENSORS_VIA686A is not set
696# CONFIG_SENSORS_W83781D is not set 712# CONFIG_SENSORS_W83781D is not set
@@ -700,10 +716,12 @@ CONFIG_I2C_ALGOBIT=m
700# 716#
701# Other I2C Chip support 717# Other I2C Chip support
702# 718#
719# CONFIG_SENSORS_DS1337 is not set
703# CONFIG_SENSORS_EEPROM is not set 720# CONFIG_SENSORS_EEPROM is not set
704# CONFIG_SENSORS_PCF8574 is not set 721# CONFIG_SENSORS_PCF8574 is not set
705# CONFIG_SENSORS_PCF8591 is not set 722# CONFIG_SENSORS_PCF8591 is not set
706# CONFIG_SENSORS_RTC8564 is not set 723# CONFIG_SENSORS_RTC8564 is not set
724# CONFIG_SENSORS_M41T00 is not set
707# CONFIG_I2C_DEBUG_CORE is not set 725# CONFIG_I2C_DEBUG_CORE is not set
708# CONFIG_I2C_DEBUG_ALGO is not set 726# CONFIG_I2C_DEBUG_ALGO is not set
709# CONFIG_I2C_DEBUG_BUS is not set 727# CONFIG_I2C_DEBUG_BUS is not set
@@ -732,7 +750,6 @@ CONFIG_I2C_ALGOBIT=m
732# Graphics support 750# Graphics support
733# 751#
734# CONFIG_FB is not set 752# CONFIG_FB is not set
735# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
736 753
737# 754#
738# Sound 755# Sound
@@ -752,13 +769,9 @@ CONFIG_SOUND=m
752# 769#
753# USB support 770# USB support
754# 771#
755# CONFIG_USB is not set
756CONFIG_USB_ARCH_HAS_HCD=y 772CONFIG_USB_ARCH_HAS_HCD=y
757CONFIG_USB_ARCH_HAS_OHCI=y 773CONFIG_USB_ARCH_HAS_OHCI=y
758 774# CONFIG_USB is not set
759#
760# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
761#
762 775
763# 776#
764# USB Gadget Support 777# USB Gadget Support
@@ -789,6 +802,10 @@ CONFIG_JBD_DEBUG=y
789CONFIG_FS_MBCACHE=y 802CONFIG_FS_MBCACHE=y
790# CONFIG_REISERFS_FS is not set 803# CONFIG_REISERFS_FS is not set
791# CONFIG_JFS_FS is not set 804# CONFIG_JFS_FS is not set
805
806#
807# XFS support
808#
792# CONFIG_XFS_FS is not set 809# CONFIG_XFS_FS is not set
793# CONFIG_MINIX_FS is not set 810# CONFIG_MINIX_FS is not set
794# CONFIG_ROMFS_FS is not set 811# CONFIG_ROMFS_FS is not set
@@ -859,7 +876,6 @@ CONFIG_NFS_V3=y
859CONFIG_ROOT_NFS=y 876CONFIG_ROOT_NFS=y
860CONFIG_LOCKD=y 877CONFIG_LOCKD=y
861CONFIG_LOCKD_V4=y 878CONFIG_LOCKD_V4=y
862# CONFIG_EXPORTFS is not set
863CONFIG_SUNRPC=y 879CONFIG_SUNRPC=y
864# CONFIG_RPCSEC_GSS_KRB5 is not set 880# CONFIG_RPCSEC_GSS_KRB5 is not set
865# CONFIG_RPCSEC_GSS_SPKM3 is not set 881# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -942,8 +958,10 @@ CONFIG_ZLIB_INFLATE=m
942# 958#
943# Kernel hacking 959# Kernel hacking
944# 960#
961# CONFIG_PRINTK_TIME is not set
945CONFIG_DEBUG_KERNEL=y 962CONFIG_DEBUG_KERNEL=y
946# CONFIG_MAGIC_SYSRQ is not set 963# CONFIG_MAGIC_SYSRQ is not set
964CONFIG_LOG_BUF_SHIFT=14
947# CONFIG_SCHEDSTATS is not set 965# CONFIG_SCHEDSTATS is not set
948# CONFIG_DEBUG_SLAB is not set 966# CONFIG_DEBUG_SLAB is not set
949# CONFIG_DEBUG_SPINLOCK is not set 967# CONFIG_DEBUG_SPINLOCK is not set
diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile
index c610ca933a25..76a55a438f23 100644
--- a/arch/ppc/kernel/Makefile
+++ b/arch/ppc/kernel/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_POWER4) += cpu_setup_power4.o
22obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o 22obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o
23obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o 23obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o
24obj-$(CONFIG_PCI) += pci.o 24obj-$(CONFIG_PCI) += pci.o
25obj-$(CONFIG_RAPIDIO) += rio.o
25obj-$(CONFIG_KGDB) += ppc-stub.o 26obj-$(CONFIG_KGDB) += ppc-stub.o
26obj-$(CONFIG_SMP) += smp.o smp-tbsync.o 27obj-$(CONFIG_SMP) += smp.o smp-tbsync.o
27obj-$(CONFIG_TAU) += temp.o 28obj-$(CONFIG_TAU) += temp.o
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 8b49679fad54..677c571aa276 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */
190 190
191 /* xlat fields */ 191 /* xlat fields */
192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ 192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193#ifndef CONFIG_440EP 193#ifdef UART0_PHYS_ERPN
194 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ 194 ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */
195#endif 195#endif
196 196
197 /* attrib fields */ 197 /* attrib fields */
diff --git a/arch/ppc/kernel/rio.c b/arch/ppc/kernel/rio.c
new file mode 100644
index 000000000000..29487fedfc76
--- /dev/null
+++ b/arch/ppc/kernel/rio.c
@@ -0,0 +1,52 @@
1/*
2 * RapidIO PPC32 support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/rio.h>
16
17#include <asm/rio.h>
18
19/**
20 * platform_rio_init - Do platform specific RIO init
21 *
22 * Any platform specific initialization of RapdIO
23 * hardware is done here as well as registration
24 * of any active master ports in the system.
25 */
26void __attribute__ ((weak))
27 platform_rio_init(void)
28{
29 printk(KERN_WARNING "RIO: No platform_rio_init() present\n");
30}
31
32/**
33 * ppc_rio_init - Do PPC32 RIO init
34 *
35 * Calls platform-specific RIO init code and then calls
36 * rio_init_mports() to initialize any master ports that
37 * have been registered with the RIO subsystem.
38 */
39static int __init ppc_rio_init(void)
40{
41 printk(KERN_INFO "RIO: RapidIO init\n");
42
43 /* Platform specific initialization */
44 platform_rio_init();
45
46 /* Enumerate all registered ports */
47 rio_init_mports();
48
49 return 0;
50}
51
52subsys_initcall(ppc_rio_init);
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 76f4476cab44..d8837911bbc6 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -82,6 +82,12 @@ config LUAN
82 help 82 help
83 This option enables support for the IBM PPC440SP evaluation board. 83 This option enables support for the IBM PPC440SP evaluation board.
84 84
85config YUCCA
86 bool "Yucca"
87 select WANT_EARLY_SERIAL
88 help
89 This option enables support for the AMCC PPC440SPe evaluation board.
90
85config OCOTEA 91config OCOTEA
86 bool "Ocotea" 92 bool "Ocotea"
87 select WANT_EARLY_SERIAL 93 select WANT_EARLY_SERIAL
@@ -124,9 +130,14 @@ config 440SP
124 depends on LUAN 130 depends on LUAN
125 default y 131 default y
126 132
133config 440SPE
134 bool
135 depends on YUCCA
136 default y
137
127config 440 138config 440
128 bool 139 bool
129 depends on 440GP || 440SP || 440EP 140 depends on 440GP || 440SP || 440SPE || 440EP
130 default y 141 default y
131 142
132config 440A 143config 440A
@@ -158,7 +169,7 @@ config BOOKE
158 169
159config IBM_OCP 170config IBM_OCP
160 bool 171 bool
161 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 172 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
162 default y 173 default y
163 174
164config XILINX_OCP 175config XILINX_OCP
@@ -168,7 +179,7 @@ config XILINX_OCP
168 179
169config IBM_EMAC4 180config IBM_EMAC4
170 bool 181 bool
171 depends on 440GX || 440SP 182 depends on 440GX || 440SP || 440SPE
172 default y 183 default y
173 184
174config BIOS_FIXUP 185config BIOS_FIXUP
@@ -214,7 +225,7 @@ config EMBEDDEDBOOT
214 225
215config IBM_OPENBIOS 226config IBM_OPENBIOS
216 bool 227 bool
217 depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 228 depends on ASH || REDWOOD_5 || REDWOOD_6
218 default y 229 default y
219 230
220config PPC4xx_DMA 231config PPC4xx_DMA
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 1dd6d7fd6a9a..c9bb61170954 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o 7obj-$(CONFIG_EP405) += ep405.o
8obj-$(CONFIG_BUBINGA) += bubinga.o 8obj-$(CONFIG_BUBINGA) += bubinga.o
9obj-$(CONFIG_LUAN) += luan.o 9obj-$(CONFIG_LUAN) += luan.o
10obj-$(CONFIG_YUCCA) += yucca.o
10obj-$(CONFIG_OCOTEA) += ocotea.o 11obj-$(CONFIG_OCOTEA) += ocotea.o
11obj-$(CONFIG_REDWOOD_5) += redwood5.o 12obj-$(CONFIG_REDWOOD_5) += redwood5.o
12obj-$(CONFIG_REDWOOD_6) += redwood6.o 13obj-$(CONFIG_REDWOOD_6) += redwood6.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_440EP) += ibm440ep.o
22obj-$(CONFIG_440GP) += ibm440gp.o 23obj-$(CONFIG_440GP) += ibm440gp.o
23obj-$(CONFIG_440GX) += ibm440gx.o 24obj-$(CONFIG_440GX) += ibm440gx.o
24obj-$(CONFIG_440SP) += ibm440sp.o 25obj-$(CONFIG_440SP) += ibm440sp.o
26obj-$(CONFIG_440SPE) += ppc440spe.o
25obj-$(CONFIG_405EP) += ibm405ep.o 27obj-$(CONFIG_405EP) += ibm405ep.o
26obj-$(CONFIG_405GPR) += ibm405gpr.o 28obj-$(CONFIG_405GPR) += ibm405gpr.o
27obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o 29obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
index 3678abf86313..8110f55668c5 100644
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ b/arch/ppc/platforms/4xx/bubinga.c
@@ -89,7 +89,7 @@ bubinga_early_serial_map(void)
89 * by 16. 89 * by 16.
90 */ 90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); 91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_pllouta_freq / uart_div; 92 uart_clock = __res.bi_procfreq / uart_div;
93 93
94 /* Setup serial port access */ 94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port)); 95 memset(&port, 0, sizeof(port));
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
index b1df856f8e22..b5380cfaf5c0 100644
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ b/arch/ppc/platforms/4xx/bubinga.h
@@ -1,52 +1,34 @@
1/* 1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga). 2 * arch/ppc/platforms/4xx/bubinga.h
3 * 3 *
4 * Author: SAW (IBM), derived from walnut.h. 4 * Bubinga board definitions
5 * Maintained by MontaVista Software <source@mvista.com> 5 *
6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * Based on original work by
10 * SAW (IBM)
11 * 2003 (c) MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
6 * 17 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */ 18 */
12 19
13#ifdef __KERNEL__ 20#ifdef __KERNEL__
14#ifndef __BUBINGA_H__ 21#ifndef __BUBINGA_H__
15#define __BUBINGA_H__ 22#define __BUBINGA_H__
16 23
17/* 405EP */ 24#include <linux/config.h>
18#include <platforms/4xx/ibm405ep.h> 25#include <platforms/4xx/ibm405ep.h>
19 26#include <asm/ppcboot.h>
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
33 unsigned int bi_intfreq; /* Processor speed, in Hz */
34 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
35 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
36 unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
37 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44 27
45/* Memory map for the Bubinga board. 28/* Memory map for the Bubinga board.
46 * Generic 4xx plus RTC. 29 * Generic 4xx plus RTC.
47 */ 30 */
48 31
49extern void *bubinga_rtc_base;
50#define BUBINGA_RTC_PADDR ((uint)0xf0000000) 32#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
51#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR 33#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
52#define BUBINGA_RTC_SIZE ((uint)8*1024) 34#define BUBINGA_RTC_SIZE ((uint)8*1024)
@@ -58,12 +40,18 @@ extern void *bubinga_rtc_base;
58 * for typical configurations at various CPU speeds. 40 * for typical configurations at various CPU speeds.
59 * The base baud is calculated as (FWDA / EXT UART DIV / 16) 41 * The base baud is calculated as (FWDA / EXT UART DIV / 16)
60 */ 42 */
61#define BASE_BAUD 0 43#define BASE_BAUD 0
62 44
63#define BUBINGA_FPGA_BASE 0xF0300000 45/* Flash */
46#define PPC40x_FPGA_BASE 0xF0300000
47#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
48#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
49#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
50#define PPC40x_FLASH_LOW 0xFFF00000
51#define PPC40x_FLASH_HIGH 0xFFF80000
52#define PPC40x_FLASH_SIZE 0x80000
64 53
65#define PPC4xx_MACHINE_NAME "IBM Bubinga" 54#define PPC4xx_MACHINE_NAME "IBM Bubinga"
66 55
67#endif /* !__ASSEMBLY__ */
68#endif /* __BUBINGA_H__ */ 56#endif /* __BUBINGA_H__ */
69#endif /* __KERNEL__ */ 57#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index d08faa46a0ae..b91ad4272dfe 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -24,8 +24,8 @@
24#define PPC44x_EMAC0_MR0 0xE0000800 24#define PPC44x_EMAC0_MR0 0xE0000800
25 25
26/* Where to find the MAC info */ 26/* Where to find the MAC info */
27#define EBONY_OPENBIOS_MAC_BASE 0xfffffe0c 27#define OPENBIOS_MAC_BASE 0xfffffe0c
28#define EBONY_OPENBIOS_MAC_OFFSET 0x0c 28#define OPENBIOS_MAC_OFFSET 0x0c
29 29
30/* Default clock rates for Rev. B and Rev. C silicon */ 30/* Default clock rates for Rev. B and Rev. C silicon */
31#define EBONY_440GP_RB_SYSCLK 33000000 31#define EBONY_440GP_RB_SYSCLK 33000000
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
new file mode 100644
index 000000000000..6139a0b3393e
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.c
@@ -0,0 +1,148 @@
1/*
2 * arch/ppc/platforms/4xx/ppc440spe.c
3 *
4 * PPC440SPe I/O descriptions
5 *
6 * Roland Dreier <rolandd@cisco.com>
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2002-2005 MontaVista Software Inc.
11 *
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 * Copyright (c) 2003, 2004 Zultys Technologies
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21#include <linux/init.h>
22#include <linux/module.h>
23#include <platforms/4xx/ppc440spe.h>
24#include <asm/ocp.h>
25#include <asm/ppc4xx_pic.h>
26
27static struct ocp_func_emac_data ppc440spe_emac0_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = -1, /* No ZMII */
31 .zmii_mux = -1, /* No ZMII */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 0, /* MAL rx channel number */
34 .mal_tx_chan = 0, /* MAL tx channel number */
35 .wol_irq = 61, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39OCP_SYSFS_EMAC_DATA()
40
41static struct ocp_func_mal_data ppc440spe_mal0_def = {
42 .num_tx_chans = 1, /* Number of TX channels */
43 .num_rx_chans = 1, /* Number of RX channels */
44 .txeob_irq = 38, /* TX End Of Buffer IRQ */
45 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
46 .txde_irq = 34, /* TX Descriptor Error IRQ */
47 .rxde_irq = 35, /* RX Descriptor Error IRQ */
48 .serr_irq = 33, /* MAL System Error IRQ */
49 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
50};
51OCP_SYSFS_MAL_DATA()
52
53static struct ocp_func_iic_data ppc440spe_iic0_def = {
54 .fast_mode = 0, /* Use standad mode (100Khz) */
55};
56
57static struct ocp_func_iic_data ppc440spe_iic1_def = {
58 .fast_mode = 0, /* Use standad mode (100Khz) */
59};
60OCP_SYSFS_IIC_DATA()
61
62struct ocp_def core_ocp[] = {
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_16550,
65 .index = 0,
66 .paddr = PPC440SPE_UART0_ADDR,
67 .irq = UART0_INT,
68 .pm = IBM_CPM_UART0,
69 },
70 { .vendor = OCP_VENDOR_IBM,
71 .function = OCP_FUNC_16550,
72 .index = 1,
73 .paddr = PPC440SPE_UART1_ADDR,
74 .irq = UART1_INT,
75 .pm = IBM_CPM_UART1,
76 },
77 { .vendor = OCP_VENDOR_IBM,
78 .function = OCP_FUNC_16550,
79 .index = 2,
80 .paddr = PPC440SPE_UART2_ADDR,
81 .irq = UART2_INT,
82 .pm = IBM_CPM_UART2,
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_IIC,
86 .index = 0,
87 .paddr = 0x00000004f0000400ULL,
88 .irq = 2,
89 .pm = IBM_CPM_IIC0,
90 .additions = &ppc440spe_iic0_def,
91 .show = &ocp_show_iic_data
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .index = 1,
96 .paddr = 0x00000004f0000500ULL,
97 .irq = 3,
98 .pm = IBM_CPM_IIC1,
99 .additions = &ppc440spe_iic1_def,
100 .show = &ocp_show_iic_data
101 },
102 { .vendor = OCP_VENDOR_IBM,
103 .function = OCP_FUNC_GPIO,
104 .index = 0,
105 .paddr = 0x00000004f0000700ULL,
106 .irq = OCP_IRQ_NA,
107 .pm = IBM_CPM_GPIO0,
108 },
109 { .vendor = OCP_VENDOR_IBM,
110 .function = OCP_FUNC_MAL,
111 .paddr = OCP_PADDR_NA,
112 .irq = OCP_IRQ_NA,
113 .pm = OCP_CPM_NA,
114 .additions = &ppc440spe_mal0_def,
115 .show = &ocp_show_mal_data,
116 },
117 { .vendor = OCP_VENDOR_IBM,
118 .function = OCP_FUNC_EMAC,
119 .index = 0,
120 .paddr = 0x00000004f0000800ULL,
121 .irq = 60,
122 .pm = OCP_CPM_NA,
123 .additions = &ppc440spe_emac0_def,
124 .show = &ocp_show_emac_data,
125 },
126 { .vendor = OCP_VENDOR_INVALID
127 }
128};
129
130/* Polarity and triggering settings for internal interrupt sources */
131struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
132 { .polarity = 0xffffffff,
133 .triggering = 0x010f0004,
134 .ext_irq_mask = 0x00000000,
135 },
136 { .polarity = 0xffffffff,
137 .triggering = 0x001f8040,
138 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
139 },
140 { .polarity = 0xffffffff,
141 .triggering = 0x00000000,
142 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
143 },
144 { .polarity = 0xffffffff,
145 .triggering = 0x00000000,
146 .ext_irq_mask = 0x00000000,
147 },
148};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
new file mode 100644
index 000000000000..2216846973b8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.h
@@ -0,0 +1,66 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440spe.h
3 *
4 * PPC440SPe definitions
5 *
6 * Roland Dreier <rolandd@cisco.com>
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2004-2005 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#ifdef __KERNEL__
19#ifndef __PPC_PLATFORMS_PPC440SPE_H
20#define __PPC_PLATFORMS_PPC440SPE_H
21
22#include <linux/config.h>
23
24#include <asm/ibm44x.h>
25
26/* UART */
27#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
28#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
29#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
30#define UART0_INT 0
31#define UART1_INT 1
32#define UART2_INT 37
33
34/* Clock and Power Management */
35#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
36#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
37#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
38#define IBM_CPM_CPU 0x02000000 /* processor core */
39#define IBM_CPM_DMA 0x01000000 /* DMA controller */
40#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
41#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
42#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
43#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
44#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
45#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
46#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
47#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
48#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
49#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
50#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
51#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
52#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
53#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
54#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
55#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
56#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
57
58#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
59 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
60 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
61 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
62 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
63 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
64 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
65#endif /* __PPC_PLATFORMS_PPC440SP_H */
66#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
index d8019eec4704..281b4a2ffb96 100644
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ b/arch/ppc/platforms/4xx/sycamore.c
@@ -88,9 +88,6 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
88void __init 88void __init
89sycamore_setup_arch(void) 89sycamore_setup_arch(void)
90{ 90{
91#define SYCAMORE_PS2_BASE 0xF0100000
92#define SYCAMORE_FPGA_BASE 0xF0300000
93
94 void *fpga_brdc; 91 void *fpga_brdc;
95 unsigned char fpga_brdc_data; 92 unsigned char fpga_brdc_data;
96 void *fpga_enable; 93 void *fpga_enable;
@@ -100,7 +97,7 @@ sycamore_setup_arch(void)
100 97
101 ppc4xx_setup_arch(); 98 ppc4xx_setup_arch();
102 99
103 ibm_ocp_set_emac(0, 1); 100 ibm_ocp_set_emac(0, 0);
104 101
105 kb_data = ioremap(SYCAMORE_PS2_BASE, 8); 102 kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
106 if (!kb_data) { 103 if (!kb_data) {
@@ -111,7 +108,7 @@ sycamore_setup_arch(void)
111 108
112 kb_cs = kb_data + 1; 109 kb_cs = kb_data + 1;
113 110
114 fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8); 111 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
115 if (!fpga_status) { 112 if (!fpga_status) {
116 printk(KERN_CRIT 113 printk(KERN_CRIT
117 "sycamore_setup_arch() fpga_status ioremap failed\n"); 114 "sycamore_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
index 3e7b4e2c8c57..1cd6c824fd62 100644
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ b/arch/ppc/platforms/4xx/sycamore.h
@@ -1,67 +1,52 @@
1/* 1/*
2 * arch/ppc/platforms/4xx/sycamore.h 2 * arch/ppc/platforms/4xx/sycamore.h
3 * 3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC 4 * Sycamore board definitions
5 * 405GPr "Sycamore" evaluation board.
6 * 5 *
7 * Author: Armin Kuster <akuster@mvista.com> 6 * Copyright (c) 2005 DENX Software Engineering
7 * Stefan Roese <sr@denx.de>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * 2000 (c) MontaVista, Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
8 * 17 *
9 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */ 18 */
14 19
15#ifdef __KERNEL__ 20#ifdef __KERNEL__
16#ifndef __ASM_SYCAMORE_H__ 21#ifndef __ASM_SYCAMORE_H__
17#define __ASM_SYCAMORE_H__ 22#define __ASM_SYCAMORE_H__
18 23
24#include <linux/config.h>
19#include <platforms/4xx/ibm405gpr.h> 25#include <platforms/4xx/ibm405gpr.h>
26#include <asm/ppcboot.h>
20 27
21#ifndef __ASSEMBLY__ 28/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
22/*
23 * Data structure defining board information maintained by the boot
24 * ROM on IBM's "Sycamore" evaluation board. An effort has been made to
25 * keep the field names consistent with the 8xx 'bd_t' board info
26 * structures.
27 */
28
29typedef struct board_info {
30 unsigned char bi_s_version[4]; /* Version of this structure */
31 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
32 unsigned int bi_memsize; /* DRAM installed, in bytes */
33 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
34 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
35 unsigned int bi_intfreq; /* Processor speed, in Hz */
36 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
37 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44
45/* Memory map for the IBM "Sycamore" 405GP evaluation board.
46 * Generic 4xx plus RTC. 29 * Generic 4xx plus RTC.
47 */ 30 */
48 31
49extern void *sycamore_rtc_base;
50#define SYCAMORE_RTC_PADDR ((uint)0xf0000000) 32#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
51#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR 33#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
52#define SYCAMORE_RTC_SIZE ((uint)8*1024) 34#define SYCAMORE_RTC_SIZE ((uint)8*1024)
53 35
54#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
55#define BASE_BAUD 201600
56#else
57#define BASE_BAUD 691200 36#define BASE_BAUD 691200
58#endif
59 37
60#define SYCAMORE_PS2_BASE 0xF0100000 38#define SYCAMORE_PS2_BASE 0xF0100000
61#define SYCAMORE_FPGA_BASE 0xF0300000 39
40/* Flash */
41#define PPC40x_FPGA_BASE 0xF0300000
42#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
43#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
44#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
45#define PPC40x_FLASH_LOW 0xFFF00000
46#define PPC40x_FLASH_HIGH 0xFFF80000
47#define PPC40x_FLASH_SIZE 0x80000
62 48
63#define PPC4xx_MACHINE_NAME "IBM Sycamore" 49#define PPC4xx_MACHINE_NAME "IBM Sycamore"
64 50
65#endif /* !__ASSEMBLY__ */
66#endif /* __ASM_SYCAMORE_H__ */ 51#endif /* __ASM_SYCAMORE_H__ */
67#endif /* __KERNEL__ */ 52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
index a33eda4b7489..74cb33182d9f 100644
--- a/arch/ppc/platforms/4xx/walnut.c
+++ b/arch/ppc/platforms/4xx/walnut.c
@@ -90,7 +90,7 @@ walnut_setup_arch(void)
90 90
91 kb_cs = kb_data + 1; 91 kb_cs = kb_data + 1;
92 92
93 fpga_status = ioremap(WALNUT_FPGA_BASE, 8); 93 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
94 if (!fpga_status) { 94 if (!fpga_status) {
95 printk(KERN_CRIT 95 printk(KERN_CRIT
96 "walnut_setup_arch() fpga_status ioremap failed\n"); 96 "walnut_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
index 04cfbf3696b9..dcf2691698c0 100644
--- a/arch/ppc/platforms/4xx/walnut.h
+++ b/arch/ppc/platforms/4xx/walnut.h
@@ -1,72 +1,55 @@
1/* 1/*
2 * arch/ppc/platforms/4xx/walnut.h 2 * arch/ppc/platforms/4xx/walnut.h
3 * 3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC 4 * Walnut board definitions
5 * 405GP "Walnut" evaluation board.
6 * 5 *
7 * Authors: Grant Erickson <grant@lcse.umn.edu>, Frank Rowand 6 * Copyright (c) 2005 DENX Software Engineering
8 * <frank_rowand@mvista.com>, Debbie Chu <debbie_chu@mvista.com> or 7 * Stefan Roese <sr@denx.de>
9 * source@mvista.com
10 * 8 *
11 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 9 * Based on original work by
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 * Frank Rowand <frank_rowand@mvista.com>
12 * Debbie Chu <debbie_chu@mvista.com>
13 * 2000 (c) MontaVista, Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
12 * 19 *
13 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */ 20 */
18 21
19#ifdef __KERNEL__ 22#ifdef __KERNEL__
20#ifndef __ASM_WALNUT_H__ 23#ifndef __ASM_WALNUT_H__
21#define __ASM_WALNUT_H__ 24#define __ASM_WALNUT_H__
22 25
23/* We have a 405GP core */ 26#include <linux/config.h>
24#include <platforms/4xx/ibm405gp.h> 27#include <platforms/4xx/ibm405gp.h>
25 28#include <asm/ppcboot.h>
26#ifndef __ASSEMBLY__
27/*
28 * Data structure defining board information maintained by the boot
29 * ROM on IBM's "Walnut" evaluation board. An effort has been made to
30 * keep the field names consistent with the 8xx 'bd_t' board info
31 * structures.
32 */
33
34typedef struct board_info {
35 unsigned char bi_s_version[4]; /* Version of this structure */
36 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
37 unsigned int bi_memsize; /* DRAM installed, in bytes */
38 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
39 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
40 unsigned int bi_intfreq; /* Processor speed, in Hz */
41 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
42 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
43} bd_t;
44
45/* Some 4xx parts use a different timebase frequency from the internal clock.
46*/
47#define bi_tbfreq bi_intfreq
48
49 29
50/* Memory map for the IBM "Walnut" 405GP evaluation board. 30/* Memory map for the IBM "Walnut" 405GP evaluation board.
51 * Generic 4xx plus RTC. 31 * Generic 4xx plus RTC.
52 */ 32 */
53 33
54extern void *walnut_rtc_base;
55#define WALNUT_RTC_PADDR ((uint)0xf0000000) 34#define WALNUT_RTC_PADDR ((uint)0xf0000000)
56#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR 35#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
57#define WALNUT_RTC_SIZE ((uint)8*1024) 36#define WALNUT_RTC_SIZE ((uint)8*1024)
58 37
59#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
60#define BASE_BAUD 201600
61#else
62#define BASE_BAUD 691200 38#define BASE_BAUD 691200
63#endif
64 39
65#define WALNUT_PS2_BASE 0xF0100000 40#define WALNUT_PS2_BASE 0xF0100000
66#define WALNUT_FPGA_BASE 0xF0300000 41
42/* Flash */
43#define PPC40x_FPGA_BASE 0xF0300000
44#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
45#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
46#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
47#define PPC40x_FLASH_LOW 0xFFF00000
48#define PPC40x_FLASH_HIGH 0xFFF80000
49#define PPC40x_FLASH_SIZE 0x80000
50#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE
67 51
68#define PPC4xx_MACHINE_NAME "IBM Walnut" 52#define PPC4xx_MACHINE_NAME "IBM Walnut"
69 53
70#endif /* !__ASSEMBLY__ */
71#endif /* __ASM_WALNUT_H__ */ 54#endif /* __ASM_WALNUT_H__ */
72#endif /* __KERNEL__ */ 55#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
new file mode 100644
index 000000000000..e60f4bd437ec
--- /dev/null
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -0,0 +1,395 @@
1/*
2 * arch/ppc/platforms/4xx/yucca.c
3 *
4 * Yucca board specific routines
5 *
6 * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
7 *
8 * Copyright 2004-2005 MontaVista Software Inc.
9 * Copyright (c) 2005 Cisco Systems. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/config.h>
18#include <linux/stddef.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/errno.h>
22#include <linux/reboot.h>
23#include <linux/pci.h>
24#include <linux/kdev_t.h>
25#include <linux/types.h>
26#include <linux/major.h>
27#include <linux/blkdev.h>
28#include <linux/console.h>
29#include <linux/delay.h>
30#include <linux/ide.h>
31#include <linux/initrd.h>
32#include <linux/seq_file.h>
33#include <linux/root_dev.h>
34#include <linux/tty.h>
35#include <linux/serial.h>
36#include <linux/serial_core.h>
37
38#include <asm/system.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
41#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/ocp.h>
45#include <asm/pci-bridge.h>
46#include <asm/time.h>
47#include <asm/todc.h>
48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h>
51
52#include <syslib/ibm44x_common.h>
53#include <syslib/ibm440gx_common.h>
54#include <syslib/ibm440sp_common.h>
55#include <syslib/ppc440spe_pcie.h>
56
57extern bd_t __res;
58
59static struct ibm44x_clocks clocks __initdata;
60
61static void __init
62yucca_calibrate_decr(void)
63{
64 unsigned int freq;
65
66 if (mfspr(SPRN_CCR1) & CCR1_TCS)
67 freq = YUCCA_TMR_CLK;
68 else
69 freq = clocks.cpu;
70
71 ibm44x_calibrate_decr(freq);
72}
73
74static int
75yucca_show_cpuinfo(struct seq_file *m)
76{
77 seq_printf(m, "vendor\t\t: AMCC\n");
78 seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
79
80 return 0;
81}
82
83static enum {
84 HOSE_UNKNOWN,
85 HOSE_PCIX,
86 HOSE_PCIE0,
87 HOSE_PCIE1,
88 HOSE_PCIE2
89} hose_type[4];
90
91static inline int
92yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
93{
94 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
95
96 if (hose_type[hose->index] == HOSE_PCIX) {
97 static char pci_irq_table[][4] =
98 /*
99 * PCI IDSEL/INTPIN->INTLINE
100 * A B C D
101 */
102 {
103 { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
104 };
105 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
106 return PCI_IRQ_TABLE_LOOKUP;
107 } else if (hose_type[hose->index] == HOSE_PCIE0) {
108 static char pci_irq_table[][4] =
109 /*
110 * PCI IDSEL/INTPIN->INTLINE
111 * A B C D
112 */
113 {
114 { 96, 97, 98, 99 },
115 };
116 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
117 return PCI_IRQ_TABLE_LOOKUP;
118 } else if (hose_type[hose->index] == HOSE_PCIE1) {
119 static char pci_irq_table[][4] =
120 /*
121 * PCI IDSEL/INTPIN->INTLINE
122 * A B C D
123 */
124 {
125 { 100, 101, 102, 103 },
126 };
127 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
128 return PCI_IRQ_TABLE_LOOKUP;
129 } else if (hose_type[hose->index] == HOSE_PCIE2) {
130 static char pci_irq_table[][4] =
131 /*
132 * PCI IDSEL/INTPIN->INTLINE
133 * A B C D
134 */
135 {
136 { 104, 105, 106, 107 },
137 };
138 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
139 return PCI_IRQ_TABLE_LOOKUP;
140 }
141 return -1;
142}
143
144static void __init yucca_set_emacdata(void)
145{
146 struct ocp_def *def;
147 struct ocp_func_emac_data *emacdata;
148
149 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
150 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
151 emacdata = def->additions;
152 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
153 emacdata->phy_mode = PHY_MODE_GMII;
154 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
155}
156
157static int __init yucca_pcie_card_present(int port)
158{
159 void __iomem *pcie_fpga_base;
160 u16 reg;
161
162 pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
163 reg = in_be16(pcie_fpga_base + FPGA_REG1C);
164 iounmap(pcie_fpga_base);
165
166 switch(port) {
167 case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
168 case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
169 case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
170 default: return 0;
171 }
172}
173
174/*
175 * For the given slot, set rootpoint mode, send power to the slot,
176 * turn on the green LED and turn off the yellow LED, enable the clock
177 * and turn off reset.
178 */
179static void __init yucca_setup_pcie_fpga_rootpoint(int port)
180{
181 void __iomem *pcie_reg_fpga_base;
182 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
183
184 pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
185
186 switch(port) {
187 case 0:
188 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
189 endpoint = 0;
190 power = FPGA_REG1A_PE0_PWRON;
191 green_led = FPGA_REG1A_PE0_GLED;
192 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
193 yellow_led = FPGA_REG1A_PE0_YLED;
194 reset_off = FPGA_REG1C_PE0_PERST;
195 break;
196 case 1:
197 rootpoint = 0;
198 endpoint = FPGA_REG1C_PE1_ENDPOINT;
199 power = FPGA_REG1A_PE1_PWRON;
200 green_led = FPGA_REG1A_PE1_GLED;
201 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
202 yellow_led = FPGA_REG1A_PE1_YLED;
203 reset_off = FPGA_REG1C_PE1_PERST;
204 break;
205 case 2:
206 rootpoint = 0;
207 endpoint = FPGA_REG1C_PE2_ENDPOINT;
208 power = FPGA_REG1A_PE2_PWRON;
209 green_led = FPGA_REG1A_PE2_GLED;
210 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
211 yellow_led = FPGA_REG1A_PE2_YLED;
212 reset_off = FPGA_REG1C_PE2_PERST;
213 break;
214
215 default:
216 return;
217 }
218
219 out_be16(pcie_reg_fpga_base + FPGA_REG1A,
220 ~(power | clock | green_led) &
221 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
222 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
223 ~(endpoint | reset_off) &
224 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
225
226 /*
227 * Leave device in reset for a while after powering on the
228 * slot to give it a chance to initialize.
229 */
230 mdelay(250);
231
232 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
233 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
234
235 iounmap(pcie_reg_fpga_base);
236}
237
238static void __init
239yucca_setup_hoses(void)
240{
241 struct pci_controller *hose;
242 char name[20];
243 int i;
244
245 if (0 && ppc440spe_init_pcie()) {
246 printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
247 return;
248 }
249
250 for (i = 0; i <= 2; ++i) {
251 if (!yucca_pcie_card_present(i))
252 continue;
253
254 printk(KERN_INFO "PCIE%d: card present\n", i);
255 yucca_setup_pcie_fpga_rootpoint(i);
256 if (ppc440spe_init_pcie_rootport(i)) {
257 printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
258 continue;
259 }
260
261 hose = pcibios_alloc_controller();
262 if (!hose)
263 return;
264
265 sprintf(name, "PCIE%d host bridge", i);
266 pci_init_resource(&hose->io_resource,
267 YUCCA_PCIX_LOWER_IO,
268 YUCCA_PCIX_UPPER_IO,
269 IORESOURCE_IO,
270 name);
271
272 hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
273 i * YUCCA_PCIE_MEM_SIZE;
274 hose->mem_space.end = hose->mem_space.start +
275 YUCCA_PCIE_MEM_SIZE - 1;
276
277 pci_init_resource(&hose->mem_resources[0],
278 hose->mem_space.start,
279 hose->mem_space.end,
280 IORESOURCE_MEM,
281 name);
282
283 hose->first_busno = 0;
284 hose->last_busno = 15;
285 hose_type[hose->index] = HOSE_PCIE0 + i;
286
287 ppc440spe_setup_pcie(hose, i);
288 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
289 }
290
291 ppc_md.pci_swizzle = common_swizzle;
292 ppc_md.pci_map_irq = yucca_map_irq;
293}
294
295TODC_ALLOC();
296
297static void __init
298yucca_early_serial_map(void)
299{
300 struct uart_port port;
301
302 /* Setup ioremapped serial port access */
303 memset(&port, 0, sizeof(port));
304 port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
305 port.irq = UART0_INT;
306 port.uartclk = clocks.uart0;
307 port.regshift = 0;
308 port.iotype = SERIAL_IO_MEM;
309 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
310 port.line = 0;
311
312 if (early_serial_setup(&port) != 0) {
313 printk("Early serial init of port 0 failed\n");
314 }
315
316 port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
317 port.irq = UART1_INT;
318 port.uartclk = clocks.uart1;
319 port.line = 1;
320
321 if (early_serial_setup(&port) != 0) {
322 printk("Early serial init of port 1 failed\n");
323 }
324
325 port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
326 port.irq = UART2_INT;
327 port.uartclk = BASE_BAUD;
328 port.line = 2;
329
330 if (early_serial_setup(&port) != 0) {
331 printk("Early serial init of port 2 failed\n");
332 }
333}
334
335static void __init
336yucca_setup_arch(void)
337{
338 yucca_set_emacdata();
339
340#if !defined(CONFIG_BDI_SWITCH)
341 /*
342 * The Abatron BDI JTAG debugger does not tolerate others
343 * mucking with the debug registers.
344 */
345 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
346#endif
347
348 /*
349 * Determine various clocks.
350 * To be completely correct we should get SysClk
351 * from FPGA, because it can be changed by on-board switches
352 * --ebs
353 */
354 /* 440GX and 440SPe clocking is the same - rd */
355 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
356 ocp_sys_info.opb_bus_freq = clocks.opb;
357
358 /* init to some ~sane value until calibrate_delay() runs */
359 loops_per_jiffy = 50000000/HZ;
360
361 /* Setup PCIXn host bridges */
362 yucca_setup_hoses();
363
364#ifdef CONFIG_BLK_DEV_INITRD
365 if (initrd_start)
366 ROOT_DEV = Root_RAM0;
367 else
368#endif
369#ifdef CONFIG_ROOT_NFS
370 ROOT_DEV = Root_NFS;
371#else
372 ROOT_DEV = Root_HDA1;
373#endif
374
375 yucca_early_serial_map();
376
377 /* Identify the system */
378 printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
379}
380
381void __init platform_init(unsigned long r3, unsigned long r4,
382 unsigned long r5, unsigned long r6, unsigned long r7)
383{
384 ibm44x_platform_init(r3, r4, r5, r6, r7);
385
386 ppc_md.setup_arch = yucca_setup_arch;
387 ppc_md.show_cpuinfo = yucca_show_cpuinfo;
388 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
389 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
390
391 ppc_md.calibrate_decr = yucca_calibrate_decr;
392#ifdef CONFIG_KGDB
393 ppc_md.early_serial_map = yucca_early_serial_map;
394#endif
395}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
new file mode 100644
index 000000000000..01a4afea1514
--- /dev/null
+++ b/arch/ppc/platforms/4xx/yucca.h
@@ -0,0 +1,111 @@
1/*
2 * arch/ppc/platforms/4xx/yucca.h
3 *
4 * Yucca board definitions
5 *
6 * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
7 *
8 * Copyright 2004-2005 MontaVista Software Inc.
9 * Copyright (c) 2005 Cisco Systems. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __ASM_YUCCA_H__
20#define __ASM_YUCCA_H__
21
22#include <linux/config.h>
23#include <platforms/4xx/ppc440spe.h>
24
25/* F/W TLB mapping used in bootloader glue to reset EMAC */
26#define PPC44x_EMAC0_MR0 0xa0000800
27
28/* Location of MAC addresses in PIBS image */
29#define PIBS_FLASH_BASE 0xffe00000
30#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
31
32/* External timer clock frequency */
33#define YUCCA_TMR_CLK 25000000
34
35/*
36 * FPGA registers
37 */
38#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
39#define YUCCA_FPGA_REG_SIZE 0x24
40
41#define FPGA_REG1A 0x1a
42
43#define FPGA_REG1A_PE0_GLED 0x8000
44#define FPGA_REG1A_PE1_GLED 0x4000
45#define FPGA_REG1A_PE2_GLED 0x2000
46#define FPGA_REG1A_PE0_YLED 0x1000
47#define FPGA_REG1A_PE1_YLED 0x0800
48#define FPGA_REG1A_PE2_YLED 0x0400
49#define FPGA_REG1A_PE0_PWRON 0x0200
50#define FPGA_REG1A_PE1_PWRON 0x0100
51#define FPGA_REG1A_PE2_PWRON 0x0080
52#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
53#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
54#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
55#define FPGA_REG1A_PE_SPREAD0 0x0008
56#define FPGA_REG1A_PE_SPREAD1 0x0004
57#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
58#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
59
60#define FPGA_REG1C 0x1c
61
62#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
63#define FPGA_REG1C_PE1_ENDPOINT 0x4000
64#define FPGA_REG1C_PE2_ENDPOINT 0x2000
65#define FPGA_REG1C_PE0_PRSNT 0x1000
66#define FPGA_REG1C_PE1_PRSNT 0x0800
67#define FPGA_REG1C_PE2_PRSNT 0x0400
68#define FPGA_REG1C_PE0_WAKE 0x0080
69#define FPGA_REG1C_PE1_WAKE 0x0040
70#define FPGA_REG1C_PE2_WAKE 0x0020
71#define FPGA_REG1C_PE0_PERST 0x0010
72#define FPGA_REG1C_PE1_PERST 0x0008
73#define FPGA_REG1C_PE2_PERST 0x0004
74
75/*
76 * Serial port defines
77 */
78#define RS_TABLE_SIZE 3
79
80/* PIBS defined UART mappings, used before early_serial_setup */
81#define UART0_IO_BASE 0xa0000200
82#define UART1_IO_BASE 0xa0000300
83#define UART2_IO_BASE 0xa0000600
84
85#define BASE_BAUD 11059200
86#define STD_UART_OP(num) \
87 { 0, BASE_BAUD, 0, UART##num##_INT, \
88 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
89 iomem_base: (void*)UART##num##_IO_BASE, \
90 io_type: SERIAL_IO_MEM},
91
92#define SERIAL_PORT_DFNS \
93 STD_UART_OP(0) \
94 STD_UART_OP(1) \
95 STD_UART_OP(2)
96
97/* PCI support */
98#define YUCCA_PCIX_LOWER_IO 0x00000000
99#define YUCCA_PCIX_UPPER_IO 0x0000ffff
100#define YUCCA_PCIX_LOWER_MEM 0x80000000
101#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
102#define YUCCA_PCIE_LOWER_MEM 0x90000000
103#define YUCCA_PCIE_MEM_SIZE 0x10000000
104
105#define YUCCA_PCIX_MEM_SIZE 0x10000000
106#define YUCCA_PCIX_MEM_OFFSET 0x00000000
107#define YUCCA_PCIE_MEM_SIZE 0x10000000
108#define YUCCA_PCIE_MEM_OFFSET 0x00000000
109
110#endif /* __ASM_YUCCA_H__ */
111#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
index bd3ac0136756..16ad092d8a06 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -45,6 +45,8 @@
45 45
46#include <mm/mmu_decl.h> 46#include <mm/mmu_decl.h>
47 47
48#include <syslib/ppc85xx_rio.h>
49
48#include <platforms/85xx/mpc85xx_ads_common.h> 50#include <platforms/85xx/mpc85xx_ads_common.h>
49 51
50#ifndef CONFIG_PCI 52#ifndef CONFIG_PCI
@@ -189,3 +191,11 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
189} 191}
190 192
191#endif /* CONFIG_PCI */ 193#endif /* CONFIG_PCI */
194
195#ifdef CONFIG_RAPIDIO
196void platform_rio_init(void)
197{
198 /* 512MB RIO LAW at 0xc0000000 */
199 mpc85xx_rio_setup(0xc0000000, 0x20000000);
200}
201#endif /* CONFIG_RAPIDIO */
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index 1e1b85f8193a..15ce9d070634 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -37,6 +37,7 @@
37#include <linux/module.h> 37#include <linux/module.h>
38#include <linux/fsl_devices.h> 38#include <linux/fsl_devices.h>
39#include <linux/interrupt.h> 39#include <linux/interrupt.h>
40#include <linux/rio.h>
40 41
41#include <asm/system.h> 42#include <asm/system.h>
42#include <asm/pgtable.h> 43#include <asm/pgtable.h>
@@ -57,6 +58,7 @@
57 58
58#include <syslib/cpm2_pic.h> 59#include <syslib/cpm2_pic.h>
59#include <syslib/ppc85xx_common.h> 60#include <syslib/ppc85xx_common.h>
61#include <syslib/ppc85xx_rio.h>
60 62
61 63
62unsigned char __res[sizeof(bd_t)]; 64unsigned char __res[sizeof(bd_t)];
@@ -273,6 +275,18 @@ int mpc85xx_exclude_device(u_char bus, u_char devfn)
273} 275}
274#endif /* CONFIG_PCI */ 276#endif /* CONFIG_PCI */
275 277
278#ifdef CONFIG_RAPIDIO
279void
280platform_rio_init(void)
281{
282 /*
283 * The STx firmware configures the RapidIO Local Access Window
284 * at 0xc0000000 with a size of 512MB.
285 */
286 mpc85xx_rio_setup(0xc0000000, 0x20000000);
287}
288#endif /* CONFIG_RAPIDIO */
289
276void __init 290void __init
277platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 291platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
278 unsigned long r6, unsigned long r7) 292 unsigned long r6, unsigned long r7)
diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c
index b1324564456e..b9d844f88c2b 100644
--- a/arch/ppc/platforms/ev64360.c
+++ b/arch/ppc/platforms/ev64360.c
@@ -52,6 +52,8 @@ static u32 ev64360_bus_frequency;
52 52
53unsigned char __res[sizeof(bd_t)]; 53unsigned char __res[sizeof(bd_t)];
54 54
55TODC_ALLOC();
56
55static int __init 57static int __init
56ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) 58ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57{ 59{
@@ -182,6 +184,9 @@ ev64360_setup_peripherals(void)
182 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); 184 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
183 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); 185 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
184 186
187 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
188 ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
189
185 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, 190 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
186 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); 191 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
187 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); 192 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
@@ -496,6 +501,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
496 ppc_md.power_off = ev64360_power_off; 501 ppc_md.power_off = ev64360_power_off;
497 ppc_md.halt = ev64360_halt; 502 ppc_md.halt = ev64360_halt;
498 ppc_md.find_end_of_memory = ev64360_find_end_of_memory; 503 ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
504 ppc_md.init = NULL;
505
506 ppc_md.time_init = todc_time_init;
507 ppc_md.set_rtc_time = todc_set_rtc_time;
508 ppc_md.get_rtc_time = todc_get_rtc_time;
509 ppc_md.nvram_read_val = todc_direct_read_val;
510 ppc_md.nvram_write_val = todc_direct_write_val;
499 ppc_md.calibrate_decr = ev64360_calibrate_decr; 511 ppc_md.calibrate_decr = ev64360_calibrate_decr;
500 512
501#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) 513#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index b4ef15b45c4a..5bd33baac243 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common.o
15obj-$(CONFIG_440GP) += ibm440gp_common.o 15obj-$(CONFIG_440GP) += ibm440gp_common.o
16obj-$(CONFIG_440GX) += ibm440gx_common.o 16obj-$(CONFIG_440GX) += ibm440gx_common.o
17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o 17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
18obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
18ifeq ($(CONFIG_4xx),y) 19ifeq ($(CONFIG_4xx),y)
19ifeq ($(CONFIG_VIRTEX_II_PRO),y) 20ifeq ($(CONFIG_VIRTEX_II_PRO),y)
20obj-$(CONFIG_40x) += xilinx_pic.o 21obj-$(CONFIG_40x) += xilinx_pic.o
@@ -32,6 +33,7 @@ obj-$(CONFIG_PPC4xx_DMA) += ppc4xx_dma.o
32obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o 33obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o
33ifeq ($(CONFIG_40x),y) 34ifeq ($(CONFIG_40x),y)
34obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o 35obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o
36obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
35endif 37endif
36endif 38endif
37obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \ 39obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
@@ -46,12 +48,14 @@ obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o
46obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o 48obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
47obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o 49obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o
48obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o 50obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
51obj-$(CONFIG_EV64360) += todc_time.o
49obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o 52obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o
50obj-$(CONFIG_GEMINI) += open_pic.o 53obj-$(CONFIG_GEMINI) += open_pic.o
51obj-$(CONFIG_GT64260) += gt64260_pic.o 54obj-$(CONFIG_GT64260) += gt64260_pic.o
52obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o 55obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o
53obj-$(CONFIG_HDPU) += pci_auto.o 56obj-$(CONFIG_HDPU) += pci_auto.o
54obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o 57obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o
58obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o
55obj-$(CONFIG_KATANA) += pci_auto.o 59obj-$(CONFIG_KATANA) += pci_auto.o
56obj-$(CONFIG_MV64360) += mv64360_pic.o 60obj-$(CONFIG_MV64360) += mv64360_pic.o
57obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o 61obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o
diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c
index 417d4cff77a0..cdafda127d81 100644
--- a/arch/ppc/syslib/ibm440sp_common.c
+++ b/arch/ppc/syslib/ibm440sp_common.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/ppc/syslib/ibm440sp_common.c 2 * arch/ppc/syslib/ibm440sp_common.c
3 * 3 *
4 * PPC440SP system library 4 * PPC440SP/PPC440SPe system library
5 * 5 *
6 * Matt Porter <mporter@kernel.crashing.org> 6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc. 7 * Copyright 2002-2005 MontaVista Software Inc.
@@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_of_memory(void)
35 u32 mem_size = 0; 35 u32 mem_size = 0;
36 36
37 /* Read two bank sizes and sum */ 37 /* Read two bank sizes and sum */
38 for (i=0; i<2; i++) 38 for (i=0; i< MQ0_NUM_BANKS; i++)
39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { 39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) {
40 case MQ0_CONFIG_SIZE_8M: 40 case MQ0_CONFIG_SIZE_8M:
41 mem_size += PPC44x_MEM_SIZE_8M; 41 mem_size += PPC44x_MEM_SIZE_8M;
diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c
index 5152c8e41340..71db11d22158 100644
--- a/arch/ppc/syslib/ibm44x_common.c
+++ b/arch/ppc/syslib/ibm44x_common.c
@@ -20,6 +20,7 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial.h> 21#include <linux/serial.h>
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/initrd.h>
23 24
24#include <asm/ibm44x.h> 25#include <asm/ibm44x.h>
25#include <asm/mmu.h> 26#include <asm/mmu.h>
@@ -214,9 +215,20 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo
214/* Called from machine_check_exception */ 215/* Called from machine_check_exception */
215void platform_machine_check(struct pt_regs *regs) 216void platform_machine_check(struct pt_regs *regs)
216{ 217{
218#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
219 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
220 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
221 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
222 mfdcr(DCRN_PLB0_BESRL));
223 printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
224 mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
225 mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
226 mfdcr(DCRN_PLB1_BESRL));
227#else
217 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", 228 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
218 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), 229 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
219 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR)); 230 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
231#endif
220 printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n", 232 printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
221 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL), 233 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
222 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1)); 234 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
diff --git a/arch/ppc/syslib/ppc405_pci.c b/arch/ppc/syslib/ppc405_pci.c
index 81c83bf98df4..d6d838b16dac 100644
--- a/arch/ppc/syslib/ppc405_pci.c
+++ b/arch/ppc/syslib/ppc405_pci.c
@@ -89,13 +89,6 @@ ppc4xx_find_bridges(void)
89 isa_mem_base = 0; 89 isa_mem_base = 0;
90 pci_dram_offset = 0; 90 pci_dram_offset = 0;
91 91
92#if (PSR_PCI_ARBIT_EN > 1)
93 /* Check if running in slave mode */
94 if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
95 printk("Running as PCI slave, kernel PCI disabled !\n");
96 return;
97 }
98#endif
99 /* Setup PCI32 hose */ 92 /* Setup PCI32 hose */
100 hose_a = pcibios_alloc_controller(); 93 hose_a = pcibios_alloc_controller();
101 if (!hose_a) 94 if (!hose_a)
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
new file mode 100644
index 000000000000..1509fc1ddfb6
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -0,0 +1,442 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/config.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16
17#include <asm/reg.h>
18#include <asm/io.h>
19#include <asm/ibm44x.h>
20
21#include "ppc440spe_pcie.h"
22
23static int
24pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
25 int len, u32 *val)
26{
27 struct pci_controller *hose = bus->sysdata;
28
29 if (PCI_SLOT(devfn) != 1)
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 offset += devfn << 12;
33
34 /*
35 * Note: the caller has already checked that offset is
36 * suitably aligned and that len is 1, 2 or 4.
37 */
38 switch (len) {
39 case 1:
40 *val = in_8(hose->cfg_data + offset);
41 break;
42 case 2:
43 *val = in_le16(hose->cfg_data + offset);
44 break;
45 default:
46 *val = in_le32(hose->cfg_data + offset);
47 break;
48 }
49
50 if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
51
52 return PCIBIOS_SUCCESSFUL;
53}
54
55static int
56pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
57 int len, u32 val)
58{
59 struct pci_controller *hose = bus->sysdata;
60
61 if (PCI_SLOT(devfn) != 1)
62 return PCIBIOS_DEVICE_NOT_FOUND;
63
64 offset += devfn << 12;
65
66 switch (len) {
67 case 1:
68 out_8(hose->cfg_data + offset, val);
69 break;
70 case 2:
71 out_le16(hose->cfg_data + offset, val);
72 break;
73 default:
74 out_le32(hose->cfg_data + offset, val);
75 break;
76 }
77 return PCIBIOS_SUCCESSFUL;
78}
79
80static struct pci_ops pcie_pci_ops =
81{
82 .read = pcie_read_config,
83 .write = pcie_write_config
84};
85
86enum {
87 PTYPE_ENDPOINT = 0x0,
88 PTYPE_LEGACY_ENDPOINT = 0x1,
89 PTYPE_ROOT_PORT = 0x4,
90
91 LNKW_X1 = 0x1,
92 LNKW_X4 = 0x4,
93 LNKW_X8 = 0x8
94};
95
96static void check_error(void)
97{
98 u32 valPE0, valPE1, valPE2;
99
100 /* SDR0_PEGPLLLCT1 reset */
101 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
102 printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0);
103 }
104
105 valPE0 = SDR_READ(PESDR0_RCSSET);
106 valPE1 = SDR_READ(PESDR1_RCSSET);
107 valPE2 = SDR_READ(PESDR2_RCSSET);
108
109 /* SDR0_PExRCSSET rstgu */
110 if ( !(valPE0 & 0x01000000) ||
111 !(valPE1 & 0x01000000) ||
112 !(valPE2 & 0x01000000)) {
113 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
114 }
115
116 /* SDR0_PExRCSSET rstdl */
117 if ( !(valPE0 & 0x00010000) ||
118 !(valPE1 & 0x00010000) ||
119 !(valPE2 & 0x00010000)) {
120 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
121 }
122
123 /* SDR0_PExRCSSET rstpyn */
124 if ( (valPE0 & 0x00001000) ||
125 (valPE1 & 0x00001000) ||
126 (valPE2 & 0x00001000)) {
127 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
128 }
129
130 /* SDR0_PExRCSSET hldplb */
131 if ( (valPE0 & 0x10000000) ||
132 (valPE1 & 0x10000000) ||
133 (valPE2 & 0x10000000)) {
134 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
135 }
136
137 /* SDR0_PExRCSSET rdy */
138 if ( (valPE0 & 0x00100000) ||
139 (valPE1 & 0x00100000) ||
140 (valPE2 & 0x00100000)) {
141 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
142 }
143
144 /* SDR0_PExRCSSET shutdown */
145 if ( (valPE0 & 0x00000100) ||
146 (valPE1 & 0x00000100) ||
147 (valPE2 & 0x00000100)) {
148 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
149 }
150}
151
152/*
153 * Initialize PCI Express core as described in User Manual section 27.12.1
154 */
155int ppc440spe_init_pcie(void)
156{
157 /* Set PLL clock receiver to LVPECL */
158 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
159
160 check_error();
161
162 printk(KERN_INFO "PCIE initialization OK\n");
163
164 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
165 printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
166 SDR_READ(PESDR0_PLLLCT2));
167
168 /* De-assert reset of PCIe PLL, wait for lock */
169 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
170 udelay(3);
171
172 return 0;
173}
174
175int ppc440spe_init_pcie_rootport(int port)
176{
177 static int core_init;
178 void __iomem *utl_base;
179 u32 val = 0;
180 int i;
181
182 if (!core_init) {
183 ++core_init;
184 i = ppc440spe_init_pcie();
185 if (i)
186 return i;
187 }
188
189 /*
190 * Initialize various parts of the PCI Express core for our port:
191 *
192 * - Set as a root port and enable max width
193 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
194 * - Set up UTL configuration.
195 * - Increase SERDES drive strength to levels suggested by AMCC.
196 * - De-assert RSTPYN, RSTDL and RSTGU.
197 */
198 switch (port) {
199 case 0:
200 SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
201
202 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
203 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
204
205 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
206 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
207 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
208 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
209 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
210 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
211 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
212 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
213
214 SDR_WRITE(PESDR0_RCSSET,
215 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
216 break;
217
218 case 1:
219 SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
220
221 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
222 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
223
224 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
225 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
226 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
227 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
228
229 SDR_WRITE(PESDR1_RCSSET,
230 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
231 break;
232
233 case 2:
234 SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
235
236 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
237 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
238
239 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
240 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
241 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
242 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
243
244 SDR_WRITE(PESDR2_RCSSET,
245 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
246 break;
247 }
248
249 mdelay(1000);
250
251 switch (port) {
252 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
253 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
254 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
255 }
256
257 if (!(val & (1 << 20)))
258 printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
259 else
260 printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
261
262 switch (port) {
263 case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
264 case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
265 case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
266 }
267
268 /*
269 * Map UTL registers at 0xc_1000_0n00
270 */
271 switch (port) {
272 case 0:
273 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
274 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
275 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
276 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
277 break;
278
279 case 1:
280 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
281 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
282 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
283 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
284 break;
285
286 case 2:
287 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
288 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
289 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
290 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
291 }
292
293 utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
294
295 /*
296 * Set buffer allocations and then assert VRB and TXE.
297 */
298 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
299 out_be32(utl_base + PEUTL_INTR, 0x02000000);
300 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
301 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
302 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
303 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
304 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
305 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
306
307 iounmap(utl_base);
308
309 /*
310 * We map PCI Express configuration access into the 512MB regions
311 * PCIE0: 0xc_4000_0000
312 * PCIE1: 0xc_8000_0000
313 * PCIE2: 0xc_c000_0000
314 */
315 switch (port) {
316 case 0:
317 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
318 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
319 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
320 break;
321
322 case 1:
323 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
324 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
325 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
326 break;
327
328 case 2:
329 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
330 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
331 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
332 break;
333 }
334
335 /*
336 * Check for VC0 active and assert RDY.
337 */
338 switch (port) {
339 case 0:
340 if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
341 printk(KERN_WARNING "PCIE0: VC0 not active\n");
342 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
343 break;
344 case 1:
345 if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
346 printk(KERN_WARNING "PCIE0: VC0 not active\n");
347 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
348 break;
349 case 2:
350 if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
351 printk(KERN_WARNING "PCIE0: VC0 not active\n");
352 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
353 break;
354 }
355
356#if 0
357 /* Dump all config regs */
358 for (i = 0x300; i <= 0x320; ++i)
359 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
360 for (i = 0x340; i <= 0x353; ++i)
361 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
362 for (i = 0x370; i <= 0x383; ++i)
363 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
364 for (i = 0x3a0; i <= 0x3a2; ++i)
365 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
366 for (i = 0x3c0; i <= 0x3c3; ++i)
367 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
368#endif
369
370 mdelay(100);
371
372 return 0;
373}
374
375void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
376{
377 void __iomem *mbase;
378
379 /*
380 * Map 16MB, which is enough for 4 bits of bus #
381 */
382 hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000,
383 1 << 24);
384 hose->ops = &pcie_pci_ops;
385
386 /*
387 * Set bus numbers on our root port
388 */
389 mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096);
390 out_8(mbase + PCI_PRIMARY_BUS, 0);
391 out_8(mbase + PCI_SECONDARY_BUS, 0);
392
393 /*
394 * Set up outbound translation to hose->mem_space from PLB
395 * addresses at an offset of 0xd_0000_0000. We set the low
396 * bits of the mask to 11 to turn off splitting into 8
397 * subregions and to enable the outbound translation.
398 */
399 out_le32(mbase + PECFG_POM0LAH, 0);
400 out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start);
401
402 switch (port) {
403 case 0:
404 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
405 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start);
406 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
407 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
408 ~(hose->mem_space.end - hose->mem_space.start) | 3);
409 break;
410 case 1:
411 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
412 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start);
413 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
414 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
415 ~(hose->mem_space.end - hose->mem_space.start) | 3);
416
417 break;
418 case 2:
419 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
420 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start);
421 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
422 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
423 ~(hose->mem_space.end - hose->mem_space.start) | 3);
424 break;
425 }
426
427 /* Set up 16GB inbound memory window at 0 */
428 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
429 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
430 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
431 out_le32(mbase + PECFG_BAR0LMPA, 0);
432 out_le32(mbase + PECFG_PIM0LAL, 0);
433 out_le32(mbase + PECFG_PIM0LAH, 0);
434 out_le32(mbase + PECFG_PIMEN, 0x1);
435
436 /* Enable I/O, Mem, and Busmaster cycles */
437 out_le16(mbase + PCI_COMMAND,
438 in_le16(mbase + PCI_COMMAND) |
439 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
440
441 iounmap(mbase);
442}
diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h
new file mode 100644
index 000000000000..55b765ad3272
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H
12#define __PPC_SYSLIB_PPC440SPE_PCIE_H
13
14#define DCRN_SDR0_CFGADDR 0x00e
15#define DCRN_SDR0_CFGDATA 0x00f
16
17#define DCRN_PCIE0_BASE 0x100
18#define DCRN_PCIE1_BASE 0x120
19#define DCRN_PCIE2_BASE 0x140
20#define PCIE0 DCRN_PCIE0_BASE
21#define PCIE1 DCRN_PCIE1_BASE
22#define PCIE2 DCRN_PCIE2_BASE
23
24#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
25#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
26#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
27#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
28#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
29#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
30#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
31#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
32#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
33#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
34#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
35#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
36#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
37#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
38
39/*
40 * System DCRs (SDRs)
41 */
42#define PESDR0_PLLLCT1 0x03a0
43#define PESDR0_PLLLCT2 0x03a1
44#define PESDR0_PLLLCT3 0x03a2
45
46#define PESDR0_UTLSET1 0x0300
47#define PESDR0_UTLSET2 0x0301
48#define PESDR0_DLPSET 0x0302
49#define PESDR0_LOOP 0x0303
50#define PESDR0_RCSSET 0x0304
51#define PESDR0_RCSSTS 0x0305
52#define PESDR0_HSSL0SET1 0x0306
53#define PESDR0_HSSL0SET2 0x0307
54#define PESDR0_HSSL0STS 0x0308
55#define PESDR0_HSSL1SET1 0x0309
56#define PESDR0_HSSL1SET2 0x030a
57#define PESDR0_HSSL1STS 0x030b
58#define PESDR0_HSSL2SET1 0x030c
59#define PESDR0_HSSL2SET2 0x030d
60#define PESDR0_HSSL2STS 0x030e
61#define PESDR0_HSSL3SET1 0x030f
62#define PESDR0_HSSL3SET2 0x0310
63#define PESDR0_HSSL3STS 0x0311
64#define PESDR0_HSSL4SET1 0x0312
65#define PESDR0_HSSL4SET2 0x0313
66#define PESDR0_HSSL4STS 0x0314
67#define PESDR0_HSSL5SET1 0x0315
68#define PESDR0_HSSL5SET2 0x0316
69#define PESDR0_HSSL5STS 0x0317
70#define PESDR0_HSSL6SET1 0x0318
71#define PESDR0_HSSL6SET2 0x0319
72#define PESDR0_HSSL6STS 0x031a
73#define PESDR0_HSSL7SET1 0x031b
74#define PESDR0_HSSL7SET2 0x031c
75#define PESDR0_HSSL7STS 0x031d
76#define PESDR0_HSSCTLSET 0x031e
77#define PESDR0_LANE_ABCD 0x031f
78#define PESDR0_LANE_EFGH 0x0320
79
80#define PESDR1_UTLSET1 0x0340
81#define PESDR1_UTLSET2 0x0341
82#define PESDR1_DLPSET 0x0342
83#define PESDR1_LOOP 0x0343
84#define PESDR1_RCSSET 0x0344
85#define PESDR1_RCSSTS 0x0345
86#define PESDR1_HSSL0SET1 0x0346
87#define PESDR1_HSSL0SET2 0x0347
88#define PESDR1_HSSL0STS 0x0348
89#define PESDR1_HSSL1SET1 0x0349
90#define PESDR1_HSSL1SET2 0x034a
91#define PESDR1_HSSL1STS 0x034b
92#define PESDR1_HSSL2SET1 0x034c
93#define PESDR1_HSSL2SET2 0x034d
94#define PESDR1_HSSL2STS 0x034e
95#define PESDR1_HSSL3SET1 0x034f
96#define PESDR1_HSSL3SET2 0x0350
97#define PESDR1_HSSL3STS 0x0351
98#define PESDR1_HSSCTLSET 0x0352
99#define PESDR1_LANE_ABCD 0x0353
100
101#define PESDR2_UTLSET1 0x0370
102#define PESDR2_UTLSET2 0x0371
103#define PESDR2_DLPSET 0x0372
104#define PESDR2_LOOP 0x0373
105#define PESDR2_RCSSET 0x0374
106#define PESDR2_RCSSTS 0x0375
107#define PESDR2_HSSL0SET1 0x0376
108#define PESDR2_HSSL0SET2 0x0377
109#define PESDR2_HSSL0STS 0x0378
110#define PESDR2_HSSL1SET1 0x0379
111#define PESDR2_HSSL1SET2 0x037a
112#define PESDR2_HSSL1STS 0x037b
113#define PESDR2_HSSL2SET1 0x037c
114#define PESDR2_HSSL2SET2 0x037d
115#define PESDR2_HSSL2STS 0x037e
116#define PESDR2_HSSL3SET1 0x037f
117#define PESDR2_HSSL3SET2 0x0380
118#define PESDR2_HSSL3STS 0x0381
119#define PESDR2_HSSCTLSET 0x0382
120#define PESDR2_LANE_ABCD 0x0383
121
122/*
123 * UTL register offsets
124 */
125#define PEUTL_PBBSZ 0x20
126#define PEUTL_OPDBSZ 0x68
127#define PEUTL_IPHBSZ 0x70
128#define PEUTL_IPDBSZ 0x78
129#define PEUTL_OUTTR 0x90
130#define PEUTL_INTR 0x98
131#define PEUTL_PCTL 0xa0
132#define PEUTL_RCIRQEN 0xb8
133
134/*
135 * Config space register offsets
136 */
137#define PECFG_BAR0LMPA 0x210
138#define PECFG_BAR0HMPA 0x214
139#define PECFG_PIMEN 0x33c
140#define PECFG_PIM0LAL 0x340
141#define PECFG_PIM0LAH 0x344
142#define PECFG_POM0LAL 0x380
143#define PECFG_POM0LAH 0x384
144
145int ppc440spe_init_pcie(void);
146int ppc440spe_init_pcie_rootport(int port);
147void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
148
149#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */
diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 0b435633a0d1..aa4165144ec2 100644
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -38,6 +38,7 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) 38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) 39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) 40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
41#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq)
41 42
42#define UIC_HANDLERS(n) \ 43#define UIC_HANDLERS(n) \
43static void ppc4xx_uic##n##_enable(unsigned int irq) \ 44static void ppc4xx_uic##n##_enable(unsigned int irq) \
@@ -88,7 +89,38 @@ static void ppc4xx_uic##n##_end(unsigned int irq) \
88 .end = ppc4xx_uic##n##_end, \ 89 .end = ppc4xx_uic##n##_end, \
89} \ 90} \
90 91
91#if NR_UICS == 3 92#if NR_UICS == 4
93#define ACK_UIC0_PARENT
94#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
95#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
96#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
97UIC_HANDLERS(0);
98UIC_HANDLERS(1);
99UIC_HANDLERS(2);
100UIC_HANDLERS(3);
101
102static int ppc4xx_pic_get_irq(struct pt_regs *regs)
103{
104 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
105 if (uic0 & UIC0_UIC1NC)
106 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
107 else if (uic0 & UIC0_UIC2NC)
108 return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
109 else if (uic0 & UIC0_UIC3NC)
110 return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3)));
111 else
112 return uic0 ? 32 - ffs(uic0) : -1;
113}
114
115static void __init ppc4xx_pic_impl_init(void)
116{
117 /* Enable cascade interrupts in UIC0 */
118 ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
119 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
120 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
121}
122
123#elif NR_UICS == 3
92#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); 124#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
93#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); 125#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
94#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); 126#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -170,6 +202,9 @@ static struct ppc4xx_uic_impl {
170 { .decl = DECLARE_UIC(1), .base = UIC1 }, 202 { .decl = DECLARE_UIC(1), .base = UIC1 },
171#if NR_UICS > 2 203#if NR_UICS > 2
172 { .decl = DECLARE_UIC(2), .base = UIC2 }, 204 { .decl = DECLARE_UIC(2), .base = UIC2 },
205#if NR_UICS > 3
206 { .decl = DECLARE_UIC(3), .base = UIC3 },
207#endif
173#endif 208#endif
174#endif 209#endif
175}; 210};
diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c
new file mode 100644
index 000000000000..297f3b549177
--- /dev/null
+++ b/arch/ppc/syslib/ppc85xx_rio.c
@@ -0,0 +1,938 @@
1/*
2 * MPC85xx RapidIO support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/dma-mapping.h>
18#include <linux/interrupt.h>
19#include <linux/rio.h>
20#include <linux/rio_drv.h>
21
22#include <asm/io.h>
23
24#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
25#define RIO_ATMU_REGS_OFFSET 0x10c00
26#define RIO_MSG_REGS_OFFSET 0x11000
27#define RIO_MAINT_WIN_SIZE 0x400000
28#define RIO_DBELL_WIN_SIZE 0x1000
29
30#define RIO_MSG_OMR_MUI 0x00000002
31#define RIO_MSG_OSR_TE 0x00000080
32#define RIO_MSG_OSR_QOI 0x00000020
33#define RIO_MSG_OSR_QFI 0x00000010
34#define RIO_MSG_OSR_MUB 0x00000004
35#define RIO_MSG_OSR_EOMI 0x00000002
36#define RIO_MSG_OSR_QEI 0x00000001
37
38#define RIO_MSG_IMR_MI 0x00000002
39#define RIO_MSG_ISR_TE 0x00000080
40#define RIO_MSG_ISR_QFI 0x00000010
41#define RIO_MSG_ISR_DIQI 0x00000001
42
43#define RIO_MSG_DESC_SIZE 32
44#define RIO_MSG_BUFFER_SIZE 4096
45#define RIO_MIN_TX_RING_SIZE 2
46#define RIO_MAX_TX_RING_SIZE 2048
47#define RIO_MIN_RX_RING_SIZE 2
48#define RIO_MAX_RX_RING_SIZE 2048
49
50#define DOORBELL_DMR_DI 0x00000002
51#define DOORBELL_DSR_TE 0x00000080
52#define DOORBELL_DSR_QFI 0x00000010
53#define DOORBELL_DSR_DIQI 0x00000001
54#define DOORBELL_TID_OFFSET 0x03
55#define DOORBELL_SID_OFFSET 0x05
56#define DOORBELL_INFO_OFFSET 0x06
57
58#define DOORBELL_MESSAGE_SIZE 0x08
59#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
60#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
61#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
62
63#define is_power_of_2(x) (((x) & ((x) - 1)) == 0)
64
65struct rio_atmu_regs {
66 u32 rowtar;
67 u32 pad1;
68 u32 rowbar;
69 u32 pad2;
70 u32 rowar;
71 u32 pad3[3];
72};
73
74struct rio_msg_regs {
75 u32 omr;
76 u32 osr;
77 u32 pad1;
78 u32 odqdpar;
79 u32 pad2;
80 u32 osar;
81 u32 odpr;
82 u32 odatr;
83 u32 odcr;
84 u32 pad3;
85 u32 odqepar;
86 u32 pad4[13];
87 u32 imr;
88 u32 isr;
89 u32 pad5;
90 u32 ifqdpar;
91 u32 pad6;
92 u32 ifqepar;
93 u32 pad7[250];
94 u32 dmr;
95 u32 dsr;
96 u32 pad8;
97 u32 dqdpar;
98 u32 pad9;
99 u32 dqepar;
100 u32 pad10[26];
101 u32 pwmr;
102 u32 pwsr;
103 u32 pad11;
104 u32 pwqbar;
105};
106
107struct rio_tx_desc {
108 u32 res1;
109 u32 saddr;
110 u32 dport;
111 u32 dattr;
112 u32 res2;
113 u32 res3;
114 u32 dwcnt;
115 u32 res4;
116};
117
118static u32 regs_win;
119static struct rio_atmu_regs *atmu_regs;
120static struct rio_atmu_regs *maint_atmu_regs;
121static struct rio_atmu_regs *dbell_atmu_regs;
122static u32 dbell_win;
123static u32 maint_win;
124static struct rio_msg_regs *msg_regs;
125
126static struct rio_dbell_ring {
127 void *virt;
128 dma_addr_t phys;
129} dbell_ring;
130
131static struct rio_msg_tx_ring {
132 void *virt;
133 dma_addr_t phys;
134 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
135 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
136 int tx_slot;
137 int size;
138 void *dev_id;
139} msg_tx_ring;
140
141static struct rio_msg_rx_ring {
142 void *virt;
143 dma_addr_t phys;
144 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
145 int rx_slot;
146 int size;
147 void *dev_id;
148} msg_rx_ring;
149
150/**
151 * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
152 * @index: ID of RapidIO interface
153 * @destid: Destination ID of target device
154 * @data: 16-bit info field of RapidIO doorbell message
155 *
156 * Sends a MPC85xx doorbell message. Returns %0 on success or
157 * %-EINVAL on failure.
158 */
159static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
160{
161 pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
162 index, destid, data);
163 out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
164 out_be16((void *)(dbell_win), data);
165
166 return 0;
167}
168
169/**
170 * mpc85xx_local_config_read - Generate a MPC85xx local config space read
171 * @index: ID of RapdiIO interface
172 * @offset: Offset into configuration space
173 * @len: Length (in bytes) of the maintenance transaction
174 * @data: Value to be read into
175 *
176 * Generates a MPC85xx local configuration space read. Returns %0 on
177 * success or %-EINVAL on failure.
178 */
179static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
180{
181 pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
182 offset);
183 *data = in_be32((void *)(regs_win + offset));
184
185 return 0;
186}
187
188/**
189 * mpc85xx_local_config_write - Generate a MPC85xx local config space write
190 * @index: ID of RapdiIO interface
191 * @offset: Offset into configuration space
192 * @len: Length (in bytes) of the maintenance transaction
193 * @data: Value to be written
194 *
195 * Generates a MPC85xx local configuration space write. Returns %0 on
196 * success or %-EINVAL on failure.
197 */
198static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
199{
200 pr_debug
201 ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
202 index, offset, data);
203 out_be32((void *)(regs_win + offset), data);
204
205 return 0;
206}
207
208/**
209 * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
210 * @index: ID of RapdiIO interface
211 * @destid: Destination ID of transaction
212 * @hopcount: Number of hops to target device
213 * @offset: Offset into configuration space
214 * @len: Length (in bytes) of the maintenance transaction
215 * @val: Location to be read into
216 *
217 * Generates a MPC85xx read maintenance transaction. Returns %0 on
218 * success or %-EINVAL on failure.
219 */
220static int
221mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
222 u32 * val)
223{
224 u8 *data;
225
226 pr_debug
227 ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
228 index, destid, hopcount, offset, len);
229 out_be32((void *)&maint_atmu_regs->rowtar,
230 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
231
232 data = (u8 *) maint_win + offset;
233 switch (len) {
234 case 1:
235 *val = in_8((u8 *) data);
236 break;
237 case 2:
238 *val = in_be16((u16 *) data);
239 break;
240 default:
241 *val = in_be32((u32 *) data);
242 break;
243 }
244
245 return 0;
246}
247
248/**
249 * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
250 * @index: ID of RapdiIO interface
251 * @destid: Destination ID of transaction
252 * @hopcount: Number of hops to target device
253 * @offset: Offset into configuration space
254 * @len: Length (in bytes) of the maintenance transaction
255 * @val: Value to be written
256 *
257 * Generates an MPC85xx write maintenance transaction. Returns %0 on
258 * success or %-EINVAL on failure.
259 */
260static int
261mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
262 int len, u32 val)
263{
264 u8 *data;
265 pr_debug
266 ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
267 index, destid, hopcount, offset, len, val);
268 out_be32((void *)&maint_atmu_regs->rowtar,
269 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
270
271 data = (u8 *) maint_win + offset;
272 switch (len) {
273 case 1:
274 out_8((u8 *) data, val);
275 break;
276 case 2:
277 out_be16((u16 *) data, val);
278 break;
279 default:
280 out_be32((u32 *) data, val);
281 break;
282 }
283
284 return 0;
285}
286
287/**
288 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
289 * @mport: Master port with outbound message queue
290 * @rdev: Target of outbound message
291 * @mbox: Outbound mailbox
292 * @buffer: Message to add to outbound queue
293 * @len: Length of message
294 *
295 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
296 * %0 on success or %-EINVAL on failure.
297 */
298int
299rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
300 void *buffer, size_t len)
301{
302 u32 omr;
303 struct rio_tx_desc *desc =
304 (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
305 int ret = 0;
306
307 pr_debug
308 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
309 rdev->destid, mbox, (int)buffer, len);
310
311 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
312 ret = -EINVAL;
313 goto out;
314 }
315
316 /* Copy and clear rest of buffer */
317 memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
318 if (len < (RIO_MAX_MSG_SIZE - 4))
319 memset((void *)((u32) msg_tx_ring.
320 virt_buffer[msg_tx_ring.tx_slot] + len), 0,
321 RIO_MAX_MSG_SIZE - len);
322
323 /* Set mbox field for message */
324 desc->dport = mbox & 0x3;
325
326 /* Enable EOMI interrupt, set priority, and set destid */
327 desc->dattr = 0x28000000 | (rdev->destid << 2);
328
329 /* Set transfer size aligned to next power of 2 (in double words) */
330 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
331
332 /* Set snooping and source buffer address */
333 desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
334
335 /* Increment enqueue pointer */
336 omr = in_be32((void *)&msg_regs->omr);
337 out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
338
339 /* Go to next descriptor */
340 if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
341 msg_tx_ring.tx_slot = 0;
342
343 out:
344 return ret;
345}
346
347EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
348
349/**
350 * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
351 * @irq: Linux interrupt number
352 * @dev_instance: Pointer to interrupt-specific data
353 * @regs: Register context
354 *
355 * Handles outbound message interrupts. Executes a register outbound
356 * mailbox event handler and acks the interrupt occurence.
357 */
358static irqreturn_t
359mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs)
360{
361 int osr;
362 struct rio_mport *port = (struct rio_mport *)dev_instance;
363
364 osr = in_be32((void *)&msg_regs->osr);
365
366 if (osr & RIO_MSG_OSR_TE) {
367 pr_info("RIO: outbound message transmission error\n");
368 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
369 goto out;
370 }
371
372 if (osr & RIO_MSG_OSR_QOI) {
373 pr_info("RIO: outbound message queue overflow\n");
374 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
375 goto out;
376 }
377
378 if (osr & RIO_MSG_OSR_EOMI) {
379 u32 dqp = in_be32((void *)&msg_regs->odqdpar);
380 int slot = (dqp - msg_tx_ring.phys) >> 5;
381 port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
382
383 /* Ack the end-of-message interrupt */
384 out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
385 }
386
387 out:
388 return IRQ_HANDLED;
389}
390
391/**
392 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
393 * @mport: Master port implementing the outbound message unit
394 * @dev_id: Device specific pointer to pass on event
395 * @mbox: Mailbox to open
396 * @entries: Number of entries in the outbound mailbox ring
397 *
398 * Initializes buffer ring, request the outbound message interrupt,
399 * and enables the outbound message unit. Returns %0 on success and
400 * %-EINVAL or %-ENOMEM on failure.
401 */
402int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
403{
404 int i, j, rc = 0;
405
406 if ((entries < RIO_MIN_TX_RING_SIZE) ||
407 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
408 rc = -EINVAL;
409 goto out;
410 }
411
412 /* Initialize shadow copy ring */
413 msg_tx_ring.dev_id = dev_id;
414 msg_tx_ring.size = entries;
415
416 for (i = 0; i < msg_tx_ring.size; i++) {
417 if (!
418 (msg_tx_ring.virt_buffer[i] =
419 dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
420 &msg_tx_ring.phys_buffer[i],
421 GFP_KERNEL))) {
422 rc = -ENOMEM;
423 for (j = 0; j < msg_tx_ring.size; j++)
424 if (msg_tx_ring.virt_buffer[j])
425 dma_free_coherent(NULL,
426 RIO_MSG_BUFFER_SIZE,
427 msg_tx_ring.
428 virt_buffer[j],
429 msg_tx_ring.
430 phys_buffer[j]);
431 goto out;
432 }
433 }
434
435 /* Initialize outbound message descriptor ring */
436 if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
437 msg_tx_ring.size *
438 RIO_MSG_DESC_SIZE,
439 &msg_tx_ring.phys,
440 GFP_KERNEL))) {
441 rc = -ENOMEM;
442 goto out_dma;
443 }
444 memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
445 msg_tx_ring.tx_slot = 0;
446
447 /* Point dequeue/enqueue pointers at first entry in ring */
448 out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
449 out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
450
451 /* Configure for snooping */
452 out_be32((void *)&msg_regs->osar, 0x00000004);
453
454 /* Clear interrupt status */
455 out_be32((void *)&msg_regs->osr, 0x000000b3);
456
457 /* Hook up outbound message handler */
458 if ((rc =
459 request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
460 "msg_tx", (void *)mport)) < 0)
461 goto out_irq;
462
463 /*
464 * Configure outbound message unit
465 * Snooping
466 * Interrupts (all enabled, except QEIE)
467 * Chaining mode
468 * Disable
469 */
470 out_be32((void *)&msg_regs->omr, 0x00100220);
471
472 /* Set number of entries */
473 out_be32((void *)&msg_regs->omr,
474 in_be32((void *)&msg_regs->omr) |
475 ((get_bitmask_order(entries) - 2) << 12));
476
477 /* Now enable the unit */
478 out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
479
480 out:
481 return rc;
482
483 out_irq:
484 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
485 msg_tx_ring.virt, msg_tx_ring.phys);
486
487 out_dma:
488 for (i = 0; i < msg_tx_ring.size; i++)
489 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
490 msg_tx_ring.virt_buffer[i],
491 msg_tx_ring.phys_buffer[i]);
492
493 return rc;
494}
495
496/**
497 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
498 * @mport: Master port implementing the outbound message unit
499 * @mbox: Mailbox to close
500 *
501 * Disables the outbound message unit, free all buffers, and
502 * frees the outbound message interrupt.
503 */
504void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
505{
506 /* Disable inbound message unit */
507 out_be32((void *)&msg_regs->omr, 0);
508
509 /* Free ring */
510 dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
511 msg_tx_ring.virt, msg_tx_ring.phys);
512
513 /* Free interrupt */
514 free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
515}
516
517/**
518 * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
519 * @irq: Linux interrupt number
520 * @dev_instance: Pointer to interrupt-specific data
521 * @regs: Register context
522 *
523 * Handles inbound message interrupts. Executes a registered inbound
524 * mailbox event handler and acks the interrupt occurence.
525 */
526static irqreturn_t
527mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs)
528{
529 int isr;
530 struct rio_mport *port = (struct rio_mport *)dev_instance;
531
532 isr = in_be32((void *)&msg_regs->isr);
533
534 if (isr & RIO_MSG_ISR_TE) {
535 pr_info("RIO: inbound message reception error\n");
536 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
537 goto out;
538 }
539
540 /* XXX Need to check/dispatch until queue empty */
541 if (isr & RIO_MSG_ISR_DIQI) {
542 /*
543 * We implement *only* mailbox 0, but can receive messages
544 * for any mailbox/letter to that mailbox destination. So,
545 * make the callback with an unknown/invalid mailbox number
546 * argument.
547 */
548 port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
549
550 /* Ack the queueing interrupt */
551 out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
552 }
553
554 out:
555 return IRQ_HANDLED;
556}
557
558/**
559 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
560 * @mport: Master port implementing the inbound message unit
561 * @dev_id: Device specific pointer to pass on event
562 * @mbox: Mailbox to open
563 * @entries: Number of entries in the inbound mailbox ring
564 *
565 * Initializes buffer ring, request the inbound message interrupt,
566 * and enables the inbound message unit. Returns %0 on success
567 * and %-EINVAL or %-ENOMEM on failure.
568 */
569int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
570{
571 int i, rc = 0;
572
573 if ((entries < RIO_MIN_RX_RING_SIZE) ||
574 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
575 rc = -EINVAL;
576 goto out;
577 }
578
579 /* Initialize client buffer ring */
580 msg_rx_ring.dev_id = dev_id;
581 msg_rx_ring.size = entries;
582 msg_rx_ring.rx_slot = 0;
583 for (i = 0; i < msg_rx_ring.size; i++)
584 msg_rx_ring.virt_buffer[i] = NULL;
585
586 /* Initialize inbound message ring */
587 if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
588 msg_rx_ring.size *
589 RIO_MAX_MSG_SIZE,
590 &msg_rx_ring.phys,
591 GFP_KERNEL))) {
592 rc = -ENOMEM;
593 goto out;
594 }
595
596 /* Point dequeue/enqueue pointers at first entry in ring */
597 out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
598 out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
599
600 /* Clear interrupt status */
601 out_be32((void *)&msg_regs->isr, 0x00000091);
602
603 /* Hook up inbound message handler */
604 if ((rc =
605 request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
606 "msg_rx", (void *)mport)) < 0) {
607 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
608 msg_tx_ring.virt_buffer[i],
609 msg_tx_ring.phys_buffer[i]);
610 goto out;
611 }
612
613 /*
614 * Configure inbound message unit:
615 * Snooping
616 * 4KB max message size
617 * Unmask all interrupt sources
618 * Disable
619 */
620 out_be32((void *)&msg_regs->imr, 0x001b0060);
621
622 /* Set number of queue entries */
623 out_be32((void *)&msg_regs->imr,
624 in_be32((void *)&msg_regs->imr) |
625 ((get_bitmask_order(entries) - 2) << 12));
626
627 /* Now enable the unit */
628 out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
629
630 out:
631 return rc;
632}
633
634/**
635 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
636 * @mport: Master port implementing the inbound message unit
637 * @mbox: Mailbox to close
638 *
639 * Disables the inbound message unit, free all buffers, and
640 * frees the inbound message interrupt.
641 */
642void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
643{
644 /* Disable inbound message unit */
645 out_be32((void *)&msg_regs->imr, 0);
646
647 /* Free ring */
648 dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
649 msg_rx_ring.virt, msg_rx_ring.phys);
650
651 /* Free interrupt */
652 free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
653}
654
655/**
656 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
657 * @mport: Master port implementing the inbound message unit
658 * @mbox: Inbound mailbox number
659 * @buf: Buffer to add to inbound queue
660 *
661 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
662 * %0 on success or %-EINVAL on failure.
663 */
664int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
665{
666 int rc = 0;
667
668 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
669 msg_rx_ring.rx_slot);
670
671 if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
672 printk(KERN_ERR
673 "RIO: error adding inbound buffer %d, buffer exists\n",
674 msg_rx_ring.rx_slot);
675 rc = -EINVAL;
676 goto out;
677 }
678
679 msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
680 if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
681 msg_rx_ring.rx_slot = 0;
682
683 out:
684 return rc;
685}
686
687EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
688
689/**
690 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
691 * @mport: Master port implementing the inbound message unit
692 * @mbox: Inbound mailbox number
693 *
694 * Gets the next available inbound message from the inbound message queue.
695 * A pointer to the message is returned on success or NULL on failure.
696 */
697void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
698{
699 u32 imr;
700 u32 phys_buf, virt_buf;
701 void *buf = NULL;
702 int buf_idx;
703
704 phys_buf = in_be32((void *)&msg_regs->ifqdpar);
705
706 /* If no more messages, then bail out */
707 if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
708 goto out2;
709
710 virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
711 buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
712 buf = msg_rx_ring.virt_buffer[buf_idx];
713
714 if (!buf) {
715 printk(KERN_ERR
716 "RIO: inbound message copy failed, no buffers\n");
717 goto out1;
718 }
719
720 /* Copy max message size, caller is expected to allocate that big */
721 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
722
723 /* Clear the available buffer */
724 msg_rx_ring.virt_buffer[buf_idx] = NULL;
725
726 out1:
727 imr = in_be32((void *)&msg_regs->imr);
728 out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
729
730 out2:
731 return buf;
732}
733
734EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
735
736/**
737 * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
738 * @irq: Linux interrupt number
739 * @dev_instance: Pointer to interrupt-specific data
740 * @regs: Register context
741 *
742 * Handles doorbell interrupts. Parses a list of registered
743 * doorbell event handlers and executes a matching event handler.
744 */
745static irqreturn_t
746mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs)
747{
748 int dsr;
749 struct rio_mport *port = (struct rio_mport *)dev_instance;
750
751 dsr = in_be32((void *)&msg_regs->dsr);
752
753 if (dsr & DOORBELL_DSR_TE) {
754 pr_info("RIO: doorbell reception error\n");
755 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
756 goto out;
757 }
758
759 if (dsr & DOORBELL_DSR_QFI) {
760 pr_info("RIO: doorbell queue full\n");
761 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
762 goto out;
763 }
764
765 /* XXX Need to check/dispatch until queue empty */
766 if (dsr & DOORBELL_DSR_DIQI) {
767 u32 dmsg =
768 (u32) dbell_ring.virt +
769 (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
770 u32 dmr;
771 struct rio_dbell *dbell;
772 int found = 0;
773
774 pr_debug
775 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
776 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
777
778 list_for_each_entry(dbell, &port->dbells, node) {
779 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
780 (dbell->res->end >= DBELL_INF(dmsg))) {
781 found = 1;
782 break;
783 }
784 }
785 if (found) {
786 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
787 DBELL_INF(dmsg));
788 } else {
789 pr_debug
790 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
791 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
792 }
793 dmr = in_be32((void *)&msg_regs->dmr);
794 out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
795 out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
796 }
797
798 out:
799 return IRQ_HANDLED;
800}
801
802/**
803 * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
804 * @mport: Master port implementing the inbound doorbell unit
805 *
806 * Initializes doorbell unit hardware and inbound DMA buffer
807 * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
808 * or %-ENOMEM on failure.
809 */
810static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
811{
812 int rc = 0;
813
814 /* Map outbound doorbell window immediately after maintenance window */
815 if (!(dbell_win =
816 (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
817 RIO_DBELL_WIN_SIZE))) {
818 printk(KERN_ERR
819 "RIO: unable to map outbound doorbell window\n");
820 rc = -ENOMEM;
821 goto out;
822 }
823
824 /* Initialize inbound doorbells */
825 if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
826 512 * DOORBELL_MESSAGE_SIZE,
827 &dbell_ring.phys,
828 GFP_KERNEL))) {
829 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
830 rc = -ENOMEM;
831 iounmap((void *)dbell_win);
832 goto out;
833 }
834
835 /* Point dequeue/enqueue pointers at first entry in ring */
836 out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
837 out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
838
839 /* Clear interrupt status */
840 out_be32((void *)&msg_regs->dsr, 0x00000091);
841
842 /* Hook up doorbell handler */
843 if ((rc =
844 request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
845 "dbell_rx", (void *)mport) < 0)) {
846 iounmap((void *)dbell_win);
847 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
848 dbell_ring.virt, dbell_ring.phys);
849 printk(KERN_ERR
850 "MPC85xx RIO: unable to request inbound doorbell irq");
851 goto out;
852 }
853
854 /* Configure doorbells for snooping, 512 entries, and enable */
855 out_be32((void *)&msg_regs->dmr, 0x00108161);
856
857 out:
858 return rc;
859}
860
861static char *cmdline = NULL;
862
863static int mpc85xx_rio_get_hdid(int index)
864{
865 /* XXX Need to parse multiple entries in some format */
866 if (!cmdline)
867 return -1;
868
869 return simple_strtol(cmdline, NULL, 0);
870}
871
872static int mpc85xx_rio_get_cmdline(char *s)
873{
874 if (!s)
875 return 0;
876
877 cmdline = s;
878 return 1;
879}
880
881__setup("riohdid=", mpc85xx_rio_get_cmdline);
882
883/**
884 * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
885 * @law_start: Starting physical address of RapidIO LAW
886 * @law_size: Size of RapidIO LAW
887 *
888 * Initializes MPC85xx RapidIO hardware interface, configures
889 * master port with system-specific info, and registers the
890 * master port with the RapidIO subsystem.
891 */
892void mpc85xx_rio_setup(int law_start, int law_size)
893{
894 struct rio_ops *ops;
895 struct rio_mport *port;
896
897 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
898 ops->lcread = mpc85xx_local_config_read;
899 ops->lcwrite = mpc85xx_local_config_write;
900 ops->cread = mpc85xx_rio_config_read;
901 ops->cwrite = mpc85xx_rio_config_write;
902 ops->dsend = mpc85xx_rio_doorbell_send;
903
904 port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
905 port->id = 0;
906 port->index = 0;
907 INIT_LIST_HEAD(&port->dbells);
908 port->iores.start = law_start;
909 port->iores.end = law_start + law_size;
910 port->iores.flags = IORESOURCE_MEM;
911
912 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
913 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
914 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
915 strcpy(port->name, "RIO0 mport");
916
917 port->ops = ops;
918 port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
919
920 rio_register_mport(port);
921
922 regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
923 atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
924 maint_atmu_regs = atmu_regs + 1;
925 dbell_atmu_regs = atmu_regs + 2;
926 msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
927
928 /* Configure maintenance transaction window */
929 out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
930 out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
931
932 maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
933
934 /* Configure outbound doorbell window */
935 out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
936 out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
937 mpc85xx_rio_doorbell_init(port);
938}
diff --git a/arch/ppc/syslib/ppc85xx_rio.h b/arch/ppc/syslib/ppc85xx_rio.h
new file mode 100644
index 000000000000..c0827a2c3eec
--- /dev/null
+++ b/arch/ppc/syslib/ppc85xx_rio.h
@@ -0,0 +1,21 @@
1/*
2 * MPC85xx RapidIO definitions
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __PPC_SYSLIB_PPC85XX_RIO_H
14#define __PPC_SYSLIB_PPC85XX_RIO_H
15
16#include <linux/config.h>
17#include <linux/init.h>
18
19extern void mpc85xx_rio_setup(int law_start, int law_size);
20
21#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index 62ee86e80711..603f01190816 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -14,6 +14,7 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17#include <linux/string.h>
17#include <asm/ppc_sys.h> 18#include <asm/ppc_sys.h>
18 19
19int (*ppc_sys_device_fixup) (struct platform_device * pdev); 20int (*ppc_sys_device_fixup) (struct platform_device * pdev);
diff --git a/arch/ppc/syslib/prom.c b/arch/ppc/syslib/prom.c
index 278da6ee62ea..1b9aa0d6a924 100644
--- a/arch/ppc/syslib/prom.c
+++ b/arch/ppc/syslib/prom.c
@@ -1335,10 +1335,8 @@ release_OF_resource(struct device_node* node, int index)
1335 if (!res) 1335 if (!res)
1336 return -ENODEV; 1336 return -ENODEV;
1337 1337
1338 if (res->name) { 1338 kfree(res->name);
1339 kfree(res->name); 1339 res->name = NULL;
1340 res->name = NULL;
1341 }
1342 release_resource(res); 1340 release_resource(res);
1343 kfree(res); 1341 kfree(res);
1344 1342
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 07:51:27 -0500