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-rw-r--r--arch/ppc/platforms/4xx/Kconfig20
-rw-r--r--arch/ppc/platforms/4xx/Makefile2
-rw-r--r--arch/ppc/platforms/4xx/bamboo.c427
-rw-r--r--arch/ppc/platforms/4xx/bamboo.h136
-rw-r--r--arch/ppc/platforms/4xx/ebony.c6
-rw-r--r--arch/ppc/platforms/4xx/ebony.h13
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c220
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.h76
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c4
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c4
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h13
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.c48
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c42
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c29
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c3
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c28
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c29
-rw-r--r--arch/ppc/platforms/chrp_pci.c1
-rw-r--r--arch/ppc/platforms/fads.h109
-rw-r--r--arch/ppc/platforms/katana.c2
-rw-r--r--arch/ppc/platforms/mpc885ads.h92
-rw-r--r--arch/ppc/platforms/pmac_cpufreq.c2
-rw-r--r--arch/ppc/platforms/pmac_pci.c1
-rw-r--r--arch/ppc/platforms/pmac_setup.c16
-rw-r--r--arch/ppc/platforms/pmac_sleep.S4
-rw-r--r--arch/ppc/platforms/pmac_time.c8
-rw-r--r--arch/ppc/platforms/prpmc750.c1
-rw-r--r--arch/ppc/platforms/sandpoint.c18
-rw-r--r--arch/ppc/platforms/tqm8260_setup.c2
29 files changed, 1246 insertions, 110 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index a0612a86455a..f7c045764e04 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -68,6 +68,11 @@ choice
68 depends on 44x 68 depends on 44x
69 default EBONY 69 default EBONY
70 70
71config BAMBOO
72 bool "Bamboo"
73 help
74 This option enables support for the IBM PPC440EP evaluation board.
75
71config EBONY 76config EBONY
72 bool "Ebony" 77 bool "Ebony"
73 help 78 help
@@ -98,6 +103,12 @@ config NP405H
98 depends on ASH 103 depends on ASH
99 default y 104 default y
100 105
106config 440EP
107 bool
108 depends on BAMBOO
109 select PPC_FPU
110 default y
111
101config 440GP 112config 440GP
102 bool 113 bool
103 depends on EBONY 114 depends on EBONY
@@ -115,7 +126,7 @@ config 440SP
115 126
116config 440 127config 440
117 bool 128 bool
118 depends on 440GP || 440SP 129 depends on 440GP || 440SP || 440EP
119 default y 130 default y
120 131
121config 440A 132config 440A
@@ -123,6 +134,11 @@ config 440A
123 depends on 440GX 134 depends on 440GX
124 default y 135 default y
125 136
137config IBM440EP_ERR42
138 bool
139 depends on 440EP
140 default y
141
126# All 405-based cores up until the 405GPR and 405EP have this errata. 142# All 405-based cores up until the 405GPR and 405EP have this errata.
127config IBM405_ERR77 143config IBM405_ERR77
128 bool 144 bool
@@ -142,7 +158,7 @@ config BOOKE
142 158
143config IBM_OCP 159config IBM_OCP
144 bool 160 bool
145 depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 161 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
146 default y 162 default y
147 163
148config XILINX_OCP 164config XILINX_OCP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index ea470c6adbb6..844c3b5066e8 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -2,6 +2,7 @@
2# Makefile for the PowerPC 4xx linux kernel. 2# Makefile for the PowerPC 4xx linux kernel.
3 3
4obj-$(CONFIG_ASH) += ash.o 4obj-$(CONFIG_ASH) += ash.o
5obj-$(CONFIG_BAMBOO) += bamboo.o
5obj-$(CONFIG_CPCI405) += cpci405.o 6obj-$(CONFIG_CPCI405) += cpci405.o
6obj-$(CONFIG_EBONY) += ebony.o 7obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o 8obj-$(CONFIG_EP405) += ep405.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_405GP) += ibm405gp.o
19obj-$(CONFIG_REDWOOD_5) += ibmstb4.o 20obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
20obj-$(CONFIG_NP405H) += ibmnp405h.o 21obj-$(CONFIG_NP405H) += ibmnp405h.o
21obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o 22obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
23obj-$(CONFIG_440EP) += ibm440ep.o
22obj-$(CONFIG_440GP) += ibm440gp.o 24obj-$(CONFIG_440GP) += ibm440gp.o
23obj-$(CONFIG_440GX) += ibm440gx.o 25obj-$(CONFIG_440GX) += ibm440gx.o
24obj-$(CONFIG_440SP) += ibm440sp.o 26obj-$(CONFIG_440SP) += ibm440sp.o
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
new file mode 100644
index 000000000000..f116787b0b76
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bamboo.c
@@ -0,0 +1,427 @@
1/*
2 * arch/ppc/platforms/4xx/bamboo.c
3 *
4 * Bamboo board specific routines
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright 2004 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/config.h>
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/types.h>
24#include <linux/major.h>
25#include <linux/blkdev.h>
26#include <linux/console.h>
27#include <linux/delay.h>
28#include <linux/ide.h>
29#include <linux/initrd.h>
30#include <linux/irq.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/tty.h>
34#include <linux/serial.h>
35#include <linux/serial_core.h>
36#include <linux/ethtool.h>
37
38#include <asm/system.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
41#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/ocp.h>
45#include <asm/pci-bridge.h>
46#include <asm/time.h>
47#include <asm/todc.h>
48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h>
51
52#include <syslib/gen550.h>
53#include <syslib/ibm440gx_common.h>
54
55/*
56 * This is a horrible kludge, we eventually need to abstract this
57 * generic PHY stuff, so the standard phy mode defines can be
58 * easily used from arch code.
59 */
60#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
61
62bd_t __res;
63
64static struct ibm44x_clocks clocks __initdata;
65
66/*
67 * Bamboo external IRQ triggering/polarity settings
68 */
69unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
76 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
80};
81
82static void __init
83bamboo_calibrate_decr(void)
84{
85 unsigned int freq;
86
87 if (mfspr(SPRN_CCR1) & CCR1_TCS)
88 freq = BAMBOO_TMRCLK;
89 else
90 freq = clocks.cpu;
91
92 ibm44x_calibrate_decr(freq);
93
94}
95
96static int
97bamboo_show_cpuinfo(struct seq_file *m)
98{
99 seq_printf(m, "vendor\t\t: IBM\n");
100 seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
101
102 return 0;
103}
104
105static inline int
106bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
107{
108 static char pci_irq_table[][4] =
109 /*
110 * PCI IDSEL/INTPIN->INTLINE
111 * A B C D
112 */
113 {
114 { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
115 { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
116 { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
117 { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
118 };
119
120 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
121 return PCI_IRQ_TABLE_LOOKUP;
122}
123
124static void __init bamboo_set_emacdata(void)
125{
126 unsigned char * selection1_base;
127 struct ocp_def *def;
128 struct ocp_func_emac_data *emacdata;
129 u8 selection1_val;
130 int mode;
131
132 selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
133 selection1_val = readb(selection1_base);
134 iounmap((void *) selection1_base);
135 if (BAMBOO_SEL_MII(selection1_val))
136 mode = PHY_MODE_MII;
137 else if (BAMBOO_SEL_RMII(selection1_val))
138 mode = PHY_MODE_RMII;
139 else
140 mode = PHY_MODE_SMII;
141
142 /* Set mac_addr and phy mode for each EMAC */
143
144 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
145 emacdata = def->additions;
146 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
147 emacdata->phy_mode = mode;
148
149 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
150 emacdata = def->additions;
151 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
152 emacdata->phy_mode = mode;
153}
154
155static int
156bamboo_exclude_device(unsigned char bus, unsigned char devfn)
157{
158 return (bus == 0 && devfn == 0);
159}
160
161#define PCI_READW(offset) \
162 (readw((void *)((u32)pci_reg_base+offset)))
163
164#define PCI_WRITEW(value, offset) \
165 (writew(value, (void *)((u32)pci_reg_base+offset)))
166
167#define PCI_WRITEL(value, offset) \
168 (writel(value, (void *)((u32)pci_reg_base+offset)))
169
170static void __init
171bamboo_setup_pci(void)
172{
173 void *pci_reg_base;
174 unsigned long memory_size;
175 memory_size = ppc_md.find_end_of_memory();
176
177 pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
178
179 /* Enable PCI I/O, Mem, and Busmaster cycles */
180 PCI_WRITEW(PCI_READW(PCI_COMMAND) |
181 PCI_COMMAND_MEMORY |
182 PCI_COMMAND_MASTER, PCI_COMMAND);
183
184 /* Disable region first */
185 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
186
187 /* PLB starting addr: 0x00000000A0000000 */
188 PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
189
190 /* PCI start addr, 0xA0000000 (PCI Address) */
191 PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
192 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
193
194 /* Enable no pre-fetch, enable region */
195 PCI_WRITEL(((0xffffffff -
196 (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
197 BAMBOO_PCIL0_PMM0MA);
198
199 /* Disable region one */
200 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
201 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
202 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
203 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
204 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
205
206 /* Disable region two */
207 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
208 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
209 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
210 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
211 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
212
213 /* Now configure the PCI->PLB windows, we only use PTM1
214 *
215 * For Inbound flow, set the window size to all available memory
216 * This is required because if size is smaller,
217 * then Eth/PCI DD would fail as PCI card not able to access
218 * the memory allocated by DD.
219 */
220
221 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
222 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
223
224 memory_size = 1 << fls(memory_size - 1);
225
226 /* Size low + Enabled */
227 PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
228
229 eieio();
230 iounmap(pci_reg_base);
231}
232
233static void __init
234bamboo_setup_hose(void)
235{
236 unsigned int bar_response, bar;
237 struct pci_controller *hose;
238
239 bamboo_setup_pci();
240
241 hose = pcibios_alloc_controller();
242
243 if (!hose)
244 return;
245
246 hose->first_busno = 0;
247 hose->last_busno = 0xff;
248
249 hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
250
251 pci_init_resource(&hose->io_resource,
252 BAMBOO_PCI_LOWER_IO,
253 BAMBOO_PCI_UPPER_IO,
254 IORESOURCE_IO,
255 "PCI host bridge");
256
257 pci_init_resource(&hose->mem_resources[0],
258 BAMBOO_PCI_LOWER_MEM,
259 BAMBOO_PCI_UPPER_MEM,
260 IORESOURCE_MEM,
261 "PCI host bridge");
262
263 ppc_md.pci_exclude_device = bamboo_exclude_device;
264
265 hose->io_space.start = BAMBOO_PCI_LOWER_IO;
266 hose->io_space.end = BAMBOO_PCI_UPPER_IO;
267 hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
268 hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
269 isa_io_base =
270 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
271 hose->io_base_virt = (void *)isa_io_base;
272
273 setup_indirect_pci(hose,
274 BAMBOO_PCI_CFGA_PLB32,
275 BAMBOO_PCI_CFGD_PLB32);
276 hose->set_cfg_type = 1;
277
278 /* Zero config bars */
279 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
280 early_write_config_dword(hose, hose->first_busno,
281 PCI_FUNC(hose->first_busno), bar,
282 0x00000000);
283 early_read_config_dword(hose, hose->first_busno,
284 PCI_FUNC(hose->first_busno), bar,
285 &bar_response);
286 }
287
288 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
289
290 ppc_md.pci_swizzle = common_swizzle;
291 ppc_md.pci_map_irq = bamboo_map_irq;
292}
293
294TODC_ALLOC();
295
296static void __init
297bamboo_early_serial_map(void)
298{
299 struct uart_port port;
300
301 /* Setup ioremapped serial port access */
302 memset(&port, 0, sizeof(port));
303 port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
304 port.irq = 0;
305 port.uartclk = clocks.uart0;
306 port.regshift = 0;
307 port.iotype = SERIAL_IO_MEM;
308 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
309 port.line = 0;
310
311 if (early_serial_setup(&port) != 0) {
312 printk("Early serial init of port 0 failed\n");
313 }
314
315#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
316 /* Configure debug serial access */
317 gen550_init(0, &port);
318#endif
319
320 port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
321 port.irq = 1;
322 port.uartclk = clocks.uart1;
323 port.line = 1;
324
325 if (early_serial_setup(&port) != 0) {
326 printk("Early serial init of port 1 failed\n");
327 }
328
329#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
330 /* Configure debug serial access */
331 gen550_init(1, &port);
332#endif
333
334 port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
335 port.irq = 3;
336 port.uartclk = clocks.uart2;
337 port.line = 2;
338
339 if (early_serial_setup(&port) != 0) {
340 printk("Early serial init of port 2 failed\n");
341 }
342
343#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
344 /* Configure debug serial access */
345 gen550_init(2, &port);
346#endif
347
348 port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
349 port.irq = 4;
350 port.uartclk = clocks.uart3;
351 port.line = 3;
352
353 if (early_serial_setup(&port) != 0) {
354 printk("Early serial init of port 3 failed\n");
355 }
356}
357
358static void __init
359bamboo_setup_arch(void)
360{
361
362 bamboo_set_emacdata();
363
364 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
365 ocp_sys_info.opb_bus_freq = clocks.opb;
366
367 /* Setup TODC access */
368 TODC_INIT(TODC_TYPE_DS1743,
369 0,
370 0,
371 ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
372 8);
373
374 /* init to some ~sane value until calibrate_delay() runs */
375 loops_per_jiffy = 50000000/HZ;
376
377 /* Setup PCI host bridge */
378 bamboo_setup_hose();
379
380#ifdef CONFIG_BLK_DEV_INITRD
381 if (initrd_start)
382 ROOT_DEV = Root_RAM0;
383 else
384#endif
385#ifdef CONFIG_ROOT_NFS
386 ROOT_DEV = Root_NFS;
387#else
388 ROOT_DEV = Root_HDA1;
389#endif
390
391 bamboo_early_serial_map();
392
393 /* Identify the system */
394 printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
395}
396
397void __init platform_init(unsigned long r3, unsigned long r4,
398 unsigned long r5, unsigned long r6, unsigned long r7)
399{
400 parse_bootinfo(find_bootinfo());
401
402 /*
403 * If we were passed in a board information, copy it into the
404 * residual data area.
405 */
406 if (r3)
407 __res = *(bd_t *)(r3 + KERNELBASE);
408
409
410 ibm44x_platform_init();
411
412 ppc_md.setup_arch = bamboo_setup_arch;
413 ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
414 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
415
416 ppc_md.calibrate_decr = bamboo_calibrate_decr;
417 ppc_md.time_init = todc_time_init;
418 ppc_md.set_rtc_time = todc_set_rtc_time;
419 ppc_md.get_rtc_time = todc_get_rtc_time;
420
421 ppc_md.nvram_read_val = todc_direct_read_val;
422 ppc_md.nvram_write_val = todc_direct_write_val;
423#ifdef CONFIG_KGDB
424 ppc_md.early_serial_map = bamboo_early_serial_map;
425#endif
426}
427
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
new file mode 100644
index 000000000000..63d714504148
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bamboo.h
@@ -0,0 +1,136 @@
1/*
2 * arch/ppc/platforms/bamboo.h
3 *
4 * Bamboo board definitions
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 *
8 * Copyright 2004 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_BAMBOO_H__
18#define __ASM_BAMBOO_H__
19
20#include <linux/config.h>
21#include <platforms/4xx/ibm440ep.h>
22
23/* F/W TLB mapping used in bootloader glue to reset EMAC */
24#define PPC44x_EMAC0_MR0 0x0EF600E00
25
26/* Location of MAC addresses in PIBS image */
27#define PIBS_FLASH_BASE 0xfff00000
28#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
29#define PIBS_MAC_SIZE 0x200
30#define PIBS_MAC_OFFSET 0x100
31
32/* Default clock rate */
33#define BAMBOO_TMRCLK 25000000
34
35/* RTC/NVRAM location */
36#define BAMBOO_RTC_ADDR 0x080000000ULL
37#define BAMBOO_RTC_SIZE 0x2000
38
39/* FPGA Registers */
40#define BAMBOO_FPGA_ADDR 0x080002000ULL
41
42#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
43#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
44#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
45#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
46
47#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
48#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
49#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
50#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
51
52#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
53#define BAMBOO_SEL_MII(x) (x & 0x80)
54#define BAMBOO_SEL_RMII(x) (x & 0x40)
55#define BAMBOO_SEL_SMII(x) (x & 0x20)
56
57/* Flash */
58#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
59#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
60#define BAMBOO_SMALL_FLASH_SIZE 0x100000
61#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
62#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
63#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
64#define BAMBOO_LARGE_FLASH_SIZE 0x400000
65#define BAMBOO_SRAM_LOW 0x087f00000ULL
66#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
67#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
68#define BAMBOO_SRAM_SIZE 0x100000
69#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
70#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
71
72/*
73 * Serial port defines
74 */
75#define RS_TABLE_SIZE 4
76
77#define UART0_IO_BASE 0xEF600300
78#define UART1_IO_BASE 0xEF600400
79#define UART2_IO_BASE 0xEF600500
80#define UART3_IO_BASE 0xEF600600
81
82#define BASE_BAUD 33177600/3/16
83#define UART0_INT 0
84#define UART1_INT 1
85#define UART2_INT 3
86#define UART3_INT 4
87
88#define STD_UART_OP(num) \
89 { 0, BASE_BAUD, 0, UART##num##_INT, \
90 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
91 iomem_base: UART##num##_IO_BASE, \
92 io_type: SERIAL_IO_MEM},
93
94#define SERIAL_PORT_DFNS \
95 STD_UART_OP(0) \
96 STD_UART_OP(1) \
97 STD_UART_OP(2) \
98 STD_UART_OP(3)
99
100/* PCI support */
101#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
102#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
103
104#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
105#define BAMBOO_PCI_IO_SIZE 0x00010000
106#define BAMBOO_PCI_MEM_OFFSET 0x00000000
107#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
108
109#define BAMBOO_PCI_LOWER_IO 0x00000000
110#define BAMBOO_PCI_UPPER_IO 0x0000ffff
111#define BAMBOO_PCI_LOWER_MEM 0xa0000000
112#define BAMBOO_PCI_UPPER_MEM 0xafffffff
113#define BAMBOO_PCI_MEM_BASE 0xa0000000
114
115#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
116#define BAMBOO_PCIL0_SIZE 0x40
117
118#define BAMBOO_PCIL0_PMM0LA 0x000
119#define BAMBOO_PCIL0_PMM0MA 0x004
120#define BAMBOO_PCIL0_PMM0PCILA 0x008
121#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
122#define BAMBOO_PCIL0_PMM1LA 0x010
123#define BAMBOO_PCIL0_PMM1MA 0x014
124#define BAMBOO_PCIL0_PMM1PCILA 0x018
125#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
126#define BAMBOO_PCIL0_PMM2LA 0x020
127#define BAMBOO_PCIL0_PMM2MA 0x024
128#define BAMBOO_PCIL0_PMM2PCILA 0x028
129#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
130#define BAMBOO_PCIL0_PTM1MS 0x030
131#define BAMBOO_PCIL0_PTM1LA 0x034
132#define BAMBOO_PCIL0_PTM2MS 0x038
133#define BAMBOO_PCIL0_PTM2LA 0x03C
134
135#endif /* __ASM_BAMBOO_H__ */
136#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index cd11734ef7c5..509e69a095f0 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -7,7 +7,7 @@
7 * Copyright 2002-2005 MontaVista Software Inc. 7 * Copyright 2002-2005 MontaVista Software Inc.
8 * 8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies 10 * Copyright (c) 2003-2005 Zultys Technologies
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -50,6 +50,7 @@
50#include <asm/bootinfo.h> 50#include <asm/bootinfo.h>
51#include <asm/ppc4xx_pic.h> 51#include <asm/ppc4xx_pic.h>
52#include <asm/ppcboot.h> 52#include <asm/ppcboot.h>
53#include <asm/tlbflush.h>
53 54
54#include <syslib/gen550.h> 55#include <syslib/gen550.h>
55#include <syslib/ibm440gp_common.h> 56#include <syslib/ibm440gp_common.h>
@@ -248,6 +249,9 @@ ebony_early_serial_map(void)
248#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 249#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
249 /* Configure debug serial access */ 250 /* Configure debug serial access */
250 gen550_init(0, &port); 251 gen550_init(0, &port);
252
253 /* Purge TLB entry added in head_44x.S for early serial access */
254 _tlbie(UART0_IO_BASE);
251#endif 255#endif
252 256
253 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); 257 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index 47c391c9174d..d08faa46a0ae 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -56,9 +56,18 @@
56 * Serial port defines 56 * Serial port defines
57 */ 57 */
58 58
59/* OpenBIOS defined UART mappings, used before early_serial_setup */ 59#if defined(__BOOTER__)
60/* OpenBIOS defined UART mappings, used by bootloader shim */
60#define UART0_IO_BASE 0xE0000200 61#define UART0_IO_BASE 0xE0000200
61#define UART1_IO_BASE 0xE0000300 62#define UART1_IO_BASE 0xE0000300
63#else
64/* head_44x.S created UART mapping, used before early_serial_setup.
65 * We cannot use default OpenBIOS UART mappings because they
66 * don't work for configurations with more than 512M RAM. --ebs
67 */
68#define UART0_IO_BASE 0xF0000200
69#define UART1_IO_BASE 0xF0000300
70#endif
62 71
63/* external Epson SG-615P */ 72/* external Epson SG-615P */
64#define BASE_BAUD 691200 73#define BASE_BAUD 691200
@@ -66,7 +75,7 @@
66#define STD_UART_OP(num) \ 75#define STD_UART_OP(num) \
67 { 0, BASE_BAUD, 0, UART##num##_INT, \ 76 { 0, BASE_BAUD, 0, UART##num##_INT, \
68 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 77 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
69 iomem_base: UART##num##_IO_BASE, \ 78 iomem_base: (void*)UART##num##_IO_BASE, \
70 io_type: SERIAL_IO_MEM}, 79 io_type: SERIAL_IO_MEM},
71 80
72#define SERIAL_PORT_DFNS \ 81#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
new file mode 100644
index 000000000000..284da01f1ffd
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.c
@@ -0,0 +1,220 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440ep.c
3 *
4 * PPC440EP I/O descriptions
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright 2004 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <platforms/4xx/ibm440ep.h>
18#include <asm/ocp.h>
19#include <asm/ppc4xx_pic.h>
20
21static struct ocp_func_emac_data ibm440ep_emac0_def = {
22 .rgmii_idx = -1, /* No RGMII */
23 .rgmii_mux = -1, /* No RGMII */
24 .zmii_idx = 0, /* ZMII device index */
25 .zmii_mux = 0, /* ZMII input of this EMAC */
26 .mal_idx = 0, /* MAL device index */
27 .mal_rx_chan = 0, /* MAL rx channel number */
28 .mal_tx_chan = 0, /* MAL tx channel number */
29 .wol_irq = 61, /* WOL interrupt number */
30 .mdio_idx = -1, /* No shared MDIO */
31 .tah_idx = -1, /* No TAH */
32};
33
34static struct ocp_func_emac_data ibm440ep_emac1_def = {
35 .rgmii_idx = -1, /* No RGMII */
36 .rgmii_mux = -1, /* No RGMII */
37 .zmii_idx = 0, /* ZMII device index */
38 .zmii_mux = 1, /* ZMII input of this EMAC */
39 .mal_idx = 0, /* MAL device index */
40 .mal_rx_chan = 1, /* MAL rx channel number */
41 .mal_tx_chan = 2, /* MAL tx channel number */
42 .wol_irq = 63, /* WOL interrupt number */
43 .mdio_idx = -1, /* No shared MDIO */
44 .tah_idx = -1, /* No TAH */
45};
46OCP_SYSFS_EMAC_DATA()
47
48static struct ocp_func_mal_data ibm440ep_mal0_def = {
49 .num_tx_chans = 4, /* Number of TX channels */
50 .num_rx_chans = 2, /* Number of RX channels */
51 .txeob_irq = 10, /* TX End Of Buffer IRQ */
52 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
53 .txde_irq = 33, /* TX Descriptor Error IRQ */
54 .rxde_irq = 34, /* RX Descriptor Error IRQ */
55 .serr_irq = 32, /* MAL System Error IRQ */
56};
57OCP_SYSFS_MAL_DATA()
58
59static struct ocp_func_iic_data ibm440ep_iic0_def = {
60 .fast_mode = 0, /* Use standad mode (100Khz) */
61};
62
63static struct ocp_func_iic_data ibm440ep_iic1_def = {
64 .fast_mode = 0, /* Use standad mode (100Khz) */
65};
66OCP_SYSFS_IIC_DATA()
67
68struct ocp_def core_ocp[] = {
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_OPB,
71 .index = 0,
72 .paddr = 0x0EF600000ULL,
73 .irq = OCP_IRQ_NA,
74 .pm = OCP_CPM_NA,
75 },
76 { .vendor = OCP_VENDOR_IBM,
77 .function = OCP_FUNC_16550,
78 .index = 0,
79 .paddr = PPC440EP_UART0_ADDR,
80 .irq = UART0_INT,
81 .pm = IBM_CPM_UART0,
82 },
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_16550,
85 .index = 1,
86 .paddr = PPC440EP_UART1_ADDR,
87 .irq = UART1_INT,
88 .pm = IBM_CPM_UART1,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 2,
93 .paddr = PPC440EP_UART2_ADDR,
94 .irq = UART2_INT,
95 .pm = IBM_CPM_UART2,
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 3,
100 .paddr = PPC440EP_UART3_ADDR,
101 .irq = UART3_INT,
102 .pm = IBM_CPM_UART3,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .index = 0,
107 .paddr = 0x0EF600700ULL,
108 .irq = 2,
109 .pm = IBM_CPM_IIC0,
110 .additions = &ibm440ep_iic0_def,
111 .show = &ocp_show_iic_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_IIC,
115 .index = 1,
116 .paddr = 0x0EF600800ULL,
117 .irq = 7,
118 .pm = IBM_CPM_IIC1,
119 .additions = &ibm440ep_iic1_def,
120 .show = &ocp_show_iic_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_GPIO,
124 .index = 0,
125 .paddr = 0x0EF600B00ULL,
126 .irq = OCP_IRQ_NA,
127 .pm = IBM_CPM_GPIO0,
128 },
129 { .vendor = OCP_VENDOR_IBM,
130 .function = OCP_FUNC_GPIO,
131 .index = 1,
132 .paddr = 0x0EF600C00ULL,
133 .irq = OCP_IRQ_NA,
134 .pm = OCP_CPM_NA,
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_MAL,
138 .paddr = OCP_PADDR_NA,
139 .irq = OCP_IRQ_NA,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440ep_mal0_def,
142 .show = &ocp_show_mal_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 0,
147 .paddr = 0x0EF600E00ULL,
148 .irq = 60,
149 .pm = OCP_CPM_NA,
150 .additions = &ibm440ep_emac0_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 1,
156 .paddr = 0x0EF600F00ULL,
157 .irq = 62,
158 .pm = OCP_CPM_NA,
159 .additions = &ibm440ep_emac1_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0x0EF600D00ULL,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
171
172/* Polarity and triggering settings for internal interrupt sources */
173struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
174 { .polarity = 0xffbffe03,
175 .triggering = 0xfffffe00,
176 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
177 },
178 { .polarity = 0xffffc6ef,
179 .triggering = 0xffffc7ff,
180 .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
181 },
182};
183
184static struct resource usb_gadget_resources[] = {
185 [0] = {
186 .start = 0x050000100ULL,
187 .end = 0x05000017FULL,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = 55,
192 .end = 55,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static u64 dma_mask = 0xffffffffULL;
198
199static struct platform_device usb_gadget_device = {
200 .name = "musbhsfc",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(usb_gadget_resources),
203 .resource = usb_gadget_resources,
204 .dev = {
205 .dma_mask = &dma_mask,
206 .coherent_dma_mask = 0xffffffffULL,
207 }
208};
209
210static struct platform_device *ibm440ep_devs[] __initdata = {
211 &usb_gadget_device,
212};
213
214static int __init
215ibm440ep_platform_add_devices(void)
216{
217 return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
218}
219arch_initcall(ibm440ep_platform_add_devices);
220
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
new file mode 100644
index 000000000000..97c80b8e3e10
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.h
@@ -0,0 +1,76 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440ep.h
3 *
4 * PPC440EP definitions
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 *
8 * Copyright 2002 Roland Dreier
9 * Copyright 2004 MontaVista Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __PPC_PLATFORMS_IBM440EP_H
20#define __PPC_PLATFORMS_IBM440EP_H
21
22#include <linux/config.h>
23#include <asm/ibm44x.h>
24
25/* UART */
26#define PPC440EP_UART0_ADDR 0x0EF600300
27#define PPC440EP_UART1_ADDR 0x0EF600400
28#define PPC440EP_UART2_ADDR 0x0EF600500
29#define PPC440EP_UART3_ADDR 0x0EF600600
30#define UART0_INT 0
31#define UART1_INT 1
32#define UART2_INT 3
33#define UART3_INT 4
34
35/* Clock and Power Management */
36#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
37#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
38#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
39#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
40#define IBM_CPM_FPU 0x04000000 /* floating point unit */
41#define IBM_CPM_CPU 0x02000000 /* processor core */
42#define IBM_CPM_DMA 0x01000000 /* DMA controller */
43#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
44#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
45#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
46#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
47#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
48#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
49#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
50#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
51#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
52#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
53#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
54#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
55#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
56#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
57#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
58#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
59#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
60#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
61#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
62#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
63#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
64#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
65#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
66
67#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
68 | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
69 | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
70 | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
71 | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
72 | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
73
74
75#endif /* __PPC_PLATFORMS_IBM440EP_H */
76#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index a203efb47aba..fa3e003a0db9 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -36,8 +36,8 @@ static struct ocp_func_emac_data ibm440sp_emac0_def = {
36OCP_SYSFS_EMAC_DATA() 36OCP_SYSFS_EMAC_DATA()
37 37
38static struct ocp_func_mal_data ibm440sp_mal0_def = { 38static struct ocp_func_mal_data ibm440sp_mal0_def = {
39 .num_tx_chans = 4, /* Number of TX channels */ 39 .num_tx_chans = 1, /* Number of TX channels */
40 .num_rx_chans = 4, /* Number of RX channels */ 40 .num_rx_chans = 1, /* Number of RX channels */
41 .txeob_irq = 38, /* TX End Of Buffer IRQ */ 41 .txeob_irq = 38, /* TX End Of Buffer IRQ */
42 .rxeob_irq = 39, /* RX End Of Buffer IRQ */ 42 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
43 .txde_irq = 34, /* TX Descriptor Error IRQ */ 43 .txde_irq = 34, /* TX Descriptor Error IRQ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 5f82a6bc7046..8fc34a344769 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -48,6 +48,7 @@
48#include <asm/bootinfo.h> 48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h> 49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h> 50#include <asm/ppcboot.h>
51#include <asm/tlbflush.h>
51 52
52#include <syslib/gen550.h> 53#include <syslib/gen550.h>
53#include <syslib/ibm440gx_common.h> 54#include <syslib/ibm440gx_common.h>
@@ -266,6 +267,9 @@ ocotea_early_serial_map(void)
266#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 267#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
267 /* Configure debug serial access */ 268 /* Configure debug serial access */
268 gen550_init(0, &port); 269 gen550_init(0, &port);
270
271 /* Purge TLB entry added in head_44x.S for early serial access */
272 _tlbie(UART0_IO_BASE);
269#endif 273#endif
270 274
271 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); 275 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
index 202dc8251190..33251153ac5f 100644
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -55,15 +55,24 @@
55 */ 55 */
56#define RS_TABLE_SIZE 2 56#define RS_TABLE_SIZE 2
57 57
58/* OpenBIOS defined UART mappings, used before early_serial_setup */ 58#if defined(__BOOTER__)
59/* OpenBIOS defined UART mappings, used by bootloader shim */
59#define UART0_IO_BASE 0xE0000200 60#define UART0_IO_BASE 0xE0000200
60#define UART1_IO_BASE 0xE0000300 61#define UART1_IO_BASE 0xE0000300
62#else
63/* head_44x.S created UART mapping, used before early_serial_setup.
64 * We cannot use default OpenBIOS UART mappings because they
65 * don't work for configurations with more than 512M RAM. --ebs
66 */
67#define UART0_IO_BASE 0xF0000200
68#define UART1_IO_BASE 0xF0000300
69#endif
61 70
62#define BASE_BAUD 11059200/16 71#define BASE_BAUD 11059200/16
63#define STD_UART_OP(num) \ 72#define STD_UART_OP(num) \
64 { 0, BASE_BAUD, 0, UART##num##_INT, \ 73 { 0, BASE_BAUD, 0, UART##num##_INT, \
65 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 74 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
66 iomem_base: UART##num##_IO_BASE, \ 75 iomem_base: (void*)UART##num##_IO_BASE, \
67 io_type: SERIAL_IO_MEM}, 76 io_type: SERIAL_IO_MEM},
68 77
69#define SERIAL_PORT_DFNS \ 78#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index 86ca5cf81263..ddd04d4c1ea9 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -94,20 +94,24 @@ mpc834x_sys_setup_arch(void)
94 94
95 /* setup the board related information for the enet controllers */ 95 /* setup the board related information for the enet controllers */
96 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1); 96 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
97 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 97 if (pdata) {
98 pdata->interruptPHY = MPC83xx_IRQ_EXT1; 98 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
99 pdata->phyid = 0; 99 pdata->interruptPHY = MPC83xx_IRQ_EXT1;
100 /* fixup phy address */ 100 pdata->phyid = 0;
101 pdata->phy_reg_addr += binfo->bi_immr_base; 101 /* fixup phy address */
102 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 102 pdata->phy_reg_addr += binfo->bi_immr_base;
103 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
104 }
103 105
104 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2); 106 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
105 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 107 if (pdata) {
106 pdata->interruptPHY = MPC83xx_IRQ_EXT2; 108 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
107 pdata->phyid = 1; 109 pdata->interruptPHY = MPC83xx_IRQ_EXT2;
108 /* fixup phy address */ 110 pdata->phyid = 1;
109 pdata->phy_reg_addr += binfo->bi_immr_base; 111 /* fixup phy address */
110 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 112 pdata->phy_reg_addr += binfo->bi_immr_base;
113 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
114 }
111 115
112#ifdef CONFIG_BLK_DEV_INITRD 116#ifdef CONFIG_BLK_DEV_INITRD
113 if (initrd_start) 117 if (initrd_start)
@@ -185,6 +189,26 @@ mpc834x_sys_init_IRQ(void)
185 ipic_set_default_priority(); 189 ipic_set_default_priority();
186} 190}
187 191
192#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
193extern ulong ds1374_get_rtc_time(void);
194extern int ds1374_set_rtc_time(ulong);
195
196static int __init
197mpc834x_rtc_hookup(void)
198{
199 struct timespec tv;
200
201 ppc_md.get_rtc_time = ds1374_get_rtc_time;
202 ppc_md.set_rtc_time = ds1374_set_rtc_time;
203
204 tv.tv_nsec = 0;
205 tv.tv_sec = (ppc_md.get_rtc_time)();
206 do_settimeofday(&tv);
207
208 return 0;
209}
210late_initcall(mpc834x_rtc_hookup);
211#endif
188static __inline__ void 212static __inline__ void
189mpc834x_sys_set_bat(void) 213mpc834x_sys_set_bat(void)
190{ 214{
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index a2ed611cd936..f761fdf160db 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -92,28 +92,34 @@ mpc8540ads_setup_arch(void)
92 92
93 /* setup the board related information for the enet controllers */ 93 /* setup the board related information for the enet controllers */
94 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 94 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
95 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 95 if (pdata) {
96 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 96 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
97 pdata->phyid = 0; 97 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
98 /* fixup phy address */ 98 pdata->phyid = 0;
99 pdata->phy_reg_addr += binfo->bi_immr_base; 99 /* fixup phy address */
100 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 100 pdata->phy_reg_addr += binfo->bi_immr_base;
101 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
102 }
101 103
102 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 104 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
103 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 105 if (pdata) {
104 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 106 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
105 pdata->phyid = 1; 107 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
106 /* fixup phy address */ 108 pdata->phyid = 1;
107 pdata->phy_reg_addr += binfo->bi_immr_base; 109 /* fixup phy address */
108 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 110 pdata->phy_reg_addr += binfo->bi_immr_base;
111 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
112 }
109 113
110 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 114 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
111 pdata->board_flags = 0; 115 if (pdata) {
112 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 116 pdata->board_flags = 0;
113 pdata->phyid = 3; 117 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
114 /* fixup phy address */ 118 pdata->phyid = 3;
115 pdata->phy_reg_addr += binfo->bi_immr_base; 119 /* fixup phy address */
116 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 120 pdata->phy_reg_addr += binfo->bi_immr_base;
121 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
122 }
117 123
118#ifdef CONFIG_BLK_DEV_INITRD 124#ifdef CONFIG_BLK_DEV_INITRD
119 if (initrd_start) 125 if (initrd_start)
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index d87dfd5ce0a2..f2748c88665a 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -56,7 +56,6 @@
56#include <syslib/ppc85xx_common.h> 56#include <syslib/ppc85xx_common.h>
57#include <syslib/ppc85xx_setup.h> 57#include <syslib/ppc85xx_setup.h>
58 58
59extern void cpm2_reset(void);
60 59
61/* ************************************************************************ 60/* ************************************************************************
62 * 61 *
@@ -90,20 +89,24 @@ mpc8560ads_setup_arch(void)
90 89
91 /* setup the board related information for the enet controllers */ 90 /* setup the board related information for the enet controllers */
92 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 91 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
93 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 92 if (pdata) {
94 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 93 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
95 pdata->phyid = 0; 94 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
96 /* fixup phy address */ 95 pdata->phyid = 0;
97 pdata->phy_reg_addr += binfo->bi_immr_base; 96 /* fixup phy address */
98 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 97 pdata->phy_reg_addr += binfo->bi_immr_base;
98 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
99 }
99 100
100 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 101 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
101 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 102 if (pdata) {
102 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 103 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
103 pdata->phyid = 1; 104 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
104 /* fixup phy address */ 105 pdata->phyid = 1;
105 pdata->phy_reg_addr += binfo->bi_immr_base; 106 /* fixup phy address */
106 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 107 pdata->phy_reg_addr += binfo->bi_immr_base;
108 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
109 }
107 110
108#ifdef CONFIG_BLK_DEV_INITRD 111#ifdef CONFIG_BLK_DEV_INITRD
109 if (initrd_start) 112 if (initrd_start)
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index 203b2ca61df8..6267b294f704 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -49,7 +49,7 @@
49#include <asm/mpc85xx.h> 49#include <asm/mpc85xx.h>
50#include <asm/irq.h> 50#include <asm/irq.h>
51#include <asm/immap_85xx.h> 51#include <asm/immap_85xx.h>
52#include <asm/immap_cpm2.h> 52#include <asm/cpm2.h>
53#include <asm/ppc_sys.h> 53#include <asm/ppc_sys.h>
54#include <asm/kgdb.h> 54#include <asm/kgdb.h>
55 55
@@ -149,6 +149,7 @@ void __init
149mpc85xx_cds_init_IRQ(void) 149mpc85xx_cds_init_IRQ(void)
150{ 150{
151 bd_t *binfo = (bd_t *) __res; 151 bd_t *binfo = (bd_t *) __res;
152 int i;
152 153
153 /* Determine the Physical Address of the OpenPIC regs */ 154 /* Determine the Physical Address of the OpenPIC regs */
154 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; 155 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index 3dbdd73618eb..165df94d4aa6 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -129,20 +129,24 @@ sbc8560_setup_arch(void)
129 129
130 /* setup the board related information for the enet controllers */ 130 /* setup the board related information for the enet controllers */
131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
132 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 132 if (pdata) {
133 pdata->interruptPHY = MPC85xx_IRQ_EXT6; 133 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
134 pdata->phyid = 25; 134 pdata->interruptPHY = MPC85xx_IRQ_EXT6;
135 /* fixup phy address */ 135 pdata->phyid = 25;
136 pdata->phy_reg_addr += binfo->bi_immr_base; 136 /* fixup phy address */
137 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 137 pdata->phy_reg_addr += binfo->bi_immr_base;
138 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
139 }
138 140
139 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 141 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
140 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 142 if (pdata) {
141 pdata->interruptPHY = MPC85xx_IRQ_EXT7; 143 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
142 pdata->phyid = 26; 144 pdata->interruptPHY = MPC85xx_IRQ_EXT7;
143 /* fixup phy address */ 145 pdata->phyid = 26;
144 pdata->phy_reg_addr += binfo->bi_immr_base; 146 /* fixup phy address */
145 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 147 pdata->phy_reg_addr += binfo->bi_immr_base;
148 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
149 }
146 150
147#ifdef CONFIG_BLK_DEV_INITRD 151#ifdef CONFIG_BLK_DEV_INITRD
148 if (initrd_start) 152 if (initrd_start)
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index 9455bb6b45e9..c99b365d6110 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -52,14 +52,13 @@
52#include <asm/mpc85xx.h> 52#include <asm/mpc85xx.h>
53#include <asm/irq.h> 53#include <asm/irq.h>
54#include <asm/immap_85xx.h> 54#include <asm/immap_85xx.h>
55#include <asm/immap_cpm2.h> 55#include <asm/cpm2.h>
56#include <asm/mpc85xx.h> 56#include <asm/mpc85xx.h>
57#include <asm/ppc_sys.h> 57#include <asm/ppc_sys.h>
58 58
59#include <syslib/cpm2_pic.h> 59#include <syslib/cpm2_pic.h>
60#include <syslib/ppc85xx_common.h> 60#include <syslib/ppc85xx_common.h>
61 61
62extern void cpm2_reset(void);
63 62
64unsigned char __res[sizeof(bd_t)]; 63unsigned char __res[sizeof(bd_t)];
65 64
@@ -122,19 +121,23 @@ gp3_setup_arch(void)
122 121
123 /* setup the board related information for the enet controllers */ 122 /* setup the board related information for the enet controllers */
124 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 123 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
125/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 124 if (pdata) {
126 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 125 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
127 pdata->phyid = 2; 126 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
128 pdata->phy_reg_addr += binfo->bi_immr_base; 127 pdata->phyid = 2;
129 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 128 pdata->phy_reg_addr += binfo->bi_immr_base;
129 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
130 }
130 131
131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 132 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
132/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 133 if (pdata) {
133 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 134 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
134 pdata->phyid = 4; 135 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
135 /* fixup phy address */ 136 pdata->phyid = 4;
136 pdata->phy_reg_addr += binfo->bi_immr_base; 137 /* fixup phy address */
137 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 138 pdata->phy_reg_addr += binfo->bi_immr_base;
139 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
140 }
138 141
139#ifdef CONFIG_BLK_DEV_INITRD 142#ifdef CONFIG_BLK_DEV_INITRD
140 if (initrd_start) 143 if (initrd_start)
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
index 7d0ee308f662..7d3fbb5c5db2 100644
--- a/arch/ppc/platforms/chrp_pci.c
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -9,7 +9,6 @@
9#include <linux/string.h> 9#include <linux/string.h>
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/ide.h> 11#include <linux/ide.h>
12#include <linux/bootmem.h>
13 12
14#include <asm/io.h> 13#include <asm/io.h>
15#include <asm/pgtable.h> 14#include <asm/pgtable.h>
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
index 632b8178ce66..b60c56450b67 100644
--- a/arch/ppc/platforms/fads.h
+++ b/arch/ppc/platforms/fads.h
@@ -3,7 +3,18 @@
3 * the Motorola 860T FADS board. Copied from the MBX stuff. 3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * 4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) 5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 *
7 * Added MPC86XADS support.
8 * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
9 * for SW point of view". This is 99% correct.
10 *
11 * Author: MontaVista Software, Inc.
12 * source@mvista.com
13 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
14 * terms of the GNU General Public License version 2. This program is licensed
15 * "as is" without any warranty of any kind, whether express or implied.
6 */ 16 */
17
7#ifdef __KERNEL__ 18#ifdef __KERNEL__
8#ifndef __ASM_FADS_H__ 19#ifndef __ASM_FADS_H__
9#define __ASM_FADS_H__ 20#define __ASM_FADS_H__
@@ -12,18 +23,45 @@
12 23
13#include <asm/ppcboot.h> 24#include <asm/ppcboot.h>
14 25
26#if defined(CONFIG_MPC86XADS)
27
28/* U-Boot maps BCSR to 0xff080000 */
29#define BCSR_ADDR ((uint)0xff080000)
30
31/* MPC86XADS has one more CPLD and an additional BCSR.
32 */
33#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
34#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
35
36#define BCSR5_T1_RST 0x10
37#define BCSR5_ATM155_RST 0x08
38#define BCSR5_ATM25_RST 0x04
39#define BCSR5_MII1_EN 0x02
40#define BCSR5_MII1_RST 0x01
41
42/* There is no PHY link change interrupt */
43#define PHY_INTERRUPT (-1)
44
45#else /* FADS */
46
15/* Memory map is configured by the PROM startup. 47/* Memory map is configured by the PROM startup.
16 * I tried to follow the FADS manual, although the startup PROM 48 * I tried to follow the FADS manual, although the startup PROM
17 * dictates this and we simply have to move some of the physical 49 * dictates this and we simply have to move some of the physical
18 * addresses for Linux. 50 * addresses for Linux.
19 */ 51 */
20#define BCSR_ADDR ((uint)0xff010000) 52#define BCSR_ADDR ((uint)0xff010000)
53
54/* PHY link change interrupt */
55#define PHY_INTERRUPT SIU_IRQ2
56
57#endif /* CONFIG_MPC86XADS */
58
21#define BCSR_SIZE ((uint)(64 * 1024)) 59#define BCSR_SIZE ((uint)(64 * 1024))
22#define BCSR0 ((uint)0xff010000) 60#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
23#define BCSR1 ((uint)0xff010004) 61#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
24#define BCSR2 ((uint)0xff010008) 62#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
25#define BCSR3 ((uint)0xff01000c) 63#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
26#define BCSR4 ((uint)0xff010010) 64#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
27 65
28#define IMAP_ADDR ((uint)0xff000000) 66#define IMAP_ADDR ((uint)0xff000000)
29#define IMAP_SIZE ((uint)(64 * 1024)) 67#define IMAP_SIZE ((uint)(64 * 1024))
@@ -34,8 +72,17 @@
34/* Bits of interest in the BCSRs. 72/* Bits of interest in the BCSRs.
35 */ 73 */
36#define BCSR1_ETHEN ((uint)0x20000000) 74#define BCSR1_ETHEN ((uint)0x20000000)
75#define BCSR1_IRDAEN ((uint)0x10000000)
37#define BCSR1_RS232EN_1 ((uint)0x01000000) 76#define BCSR1_RS232EN_1 ((uint)0x01000000)
77#define BCSR1_PCCEN ((uint)0x00800000)
78#define BCSR1_PCCVCC0 ((uint)0x00400000)
79#define BCSR1_PCCVPP0 ((uint)0x00200000)
80#define BCSR1_PCCVPP1 ((uint)0x00100000)
81#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
38#define BCSR1_RS232EN_2 ((uint)0x00040000) 82#define BCSR1_RS232EN_2 ((uint)0x00040000)
83#define BCSR1_PCCVCC1 ((uint)0x00010000)
84#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
85
39#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */ 86#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */
40#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */ 87#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */
41#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */ 88#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */
@@ -44,14 +91,64 @@
44#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */ 91#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */
45#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */ 92#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */
46 93
94/* IO_BASE definition for pcmcia.
95 */
96#define _IO_BASE 0x80000000
97#define _IO_BASE_SIZE 0x1000
98
99#ifdef CONFIG_IDE
100#define MAX_HWIFS 1
101#endif
102
47/* Interrupt level assignments. 103/* Interrupt level assignments.
48 */ 104 */
49#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ 105#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
50#define PHY_INTERRUPT SIU_IRQ2 /* PHY link change interrupt */
51 106
52/* We don't use the 8259. 107/* We don't use the 8259.
53 */ 108 */
54#define NR_8259_INTS 0 109#define NR_8259_INTS 0
55 110
111/* CPM Ethernet through SCC1 or SCC2 */
112
113#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */
114/* Bits in parallel I/O port registers that have to be set/cleared
115 * to configure the pins for SCC1 use.
116 * TCLK - CLK1, RCLK - CLK2.
117 */
118#define PA_ENET_RXD ((ushort)0x0001)
119#define PA_ENET_TXD ((ushort)0x0002)
120#define PA_ENET_TCLK ((ushort)0x0100)
121#define PA_ENET_RCLK ((ushort)0x0200)
122#define PB_ENET_TENA ((uint)0x00001000)
123#define PC_ENET_CLSN ((ushort)0x0010)
124#define PC_ENET_RENA ((ushort)0x0020)
125
126/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
127 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
128 */
129#define SICR_ENET_MASK ((uint)0x000000ff)
130#define SICR_ENET_CLKRT ((uint)0x0000002c)
131#endif /* CONFIG_SCC1_ENET */
132
133#ifdef CONFIG_SCC2_ENET /* Probably 823/850 variant */
134/* Bits in parallel I/O port registers that have to be set/cleared
135 * to configure the pins for SCC1 use.
136 * TCLK - CLK1, RCLK - CLK2.
137 */
138#define PA_ENET_RXD ((ushort)0x0004)
139#define PA_ENET_TXD ((ushort)0x0008)
140#define PA_ENET_TCLK ((ushort)0x0400)
141#define PA_ENET_RCLK ((ushort)0x0200)
142#define PB_ENET_TENA ((uint)0x00002000)
143#define PC_ENET_CLSN ((ushort)0x0040)
144#define PC_ENET_RENA ((ushort)0x0080)
145
146/* Control bits in the SICR to route TCLK and RCLK to
147 * SCC2. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
148 */
149#define SICR_ENET_MASK ((uint)0x0000ff00)
150#define SICR_ENET_CLKRT ((uint)0x00002e00)
151#endif /* CONFIG_SCC2_ENET */
152
56#endif /* __ASM_FADS_H__ */ 153#endif /* __ASM_FADS_H__ */
57#endif /* __KERNEL__ */ 154#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
index eda922ac3167..169dbf6534b9 100644
--- a/arch/ppc/platforms/katana.c
+++ b/arch/ppc/platforms/katana.c
@@ -27,12 +27,12 @@
27#include <linux/root_dev.h> 27#include <linux/root_dev.h>
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/seq_file.h> 29#include <linux/seq_file.h>
30#include <linux/bootmem.h>
31#include <linux/mtd/physmap.h> 30#include <linux/mtd/physmap.h>
32#include <linux/mv643xx.h> 31#include <linux/mv643xx.h>
33#ifdef CONFIG_BOOTIMG 32#ifdef CONFIG_BOOTIMG
34#include <linux/bootimg.h> 33#include <linux/bootimg.h>
35#endif 34#endif
35#include <asm/io.h>
36#include <asm/page.h> 36#include <asm/page.h>
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/smp.h> 38#include <asm/smp.h>
diff --git a/arch/ppc/platforms/mpc885ads.h b/arch/ppc/platforms/mpc885ads.h
new file mode 100644
index 000000000000..eb386635b0fd
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads.h
@@ -0,0 +1,92 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Freescale MPC885ADS board.
4 * Copied from the FADS stuff.
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_MPC885ADS_H__
16#define __ASM_MPC885ADS_H__
17
18#include <linux/config.h>
19
20#include <asm/ppcboot.h>
21
22/* U-Boot maps BCSR to 0xff080000 */
23#define BCSR_ADDR ((uint)0xff080000)
24#define BCSR_SIZE ((uint)32)
25#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
26#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
27#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
28#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
29#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
30
31#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
32#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
33
34#define IMAP_ADDR ((uint)0xff000000)
35#define IMAP_SIZE ((uint)(64 * 1024))
36
37#define PCMCIA_MEM_ADDR ((uint)0xff020000)
38#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
39
40/* Bits of interest in the BCSRs.
41 */
42#define BCSR1_ETHEN ((uint)0x20000000)
43#define BCSR1_IRDAEN ((uint)0x10000000)
44#define BCSR1_RS232EN_1 ((uint)0x01000000)
45#define BCSR1_PCCEN ((uint)0x00800000)
46#define BCSR1_PCCVCC0 ((uint)0x00400000)
47#define BCSR1_PCCVPP0 ((uint)0x00200000)
48#define BCSR1_PCCVPP1 ((uint)0x00100000)
49#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
50#define BCSR1_RS232EN_2 ((uint)0x00040000)
51#define BCSR1_PCCVCC1 ((uint)0x00010000)
52#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
53
54#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
55#define BCSR4_USB_LO_SPD ((uint)0x04000000)
56#define BCSR4_USB_VCC ((uint)0x02000000)
57#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
58#define BCSR4_USB_EN ((uint)0x00020000)
59
60#define BCSR5_MII2_EN 0x40
61#define BCSR5_MII2_RST 0x20
62#define BCSR5_T1_RST 0x10
63#define BCSR5_ATM155_RST 0x08
64#define BCSR5_ATM25_RST 0x04
65#define BCSR5_MII1_EN 0x02
66#define BCSR5_MII1_RST 0x01
67
68/* Interrupt level assignments */
69#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
70#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
71#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
72#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
73
74/* We don't use the 8259 */
75#define NR_8259_INTS 0
76
77/* CPM Ethernet through SCC3 */
78#define PA_ENET_RXD ((ushort)0x0040)
79#define PA_ENET_TXD ((ushort)0x0080)
80#define PE_ENET_TCLK ((uint)0x00004000)
81#define PE_ENET_RCLK ((uint)0x00008000)
82#define PE_ENET_TENA ((uint)0x00000010)
83#define PC_ENET_CLSN ((ushort)0x0400)
84#define PC_ENET_RENA ((ushort)0x0800)
85
86/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
87 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
88#define SICR_ENET_MASK ((uint)0x00ff0000)
89#define SICR_ENET_CLKRT ((uint)0x002c0000)
90
91#endif /* __ASM_MPC885ADS_H__ */
92#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
index 5fdd4f607a40..c0605244edda 100644
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ b/arch/ppc/platforms/pmac_cpufreq.c
@@ -452,7 +452,7 @@ static u32 __pmac read_gpio(struct device_node *np)
452 return offset; 452 return offset;
453} 453}
454 454
455static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, u32 state) 455static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
456{ 456{
457 /* Ok, this could be made a bit smarter, but let's be robust for now. We 457 /* Ok, this could be made a bit smarter, but let's be robust for now. We
458 * always force a speed change to high speed before sleep, to make sure 458 * always force a speed change to high speed before sleep, to make sure
diff --git a/arch/ppc/platforms/pmac_pci.c b/arch/ppc/platforms/pmac_pci.c
index f6ff51924061..719fb49fe2bc 100644
--- a/arch/ppc/platforms/pmac_pci.c
+++ b/arch/ppc/platforms/pmac_pci.c
@@ -17,7 +17,6 @@
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/string.h> 18#include <linux/string.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/bootmem.h>
21 20
22#include <asm/sections.h> 21#include <asm/sections.h>
23#include <asm/io.h> 22#include <asm/io.h>
diff --git a/arch/ppc/platforms/pmac_setup.c b/arch/ppc/platforms/pmac_setup.c
index 4d324b630f4f..b392b9a15987 100644
--- a/arch/ppc/platforms/pmac_setup.c
+++ b/arch/ppc/platforms/pmac_setup.c
@@ -113,7 +113,7 @@ extern int pmac_newworld;
113extern void zs_kgdb_hook(int tty_num); 113extern void zs_kgdb_hook(int tty_num);
114static void ohare_init(void); 114static void ohare_init(void);
115#ifdef CONFIG_BOOTX_TEXT 115#ifdef CONFIG_BOOTX_TEXT
116void pmac_progress(char *s, unsigned short hex); 116static void pmac_progress(char *s, unsigned short hex);
117#endif 117#endif
118 118
119sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN; 119sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
@@ -123,7 +123,7 @@ extern struct smp_ops_t psurge_smp_ops;
123extern struct smp_ops_t core99_smp_ops; 123extern struct smp_ops_t core99_smp_ops;
124#endif /* CONFIG_SMP */ 124#endif /* CONFIG_SMP */
125 125
126int __pmac 126static int __pmac
127pmac_show_cpuinfo(struct seq_file *m) 127pmac_show_cpuinfo(struct seq_file *m)
128{ 128{
129 struct device_node *np; 129 struct device_node *np;
@@ -227,7 +227,7 @@ pmac_show_cpuinfo(struct seq_file *m)
227 return 0; 227 return 0;
228} 228}
229 229
230int __openfirmware 230static int __openfirmware
231pmac_show_percpuinfo(struct seq_file *m, int i) 231pmac_show_percpuinfo(struct seq_file *m, int i)
232{ 232{
233#ifdef CONFIG_CPU_FREQ_PMAC 233#ifdef CONFIG_CPU_FREQ_PMAC
@@ -415,7 +415,7 @@ find_ide_boot(void)
415} 415}
416#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */ 416#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
417 417
418void __init 418static void __init
419find_boot_device(void) 419find_boot_device(void)
420{ 420{
421#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC) 421#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
@@ -512,7 +512,7 @@ note_bootable_part(dev_t dev, int part, int goodness)
512 } 512 }
513} 513}
514 514
515void __pmac 515static void __pmac
516pmac_restart(char *cmd) 516pmac_restart(char *cmd)
517{ 517{
518#ifdef CONFIG_ADB_CUDA 518#ifdef CONFIG_ADB_CUDA
@@ -537,7 +537,7 @@ pmac_restart(char *cmd)
537 } 537 }
538} 538}
539 539
540void __pmac 540static void __pmac
541pmac_power_off(void) 541pmac_power_off(void)
542{ 542{
543#ifdef CONFIG_ADB_CUDA 543#ifdef CONFIG_ADB_CUDA
@@ -562,7 +562,7 @@ pmac_power_off(void)
562 } 562 }
563} 563}
564 564
565void __pmac 565static void __pmac
566pmac_halt(void) 566pmac_halt(void)
567{ 567{
568 pmac_power_off(); 568 pmac_power_off();
@@ -700,7 +700,7 @@ pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
700} 700}
701 701
702#ifdef CONFIG_BOOTX_TEXT 702#ifdef CONFIG_BOOTX_TEXT
703void __init 703static void __init
704pmac_progress(char *s, unsigned short hex) 704pmac_progress(char *s, unsigned short hex)
705{ 705{
706 if (boot_text_mapped) { 706 if (boot_text_mapped) {
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
index f459ade1bd63..016a74649155 100644
--- a/arch/ppc/platforms/pmac_sleep.S
+++ b/arch/ppc/platforms/pmac_sleep.S
@@ -46,7 +46,7 @@
46 .section .text 46 .section .text
47 .align 5 47 .align 5
48 48
49#if defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ_PMAC) 49#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC)
50 50
51/* This gets called by via-pmu.c late during the sleep process. 51/* This gets called by via-pmu.c late during the sleep process.
52 * The PMU was already send the sleep command and will shut us down 52 * The PMU was already send the sleep command and will shut us down
@@ -382,7 +382,7 @@ turn_on_mmu:
382 isync 382 isync
383 rfi 383 rfi
384 384
385#endif /* defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_CPU_FREQ) */ 385#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
386 386
387 .section .data 387 .section .data
388 .balign L1_CACHE_LINE_SIZE 388 .balign L1_CACHE_LINE_SIZE
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
index de60ccc7db9f..778ce4fec368 100644
--- a/arch/ppc/platforms/pmac_time.c
+++ b/arch/ppc/platforms/pmac_time.c
@@ -206,7 +206,7 @@ via_calibrate_decr(void)
206 return 1; 206 return 1;
207} 207}
208 208
209#ifdef CONFIG_PMAC_PBOOK 209#ifdef CONFIG_PM
210/* 210/*
211 * Reset the time after a sleep. 211 * Reset the time after a sleep.
212 */ 212 */
@@ -238,7 +238,7 @@ time_sleep_notify(struct pmu_sleep_notifier *self, int when)
238static struct pmu_sleep_notifier time_sleep_notifier __pmacdata = { 238static struct pmu_sleep_notifier time_sleep_notifier __pmacdata = {
239 time_sleep_notify, SLEEP_LEVEL_MISC, 239 time_sleep_notify, SLEEP_LEVEL_MISC,
240}; 240};
241#endif /* CONFIG_PMAC_PBOOK */ 241#endif /* CONFIG_PM */
242 242
243/* 243/*
244 * Query the OF and get the decr frequency. 244 * Query the OF and get the decr frequency.
@@ -251,9 +251,9 @@ pmac_calibrate_decr(void)
251 struct device_node *cpu; 251 struct device_node *cpu;
252 unsigned int freq, *fp; 252 unsigned int freq, *fp;
253 253
254#ifdef CONFIG_PMAC_PBOOK 254#ifdef CONFIG_PM
255 pmu_register_sleep_notifier(&time_sleep_notifier); 255 pmu_register_sleep_notifier(&time_sleep_notifier);
256#endif /* CONFIG_PMAC_PBOOK */ 256#endif /* CONFIG_PM */
257 257
258 /* We assume MacRISC2 machines have correct device-tree 258 /* We assume MacRISC2 machines have correct device-tree
259 * calibration. That's better since the VIA itself seems 259 * calibration. That's better since the VIA itself seems
diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c
index c894e1ab5934..24ae1caafc61 100644
--- a/arch/ppc/platforms/prpmc750.c
+++ b/arch/ppc/platforms/prpmc750.c
@@ -29,6 +29,7 @@
29#include <linux/ide.h> 29#include <linux/ide.h>
30#include <linux/root_dev.h> 30#include <linux/root_dev.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/serial_reg.h>
32 33
33#include <asm/byteorder.h> 34#include <asm/byteorder.h>
34#include <asm/system.h> 35#include <asm/system.h>
diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c
index 70e58f43f2b8..21e31346b12b 100644
--- a/arch/ppc/platforms/sandpoint.c
+++ b/arch/ppc/platforms/sandpoint.c
@@ -311,19 +311,23 @@ sandpoint_setup_arch(void)
311 { 311 {
312 bd_t *bp = (bd_t *)__res; 312 bd_t *bp = (bd_t *)__res;
313 struct plat_serial8250_port *pdata; 313 struct plat_serial8250_port *pdata;
314 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_DUART);
315 314
315 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
316 if (pdata) 316 if (pdata)
317 { 317 {
318 pdata[0].uartclk = bp->bi_busfreq; 318 pdata[0].uartclk = bp->bi_busfreq;
319 pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); 319 }
320 320
321 /* this disables the 2nd serial port on the DUART 321#ifdef CONFIG_SANDPOINT_ENABLE_UART1
322 * since the sandpoint does not have it connected */ 322 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
323 pdata[1].uartclk = 0; 323 if (pdata)
324 pdata[1].irq = 0; 324 {
325 pdata[1].mapbase = 0; 325 pdata[0].uartclk = bp->bi_busfreq;
326 } 326 }
327#else
328 ppc_sys_device_remove(MPC10X_UART1);
329#endif
330 }
327 331
328 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); 332 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
329 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); 333 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c
index a8880bfc034b..3409139330b1 100644
--- a/arch/ppc/platforms/tqm8260_setup.c
+++ b/arch/ppc/platforms/tqm8260_setup.c
@@ -16,8 +16,8 @@
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18 18
19#include <asm/immap_cpm2.h>
20#include <asm/mpc8260.h> 19#include <asm/mpc8260.h>
20#include <asm/cpm2.h>
21#include <asm/machdep.h> 21#include <asm/machdep.h>
22 22
23static int 23static int
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 17:38:25 -0500