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-rw-r--r--arch/ppc/platforms/rpxclassic.h114
1 files changed, 0 insertions, 114 deletions
diff --git a/arch/ppc/platforms/rpxclassic.h b/arch/ppc/platforms/rpxclassic.h
deleted file mode 100644
index a3c1118e5b09..000000000000
--- a/arch/ppc/platforms/rpxclassic.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 */
7#ifdef __KERNEL__
8#ifndef __MACH_RPX_DEFS
9#define __MACH_RPX_DEFS
10
11
12#ifndef __ASSEMBLY__
13/* A Board Information structure that is given to a program when
14 * prom starts it up.
15 */
16typedef struct bd_info {
17 unsigned int bi_memstart; /* Memory start address */
18 unsigned int bi_memsize; /* Memory (end) size in bytes */
19 unsigned int bi_intfreq; /* Internal Freq, in Hz */
20 unsigned int bi_busfreq; /* Bus Freq, in Hz */
21 unsigned char bi_enetaddr[6];
22 unsigned int bi_baudrate;
23} bd_t;
24
25extern bd_t m8xx_board_info;
26
27/* Memory map is configured by the PROM startup.
28 * We just map a few things we need. The CSR is actually 4 byte-wide
29 * registers that can be accessed as 8-, 16-, or 32-bit values.
30 */
31#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
32#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
33#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
34#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
35#define RPX_CSR_ADDR ((uint)0xfa400000)
36#define RPX_CSR_SIZE ((uint)(4 * 1024))
37#define IMAP_ADDR ((uint)0xfa200000)
38#define IMAP_SIZE ((uint)(64 * 1024))
39#define PCI_CSR_ADDR ((uint)0x80000000)
40#define PCI_CSR_SIZE ((uint)(64 * 1024))
41#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
42#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
43#define PCMCIA_IO_ADDR ((uint)0xe4000000)
44#define PCMCIA_IO_SIZE ((uint)(4 * 1024))
45#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
46#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024))
47
48/* Things of interest in the CSR.
49*/
50#define BCSR0_ETHEN ((uint)0x80000000)
51#define BCSR0_ETHLPBK ((uint)0x40000000)
52#define BCSR0_COLTESTDIS ((uint)0x20000000)
53#define BCSR0_FULLDPLXDIS ((uint)0x10000000)
54#define BCSR0_ENFLSHSEL ((uint)0x04000000)
55#define BCSR0_FLASH_SEL ((uint)0x02000000)
56#define BCSR0_ENMONXCVR ((uint)0x01000000)
57
58#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */
59#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */
60#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */
61
62#define BCSR1_IPB5SEL ((uint)0x00100000)
63#define BCSR1_PCVCTL4 ((uint)0x00080000)
64#define BCSR1_PCVCTL5 ((uint)0x00040000)
65#define BCSR1_PCVCTL6 ((uint)0x00020000)
66#define BCSR1_PCVCTL7 ((uint)0x00010000)
67
68#define BCSR2_EN232XCVR ((uint)0x00008000)
69#define BCSR2_QSPACESEL ((uint)0x00004000)
70#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */
71
72/* define IO_BASE for pcmcia, CLLF only */
73#if !defined(CONFIG_PCI)
74#define _IO_BASE 0x80000000
75#define _IO_BASE_SIZE 0x1000
76
77/* for pcmcia sandisk */
78#ifdef CONFIG_IDE
79# define MAX_HWIFS 1
80#endif
81#endif
82
83/* Interrupt level assignments.
84*/
85#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
86
87
88/* CPM Ethernet through SCCx.
89 *
90 * Bits in parallel I/O port registers that have to be set/cleared
91 * to configure the pins for SCC1 use.
92 */
93#define PA_ENET_RXD ((ushort)0x0001)
94#define PA_ENET_TXD ((ushort)0x0002)
95#define PA_ENET_TCLK ((ushort)0x0200)
96#define PA_ENET_RCLK ((ushort)0x0800)
97#define PB_ENET_TENA ((uint)0x00001000)
98#define PC_ENET_CLSN ((ushort)0x0010)
99#define PC_ENET_RENA ((ushort)0x0020)
100
101/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
102 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
103 */
104#define SICR_ENET_MASK ((uint)0x000000ff)
105#define SICR_ENET_CLKRT ((uint)0x0000003d)
106
107/* We don't use the 8259.
108*/
109
110#define NR_8259_INTS 0
111
112#endif /* !__ASSEMBLY__ */
113#endif /* __MACH_RPX_DEFS */
114#endif /* __KERNEL__ */