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-rw-r--r--arch/ppc/platforms/pcore.c352
1 files changed, 0 insertions, 352 deletions
diff --git a/arch/ppc/platforms/pcore.c b/arch/ppc/platforms/pcore.c
deleted file mode 100644
index d7191630a650..000000000000
--- a/arch/ppc/platforms/pcore.c
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * arch/ppc/platforms/pcore_setup.c
3 *
4 * Setup routines for Force PCORE boards
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/types.h>
23#include <linux/major.h>
24#include <linux/initrd.h>
25#include <linux/console.h>
26#include <linux/irq.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29
30#include <asm/io.h>
31#include <asm/machdep.h>
32#include <asm/time.h>
33#include <asm/i8259.h>
34#include <asm/mpc10x.h>
35#include <asm/todc.h>
36#include <asm/bootinfo.h>
37#include <asm/kgdb.h>
38
39#include "pcore.h"
40
41extern unsigned long loops_per_jiffy;
42
43static int board_type;
44
45static inline int __init
46pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
47{
48 static char pci_irq_table[][4] =
49 /*
50 * PCI IDSEL/INTPIN->INTLINE
51 * A B C D
52 */
53 {
54 {9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
55 {10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
56 {11, 12, 9, 10}, /* IDSEL 26 - PMC I */
57 {12, 9, 10, 11}, /* IDSEL 27 - PMC II */
58 {0, 0, 0, 0}, /* IDSEL 28 - unused */
59 {0, 0, 9, 0}, /* IDSEL 29 - unused */
60 {0, 0, 0, 0}, /* IDSEL 30 - Winbond */
61 };
62 const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
63 return PCI_IRQ_TABLE_LOOKUP;
64};
65
66static inline int __init
67pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
68{
69 static char pci_irq_table[][4] =
70 /*
71 * PCI IDSEL/INTPIN->INTLINE
72 * A B C D
73 */
74 {
75 {9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
76 {10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
77 {11, 12, 9, 10}, /* IDSEL 26 - PMC I */
78 {12, 9, 10, 11}, /* IDSEL 27 - PMC II */
79 {9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */
80 {0, 0, 0, 0}, /* IDSEL 29 - unused */
81 {0, 0, 0, 0}, /* IDSEL 30 - Winbond */
82 };
83 const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
84 return PCI_IRQ_TABLE_LOOKUP;
85};
86
87void __init
88pcore_pcibios_fixup(void)
89{
90 struct pci_dev *dev;
91
92 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
93 PCI_DEVICE_ID_WINBOND_83C553,
94 0)))
95 {
96 /* Reroute interrupts both IDE channels to 15 */
97 pci_write_config_byte(dev,
98 PCORE_WINBOND_IDE_INT,
99 0xff);
100
101 /* Route INTA-D to IRQ9-12, respectively */
102 pci_write_config_word(dev,
103 PCORE_WINBOND_PCI_INT,
104 0x9abc);
105
106 /*
107 * Set up 8259 edge/level triggering
108 */
109 outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
110 outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
111 pci_dev_put(dev);
112 }
113}
114
115int __init
116pcore_find_bridges(void)
117{
118 struct pci_controller* hose;
119 int host_bridge, board_type;
120
121 hose = pcibios_alloc_controller();
122 if (!hose)
123 return 0;
124
125 mpc10x_bridge_init(hose,
126 MPC10X_MEM_MAP_B,
127 MPC10X_MEM_MAP_B,
128 MPC10X_MAPB_EUMB_BASE);
129
130 /* Determine board type */
131 early_read_config_dword(hose,
132 0,
133 PCI_DEVFN(0,0),
134 PCI_VENDOR_ID,
135 &host_bridge);
136 if (host_bridge == MPC10X_BRIDGE_106)
137 board_type = PCORE_TYPE_6750;
138 else /* MPC10X_BRIDGE_107 */
139 board_type = PCORE_TYPE_680;
140
141 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
142
143 ppc_md.pcibios_fixup = pcore_pcibios_fixup;
144 ppc_md.pci_swizzle = common_swizzle;
145
146 if (board_type == PCORE_TYPE_6750)
147 ppc_md.pci_map_irq = pcore_6750_map_irq;
148 else /* PCORE_TYPE_680 */
149 ppc_md.pci_map_irq = pcore_680_map_irq;
150
151 return board_type;
152}
153
154/* Dummy variable to satisfy mpc10x_common.o */
155void *OpenPIC_Addr;
156
157static int
158pcore_show_cpuinfo(struct seq_file *m)
159{
160 seq_printf(m, "vendor\t\t: Force Computers\n");
161
162 if (board_type == PCORE_TYPE_6750)
163 seq_printf(m, "machine\t\t: PowerCore 6750\n");
164 else /* PCORE_TYPE_680 */
165 seq_printf(m, "machine\t\t: PowerCore 680\n");
166
167 seq_printf(m, "L2\t\t: " );
168 if (board_type == PCORE_TYPE_6750)
169 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
170 {
171 case PCORE_DCCR_L2_0KB:
172 seq_printf(m, "nocache");
173 break;
174 case PCORE_DCCR_L2_256KB:
175 seq_printf(m, "256KB");
176 break;
177 case PCORE_DCCR_L2_1MB:
178 seq_printf(m, "1MB");
179 break;
180 case PCORE_DCCR_L2_512KB:
181 seq_printf(m, "512KB");
182 break;
183 default:
184 seq_printf(m, "error");
185 break;
186 }
187 else /* PCORE_TYPE_680 */
188 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
189 {
190 case PCORE_DCCR_L2_2MB:
191 seq_printf(m, "2MB");
192 break;
193 case PCORE_DCCR_L2_256KB:
194 seq_printf(m, "reserved");
195 break;
196 case PCORE_DCCR_L2_1MB:
197 seq_printf(m, "1MB");
198 break;
199 case PCORE_DCCR_L2_512KB:
200 seq_printf(m, "512KB");
201 break;
202 default:
203 seq_printf(m, "error");
204 break;
205 }
206
207 seq_printf(m, "\n");
208
209 return 0;
210}
211
212static void __init
213pcore_setup_arch(void)
214{
215 /* init to some ~sane value until calibrate_delay() runs */
216 loops_per_jiffy = 50000000/HZ;
217
218 /* Lookup PCI host bridges */
219 board_type = pcore_find_bridges();
220
221#ifdef CONFIG_BLK_DEV_INITRD
222 if (initrd_start)
223 ROOT_DEV = Root_RAM0;
224 else
225#endif
226#ifdef CONFIG_ROOT_NFS
227 ROOT_DEV = Root_NFS;
228#else
229 ROOT_DEV = Root_SDA2;
230#endif
231
232 printk(KERN_INFO "Force PowerCore ");
233 if (board_type == PCORE_TYPE_6750)
234 printk("6750\n");
235 else
236 printk("680\n");
237 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
238 _set_L2CR(L2CR_L2E | _get_L2CR());
239
240}
241
242static void
243pcore_restart(char *cmd)
244{
245 local_irq_disable();
246 /* Hard reset */
247 writeb(0x11, 0xfe000332);
248 while(1);
249}
250
251static void
252pcore_halt(void)
253{
254 local_irq_disable();
255 /* Turn off user LEDs */
256 writeb(0x00, 0xfe000300);
257 while (1);
258}
259
260static void
261pcore_power_off(void)
262{
263 pcore_halt();
264}
265
266
267static void __init
268pcore_init_IRQ(void)
269{
270 int i;
271
272 for ( i = 0 ; i < 16 ; i++ )
273 irq_desc[i].handler = &i8259_pic;
274
275 i8259_init(0);
276}
277
278/*
279 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
280 */
281static __inline__ void
282pcore_set_bat(void)
283{
284 mb();
285 mtspr(SPRN_DBAT3U, 0xf0001ffe);
286 mtspr(SPRN_DBAT3L, 0xfe80002a);
287 mb();
288
289}
290
291static unsigned long __init
292pcore_find_end_of_memory(void)
293{
294
295 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
296}
297
298static void __init
299pcore_map_io(void)
300{
301 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
302}
303
304TODC_ALLOC();
305
306void __init
307platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
308 unsigned long r6, unsigned long r7)
309{
310 parse_bootinfo(find_bootinfo());
311
312 /* Cover I/O space with a BAT */
313 /* yuck, better hope your ram size is a power of 2 -- paulus */
314 pcore_set_bat();
315
316 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
317 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
318 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
319
320 ppc_md.setup_arch = pcore_setup_arch;
321 ppc_md.show_cpuinfo = pcore_show_cpuinfo;
322 ppc_md.init_IRQ = pcore_init_IRQ;
323 ppc_md.get_irq = i8259_irq;
324
325 ppc_md.find_end_of_memory = pcore_find_end_of_memory;
326 ppc_md.setup_io_mappings = pcore_map_io;
327
328 ppc_md.restart = pcore_restart;
329 ppc_md.power_off = pcore_power_off;
330 ppc_md.halt = pcore_halt;
331
332 TODC_INIT(TODC_TYPE_MK48T59,
333 PCORE_NVRAM_AS0,
334 PCORE_NVRAM_AS1,
335 PCORE_NVRAM_DATA,
336 8);
337
338 ppc_md.time_init = todc_time_init;
339 ppc_md.get_rtc_time = todc_get_rtc_time;
340 ppc_md.set_rtc_time = todc_set_rtc_time;
341 ppc_md.calibrate_decr = todc_calibrate_decr;
342
343 ppc_md.nvram_read_val = todc_m48txx_read_val;
344 ppc_md.nvram_write_val = todc_m48txx_write_val;
345
346#ifdef CONFIG_SERIAL_TEXT_DEBUG
347 ppc_md.progress = gen550_progress;
348#endif
349#ifdef CONFIG_KGDB
350 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
351#endif
352}
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