1 files changed, 4 insertions, 113 deletions

diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S
index c7cb9d5f24a3..1b0ec7202dd5 100644
--- a/arch/ppc/kernel/head.S
+++ b/arch/ppc/kernel/head.S
@@ -32,10 +32,6 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 
-#ifdef CONFIG_APUS
-#include <asm/amigappc.h>
-#endif
-
 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
 #define LOAD_BAT(n, reg, RA, RB)        \
         /* see the comment for clear_bats() -- Cort */ \
@@ -128,14 +124,6 @@ __start:
  */
         bl      early_init
 
-#ifdef CONFIG_APUS
-/* On APUS the __va/__pa constants need to be set to the correct
- * values before continuing.
- */
-        mr      r4,r30
-        bl      fix_mem_constants
-#endif /* CONFIG_APUS */
-
 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
  * the physical address we are running at, returned by early_init()
  */
@@ -145,7 +133,7 @@ __after_mmu_off:
         bl      flush_tlbs
 
         bl      initial_bats
-#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
+#ifdef CONFIG_BOOTX_TEXT
         bl      setup_disp_bat
 #endif
 
@@ -161,7 +149,6 @@ __after_mmu_off:
 #endif /* CONFIG_6xx */
 
 
-#ifndef CONFIG_APUS
 /*
  * We need to run with _start at physical address 0.
  * If the MMU is already turned on, we copy stuff to KERNELBASE,
@@ -172,7 +159,7 @@ __after_mmu_off:
         addis   r4,r3,KERNELBASE@h      /* current address of _start */
         cmpwi   0,r4,0                  /* are we already running at 0? */
         bne     relocate_kernel
-#endif /* CONFIG_APUS */
+
 /*
  * we now have the 1st 16M of ram mapped with the bats.
  * prep needs the mmu to be turned on here, but pmac already has it on.
@@ -812,85 +799,6 @@ copy_and_flush:
         addi    r6,r6,4
         blr
 
-#ifdef CONFIG_APUS
-/*
- * On APUS the physical base address of the kernel is not known at compile
- * time, which means the __pa/__va constants used are incorrect. In the
- * __init section is recorded the virtual addresses of instructions using
- * these constants, so all that has to be done is fix these before
- * continuing the kernel boot.
- *
- * r4 = The physical address of the kernel base.
- */
-fix_mem_constants:
-        mr      r10,r4
-        addis   r10,r10,-KERNELBASE@h    /* virt_to_phys constant */
-        neg     r11,r10                  /* phys_to_virt constant */
-
-        lis     r12,__vtop_table_begin@h
-        ori     r12,r12,__vtop_table_begin@l
-        add     r12,r12,r10              /* table begin phys address */
-        lis     r13,__vtop_table_end@h
-        ori     r13,r13,__vtop_table_end@l
-        add     r13,r13,r10              /* table end phys address */
-        subi    r12,r12,4
-        subi    r13,r13,4
-1:      lwzu    r14,4(r12)               /* virt address of instruction */
-        add     r14,r14,r10              /* phys address of instruction */
-        lwz     r15,0(r14)               /* instruction, now insert top */
-        rlwimi  r15,r10,16,16,31         /* half of vp const in low half */
-        stw     r15,0(r14)               /* of instruction and restore. */
-        dcbst   r0,r14                   /* write it to memory */
-        sync
-        icbi    r0,r14                   /* flush the icache line */
-        cmpw    r12,r13
-        bne     1b
-        sync                            /* additional sync needed on g4 */
-        isync
-
-/*
- * Map the memory where the exception handlers will
- * be copied to when hash constants have been patched.
- */
-#ifdef CONFIG_APUS_FAST_EXCEPT
-        lis     r8,0xfff0
-#else
-        lis     r8,0
-#endif
-        ori     r8,r8,0x2               /* 128KB, supervisor */
-        mtspr   SPRN_DBAT3U,r8
-        mtspr   SPRN_DBAT3L,r8
-
-        lis     r12,__ptov_table_begin@h
-        ori     r12,r12,__ptov_table_begin@l
-        add     r12,r12,r10              /* table begin phys address */
-        lis     r13,__ptov_table_end@h
-        ori     r13,r13,__ptov_table_end@l
-        add     r13,r13,r10              /* table end phys address */
-        subi    r12,r12,4
-        subi    r13,r13,4
-1:      lwzu    r14,4(r12)               /* virt address of instruction */
-        add     r14,r14,r10              /* phys address of instruction */
-        lwz     r15,0(r14)               /* instruction, now insert top */
-        rlwimi  r15,r11,16,16,31         /* half of pv const in low half*/
-        stw     r15,0(r14)               /* of instruction and restore. */
-        dcbst   r0,r14                   /* write it to memory */
-        sync
-        icbi    r0,r14                   /* flush the icache line */
-        cmpw    r12,r13
-        bne     1b
-
-        sync                            /* additional sync needed on g4 */
-        isync                           /* No speculative loading until now */
-        blr
-
-/***********************************************************************
- *  Please note that on APUS the exception handlers are located at the
- *  physical address 0xfff0000. For this reason, the exception handlers
- *  cannot use relative branches to access the code below.
- ***********************************************************************/
-#endif /* CONFIG_APUS */
-
 #ifdef CONFIG_SMP
         .globl  __secondary_start_pmac_0
 __secondary_start_pmac_0:
@@ -1043,19 +951,6 @@ start_here:
         bl      machine_init
         bl      MMU_init
 
-#ifdef CONFIG_APUS
-        /* Copy exception code to exception vector base on APUS. */
-        lis     r4,KERNELBASE@h
-#ifdef CONFIG_APUS_FAST_EXCEPT
-        lis     r3,0xfff0               /* Copy to 0xfff00000 */
-#else
-        lis     r3,0                    /* Copy to 0x00000000 */
-#endif
-        li      r5,0x4000               /* # bytes of memory to copy */
-        li      r6,0
-        bl      copy_and_flush          /* copy the first 0x4000 bytes */
-#endif  /* CONFIG_APUS */
-
 /*
  * Go back to running unmapped so we can load up new values
  * for SDR1 (hash table pointer) and the segment registers
@@ -1232,11 +1127,7 @@ initial_bats:
 #else
         ori     r8,r8,2                 /* R/W access */
 #endif /* CONFIG_SMP */
-#ifdef CONFIG_APUS
-        ori     r11,r11,BL_8M<<2|0x2    /* set up 8MB BAT registers for 604 */
-#else
         ori     r11,r11,BL_256M<<2|0x2  /* set up BAT registers for 604 */
-#endif /* CONFIG_APUS */
 
         mtspr   SPRN_DBAT0L,r8          /* N.B. 6xx (not 601) have valid */
         mtspr   SPRN_DBAT0U,r11         /* bit in upper BAT register */
@@ -1245,7 +1136,7 @@ initial_bats:
         isync
         blr
 
-#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
+#ifdef CONFIG_BOOTX_TEXT
 setup_disp_bat:
         /*
          * setup the display bat prepared for us in prom.c
@@ -1268,7 +1159,7 @@ setup_disp_bat:
         mtspr   SPRN_IBAT3U,r11
         blr
 
-#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
+#endif /* defined(CONFIG_BOOTX_TEXT) */
 
 #ifdef CONFIG_8260
 /* Jump into the system reset for the rom.