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-rw-r--r--arch/ppc/boot/common/ns16550.c103
1 files changed, 0 insertions, 103 deletions
diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.c
deleted file mode 100644
index fc5b72041948..000000000000
--- a/arch/ppc/boot/common/ns16550.c
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * COM1 NS16550 support
3 */
4
5#include <linux/types.h>
6#include <linux/serial.h>
7#include <linux/serial_reg.h>
8#include <asm/serial.h>
9
10#if defined(CONFIG_XILINX_VIRTEX)
11#include <platforms/4xx/xparameters/xparameters.h>
12#endif
13#include "nonstdio.h"
14#include "serial.h"
15
16#define SERIAL_BAUD 9600
17
18extern unsigned long ISA_io;
19
20static struct serial_state rs_table[RS_TABLE_SIZE] = {
21 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
22};
23
24static int shift;
25
26unsigned long serial_init(int chan, void *ignored)
27{
28 unsigned long com_port, base_baud;
29 unsigned char lcr, dlm;
30
31 /* We need to find out which type io we're expecting. If it's
32 * 'SERIAL_IO_PORT', we get an offset from the isa_io_base.
33 * If it's 'SERIAL_IO_MEM', we can the exact location. -- Tom */
34 switch (rs_table[chan].io_type) {
35 case SERIAL_IO_PORT:
36 com_port = rs_table[chan].port;
37 break;
38 case SERIAL_IO_MEM:
39 com_port = (unsigned long)rs_table[chan].iomem_base;
40 break;
41 default:
42 /* We can't deal with it. */
43 return -1;
44 }
45
46 /* How far apart the registers are. */
47 shift = rs_table[chan].iomem_reg_shift;
48 /* Base baud.. */
49 base_baud = rs_table[chan].baud_base;
50
51 /* save the LCR */
52 lcr = inb(com_port + (UART_LCR << shift));
53 /* Access baud rate */
54 outb(com_port + (UART_LCR << shift), 0x80);
55 dlm = inb(com_port + (UART_DLM << shift));
56 /*
57 * Test if serial port is unconfigured.
58 * We assume that no-one uses less than 110 baud or
59 * less than 7 bits per character these days.
60 * -- paulus.
61 */
62
63 if ((dlm <= 4) && (lcr & 2))
64 /* port is configured, put the old LCR back */
65 outb(com_port + (UART_LCR << shift), lcr);
66 else {
67 /* Input clock. */
68 outb(com_port + (UART_DLL << shift),
69 (base_baud / SERIAL_BAUD) & 0xFF);
70 outb(com_port + (UART_DLM << shift),
71 (base_baud / SERIAL_BAUD) >> 8);
72 /* 8 data, 1 stop, no parity */
73 outb(com_port + (UART_LCR << shift), 0x03);
74 /* RTS/DTR */
75 outb(com_port + (UART_MCR << shift), 0x03);
76 }
77 /* Clear & enable FIFOs */
78 outb(com_port + (UART_FCR << shift), 0x07);
79
80 return (com_port);
81}
82
83void
84serial_putc(unsigned long com_port, unsigned char c)
85{
86 while ((inb(com_port + (UART_LSR << shift)) & UART_LSR_THRE) == 0)
87 ;
88 outb(com_port, c);
89}
90
91unsigned char
92serial_getc(unsigned long com_port)
93{
94 while ((inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) == 0)
95 ;
96 return inb(com_port);
97}
98
99int
100serial_tstc(unsigned long com_port)
101{
102 return ((inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) != 0);
103}