3 files changed, 52 insertions, 4 deletions

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fc14a38c7ccf..91441d9cbaae 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -256,6 +256,8 @@ struct thread_struct {
         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
         u64             acc;            /* Accumulator */
         unsigned long   spefscr;        /* SPE & eFP status */
+        unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
+                                           call or trap return */
         int             used_spe;       /* set if process has used spe */
 #endif /* CONFIG_SPE */
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -317,7 +319,9 @@ struct thread_struct {
         (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 
 #ifdef CONFIG_SPE
-#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
+#define SPEFSCR_INIT \
+        .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
+        .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 #else
 #define SPEFSCR_INIT
 #endif
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 3386d8ab7eb0..b08c0d03530f 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1175,6 +1175,19 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
         if (val & PR_FP_EXC_SW_ENABLE) {
 #ifdef CONFIG_SPE
                 if (cpu_has_feature(CPU_FTR_SPE)) {
+                        /*
+                         * When the sticky exception bits are set
+                         * directly by userspace, it must call prctl
+                         * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
+                         * in the existing prctl settings) or
+                         * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
+                         * the bits being set).  <fenv.h> functions
+                         * saving and restoring the whole
+                         * floating-point environment need to do so
+                         * anyway to restore the prctl settings from
+                         * the saved environment.
+                         */
+                        tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
                         tsk->thread.fpexc_mode = val &
                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
                         return 0;
@@ -1206,9 +1219,22 @@ int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
 
         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
 #ifdef CONFIG_SPE
-                if (cpu_has_feature(CPU_FTR_SPE))
+                if (cpu_has_feature(CPU_FTR_SPE)) {
+                        /*
+                         * When the sticky exception bits are set
+                         * directly by userspace, it must call prctl
+                         * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
+                         * in the existing prctl settings) or
+                         * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
+                         * the bits being set).  <fenv.h> functions
+                         * saving and restoring the whole
+                         * floating-point environment need to do so
+                         * anyway to restore the prctl settings from
+                         * the saved environment.
+                         */
+                        tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
                         val = tsk->thread.fpexc_mode;
-                else
+                } else
                         return -EINVAL;
 #else
                 return -EINVAL;
diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c
index a73f0884d358..59835c625dc6 100644
--- a/arch/powerpc/math-emu/math_efp.c
+++ b/arch/powerpc/math-emu/math_efp.c
@@ -630,9 +630,27 @@ update_ccr:
         regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
 
 update_regs:
-        __FPU_FPSCR &= ~FP_EX_MASK;
+        /*
+         * If the "invalid" exception sticky bit was set by the
+         * processor for non-finite input, but was not set before the
+         * instruction being emulated, clear it.  Likewise for the
+         * "underflow" bit, which may have been set by the processor
+         * for exact underflow, not just inexact underflow when the
+         * flag should be set for IEEE 754 semantics.  Other sticky
+         * exceptions will only be set by the processor when they are
+         * correct according to IEEE 754 semantics, and we must not
+         * clear sticky bits that were already set before the emulated
+         * instruction as they represent the user-visible sticky
+         * exception status.  "inexact" traps to kernel are not
+         * required for IEEE semantics and are not enabled by default,
+         * so the "inexact" sticky bit may have been set by a previous
+         * instruction without the kernel being aware of it.
+         */
+        __FPU_FPSCR
+          &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;
         __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
         mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
+        current->thread.spefscr_last = __FPU_FPSCR;
 
         current->thread.evr[fc] = vc.wp[0];
         regs->gpr[fc] = vc.wp[1];