4 files changed, 417 insertions, 41 deletions

diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 661df42830b9..4a04823e8423 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/spinlock.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/8xx_immap.h>
@@ -42,6 +43,10 @@
 
 #include <asm/fs_pd.h>
 
+#ifdef CONFIG_8xx_GPIO
+#include <linux/of_gpio.h>
+#endif
+
 #define CPM_MAP_SIZE    (0x4000)
 
 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
@@ -290,20 +295,24 @@ struct cpm_ioport16 {
         __be16 res[3];
 };
 
-struct cpm_ioport32 {
-        __be32 dir, par, sor;
+struct cpm_ioport32b {
+        __be32 dir, par, odr, dat;
+};
+
+struct cpm_ioport32e {
+        __be32 dir, par, sor, odr, dat;
 };
 
 static void cpm1_set_pin32(int port, int pin, int flags)
 {
-        struct cpm_ioport32 __iomem *iop;
+        struct cpm_ioport32e __iomem *iop;
         pin = 1 << (31 - pin);
 
         if (port == CPM_PORTB)
-                iop = (struct cpm_ioport32 __iomem *)
+                iop = (struct cpm_ioport32e __iomem *)
                       &mpc8xx_immr->im_cpm.cp_pbdir;
         else
-                iop = (struct cpm_ioport32 __iomem *)
+                iop = (struct cpm_ioport32e __iomem *)
                       &mpc8xx_immr->im_cpm.cp_pedir;
 
         if (flags & CPM_PIN_OUTPUT)
@@ -498,3 +507,251 @@ int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 
         return 0;
 }
+
+/*
+ * GPIO LIB API implementation
+ */
+#ifdef CONFIG_8xx_GPIO
+
+struct cpm1_gpio16_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u16 cpdata;
+};
+
+static inline struct cpm1_gpio16_chip *
+to_cpm1_gpio16_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
+}
+
+static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+
+        cpm1_gc->cpdata = in_be16(&iop->dat);
+}
+
+static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        return !!(in_be16(&iop->dat) & pin_mask);
+}
+
+static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u16 pin_mask = 1 << (15 - gpio);
+
+        spin_lock_irqsave(&cpm1_gc->lock, flags);
+
+        if (value)
+                cpm1_gc->cpdata |= pin_mask;
+        else
+                cpm1_gc->cpdata &= ~pin_mask;
+
+        out_be16(&iop->dat, cpm1_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm1_gc->lock, flags);
+}
+
+static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        setbits16(&iop->dir, pin_mask);
+
+        cpm1_gpio16_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        clrbits16(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm1_gpiochip_add16(struct device_node *np)
+{
+        struct cpm1_gpio16_chip *cpm1_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
+        if (!cpm1_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm1_gc->lock);
+
+        mm_gc = &cpm1_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm1_gpio16_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 16;
+        gc->direction_input = cpm1_gpio16_dir_in;
+        gc->direction_output = cpm1_gpio16_dir_out;
+        gc->get = cpm1_gpio16_get;
+        gc->set = cpm1_gpio16_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+
+struct cpm1_gpio32_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u32 cpdata;
+};
+
+static inline struct cpm1_gpio32_chip *
+to_cpm1_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
+}
+
+static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+
+        cpm1_gc->cpdata = in_be32(&iop->dat);
+}
+
+static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        return !!(in_be32(&iop->dat) & pin_mask);
+}
+
+static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u32 pin_mask = 1 << (31 - gpio);
+
+        spin_lock_irqsave(&cpm1_gc->lock, flags);
+
+        if (value)
+                cpm1_gc->cpdata |= pin_mask;
+        else
+                cpm1_gc->cpdata &= ~pin_mask;
+
+        out_be32(&iop->dat, cpm1_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm1_gc->lock, flags);
+}
+
+static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        setbits32(&iop->dir, pin_mask);
+
+        cpm1_gpio32_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        clrbits32(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm1_gpiochip_add32(struct device_node *np)
+{
+        struct cpm1_gpio32_chip *cpm1_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
+        if (!cpm1_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm1_gc->lock);
+
+        mm_gc = &cpm1_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm1_gpio32_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 32;
+        gc->direction_input = cpm1_gpio32_dir_in;
+        gc->direction_output = cpm1_gpio32_dir_out;
+        gc->get = cpm1_gpio32_get;
+        gc->set = cpm1_gpio32_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+
+static int cpm_init_par_io(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
+                cpm1_gpiochip_add16(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
+                cpm1_gpiochip_add32(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
+                cpm1_gpiochip_add16(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
+                cpm1_gpiochip_add16(np);
+
+        /* Port E uses CPM2 layout */
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
+                cpm2_gpiochip_add32(np);
+        return 0;
+}
+arch_initcall(cpm_init_par_io);
+
+#endif /* CONFIG_8xx_GPIO */
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 5a6c5dfc53ef..f1c3395633b9 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -115,16 +115,10 @@ EXPORT_SYMBOL(cpm_command);
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK     (get_brgfreq())
-#define BRG_UART_CLK    (BRG_INT_CLK/16)
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-void
-cpm_setbrg(uint brg, uint rate)
+void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
 {
         u32 __iomem *bp;
+        u32 val;
 
         /* This is good enough to get SMCs running.....
         */
@@ -135,34 +129,14 @@ cpm_setbrg(uint brg, uint rate)
                 brg -= 4;
         }
         bp += brg;
-        out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
-
-        cpm2_unmap(bp);
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-void
-cpm2_fastbrg(uint brg, uint rate, int div16)
-{
-        u32 __iomem *bp;
-        u32 val;
-
-        if (brg < 4) {
-                bp = cpm2_map_size(im_brgc1, 16);
-        } else {
-                bp = cpm2_map_size(im_brgc5, 16);
-                brg -= 4;
-        }
-        bp += brg;
-        val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
+        val = (((clk / rate) - 1) << 1) | CPM_BRG_EN | src;
         if (div16)
                 val |= CPM_BRG_DIV16;
 
         out_be32(bp, val);
         cpm2_unmap(bp);
 }
+EXPORT_SYMBOL(__cpm2_setbrg);
 
 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 {
@@ -377,3 +351,14 @@ void cpm2_set_pin(int port, int pin, int flags)
         else
                 clrbits32(&iop[port].odr, pin);
 }
+
+static int cpm_init_par_io(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
+                cpm2_gpiochip_add32(np);
+        return 0;
+}
+arch_initcall(cpm_init_par_io);
+
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index e4b7296acb2c..53da8a079f96 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -19,6 +19,8 @@
 
 #include <linux/init.h>
 #include <linux/of_device.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
 
 #include <asm/udbg.h>
 #include <asm/io.h>
@@ -28,6 +30,10 @@
 
 #include <mm/mmu_decl.h>
 
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+#include <linux/of_gpio.h>
+#endif
+
 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
 static u32 __iomem *cpm_udbg_txdesc =
         (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
@@ -207,3 +213,120 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
         return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
 }
 EXPORT_SYMBOL(cpm_muram_dma);
+
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+        u32 dir, par, sor, odr, dat;
+        u32 res[3];
+};
+
+struct cpm2_gpio32_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u32 cpdata;
+};
+
+static inline struct cpm2_gpio32_chip *
+to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
+}
+
+static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+
+        cpm2_gc->cpdata = in_be32(&iop->dat);
+}
+
+static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        return !!(in_be32(&iop->dat) & pin_mask);
+}
+
+static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u32 pin_mask = 1 << (31 - gpio);
+
+        spin_lock_irqsave(&cpm2_gc->lock, flags);
+
+        if (value)
+                cpm2_gc->cpdata |= pin_mask;
+        else
+                cpm2_gc->cpdata &= ~pin_mask;
+
+        out_be32(&iop->dat, cpm2_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm2_gc->lock, flags);
+}
+
+static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        setbits32(&iop->dir, pin_mask);
+
+        cpm2_gpio32_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        clrbits32(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm2_gpiochip_add32(struct device_node *np)
+{
+        struct cpm2_gpio32_chip *cpm2_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
+        if (!cpm2_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm2_gc->lock);
+
+        mm_gc = &cpm2_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm2_gpio32_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 32;
+        gc->direction_input = cpm2_gpio32_dir_in;
+        gc->direction_output = cpm2_gpio32_dir_out;
+        gc->get = cpm2_gpio32_get;
+        gc->set = cpm2_gpio32_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index c09ddc0dbeb3..c1879ebfd4f4 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -21,6 +21,7 @@ static int  __init add_rtc(void)
         struct device_node *np;
         struct platform_device *pd;
         struct resource res[2];
+        unsigned int num_res = 1;
         int ret;
 
         memset(&res, 0, sizeof(res));
@@ -41,14 +42,24 @@ static int  __init add_rtc(void)
         if (res[0].start != RTC_PORT(0))
                 return -EINVAL;
 
-        /* Use a fixed interrupt value of 8 since on PPC if we are using this
-         * its off an i8259 which we ensure has interrupt numbers 0..15. */
-        res[1].start = 8;
-        res[1].end = 8;
-        res[1].flags = IORESOURCE_IRQ;
+        np = of_find_compatible_node(NULL, NULL, "chrp,iic");
+        if (!np)
+                np = of_find_compatible_node(NULL, NULL, "pnpPNP,000");
+        if (np) {
+                of_node_put(np);
+                /*
+                 * Use a fixed interrupt value of 8 since on PPC if we are
+                 * using this its off an i8259 which we ensure has interrupt
+                 * numbers 0..15.
+                 */
+                res[1].start = 8;
+                res[1].end = 8;
+                res[1].flags = IORESOURCE_IRQ;
+                num_res++;
+        }
 
         pd = platform_device_register_simple("rtc_cmos", -1,
-                                             &res[0], 2);
+                                             &res[0], num_res);
 
         if (IS_ERR(pd))
                 return PTR_ERR(pd);