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-rw-r--r--arch/powerpc/sysdev/cpm2_pic.c2
-rw-r--r--arch/powerpc/sysdev/ipic.c2
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c17
3 files changed, 19 insertions, 2 deletions
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index b16ca3ed65d2..78f1f7cca0a0 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -165,7 +165,7 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
165 edibit = (14 - (src - CPM2_IRQ_EXT1)); 165 edibit = (14 - (src - CPM2_IRQ_EXT1));
166 else 166 else
167 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) 167 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
168 edibit = (31 - (src - CPM2_IRQ_PORTC15)); 168 edibit = (31 - (CPM2_IRQ_PORTC0 - src));
169 else 169 else
170 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; 170 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
171 171
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 88a983ece5c9..9a89cd3e80a2 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -890,7 +890,7 @@ unsigned int ipic_get_irq(void)
890 return irq_linear_revmap(primary_ipic->irqhost, irq); 890 return irq_linear_revmap(primary_ipic->irqhost, irq);
891} 891}
892 892
893#ifdef CONFIG_PM 893#ifdef CONFIG_SUSPEND
894static struct { 894static struct {
895 u32 sicfr; 895 u32 sicfr;
896 u32 siprr[2]; 896 u32 siprr[2];
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 77fae5f64f2e..5558d932b4d5 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -204,6 +204,23 @@ static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
204{ 204{
205 u32 ma, pcila, pciha; 205 u32 ma, pcila, pciha;
206 206
207 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
208 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
209 * address are actually hard wired to a value that appears to depend
210 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
211 *
212 * The trick here is we just crop those top bits and ignore them when
213 * programming the chip. That means the device-tree has to be right
214 * for the specific part used (we don't print a warning if it's wrong
215 * but on the other hand, you'll crash quickly enough), but at least
216 * this code should work whatever the hard coded value is
217 */
218 plb_addr &= 0xffffffffull;
219
220 /* Note: Due to the above hack, the test below doesn't actually test
221 * if you address is above 4G, but it tests that address and
222 * (address + size) are both contained in the same 4G
223 */
207 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || 224 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
208 size < 0x1000 || (plb_addr & (size - 1)) != 0) { 225 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
209 printk(KERN_WARNING "%s: Resource out of range\n", 226 printk(KERN_WARNING "%s: Resource out of range\n",