8 files changed, 275 insertions, 153 deletions

diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index adc66212a419..4bb18f57901e 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -20,3 +20,16 @@ config UCC
         bool
         default y if UCC_FAST || UCC_SLOW
 
+config QE_USB
+        bool
+        help
+          QE USB Host Controller support
+
+config QE_GPIO
+        bool "QE GPIO support"
+        depends on QUICC_ENGINE
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
+        help
+          Say Y here if you're going to use hardware that connects to the
+          QE GPIOs.
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
index 874fe1a5b1cf..f1855c185291 100644
--- a/arch/powerpc/sysdev/qe_lib/Makefile
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_ic.o qe_io.o
 obj-$(CONFIG_UCC)       += ucc.o
 obj-$(CONFIG_UCC_SLOW)  += ucc_slow.o
 obj-$(CONFIG_UCC_FAST)  += ucc_fast.o
+obj-$(CONFIG_QE_USB)    += usb.o
+obj-$(CONFIG_QE_GPIO)   += gpio.o
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
new file mode 100644
index 000000000000..8e5a0bc36d0b
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -0,0 +1,149 @@
+/*
+ * QUICC Engine GPIOs
+ *
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <asm/qe.h>
+
+struct qe_gpio_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u32 cpdata;
+};
+
+static inline struct qe_gpio_chip *
+to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
+}
+
+static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+        struct qe_pio_regs __iomem *regs = mm_gc->regs;
+
+        qe_gc->cpdata = in_be32(&regs->cpdata);
+}
+
+static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct qe_pio_regs __iomem *regs = mm_gc->regs;
+        u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+
+        return in_be32(&regs->cpdata) & pin_mask;
+}
+
+static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+        struct qe_pio_regs __iomem *regs = mm_gc->regs;
+        unsigned long flags;
+        u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        if (val)
+                qe_gc->cpdata |= pin_mask;
+        else
+                qe_gc->cpdata &= ~pin_mask;
+
+        out_be32(&regs->cpdata, qe_gc->cpdata);
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+
+static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+        unsigned long flags;
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+        return 0;
+}
+
+static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+        unsigned long flags;
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+        qe_gpio_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int __init qe_add_gpiochips(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
+                int ret;
+                struct qe_gpio_chip *qe_gc;
+                struct of_mm_gpio_chip *mm_gc;
+                struct of_gpio_chip *of_gc;
+                struct gpio_chip *gc;
+
+                qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
+                if (!qe_gc) {
+                        ret = -ENOMEM;
+                        goto err;
+                }
+
+                spin_lock_init(&qe_gc->lock);
+
+                mm_gc = &qe_gc->mm_gc;
+                of_gc = &mm_gc->of_gc;
+                gc = &of_gc->gc;
+
+                mm_gc->save_regs = qe_gpio_save_regs;
+                of_gc->gpio_cells = 2;
+                gc->ngpio = QE_PIO_PINS;
+                gc->direction_input = qe_gpio_dir_in;
+                gc->direction_output = qe_gpio_dir_out;
+                gc->get = qe_gpio_get;
+                gc->set = qe_gpio_set;
+
+                ret = of_mm_gpiochip_add(np, mm_gc);
+                if (ret)
+                        goto err;
+                continue;
+err:
+                pr_err("%s: registration failed with status %d\n",
+                       np->full_name, ret);
+                kfree(qe_gc);
+                /* try others anyway */
+        }
+        return 0;
+}
+arch_initcall(qe_add_gpiochips);
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index cff550eec7e8..9e82d7e725a5 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -35,7 +35,6 @@
 #include <asm/rheap.h>
 
 static void qe_snums_init(void);
-static void qe_muram_init(void);
 static int qe_sdma_init(void);
 
 static DEFINE_SPINLOCK(qe_lock);
@@ -88,7 +87,7 @@ phys_addr_t get_qe_base(void)
 
 EXPORT_SYMBOL(get_qe_base);
 
-void qe_reset(void)
+void __init qe_reset(void)
 {
         if (qe_immr == NULL)
                 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
@@ -325,97 +324,6 @@ static int qe_sdma_init(void)
         return 0;
 }
 
-/*
- * muram_alloc / muram_free bits.
- */
-static DEFINE_SPINLOCK(qe_muram_lock);
-
-/* 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up... */
-static rh_block_t qe_boot_muram_rh_block[16];
-static rh_info_t qe_muram_info;
-
-static void qe_muram_init(void)
-{
-        struct device_node *np;
-        const u32 *address;
-        u64 size;
-        unsigned int flags;
-
-        /* initialize the info header */
-        rh_init(&qe_muram_info, 1,
-                sizeof(qe_boot_muram_rh_block) /
-                sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
-
-        /* Attach the usable muram area */
-        /* XXX: This is a subset of the available muram. It
-         * varies with the processor and the microcode patches activated.
-         */
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data");
-        if (!np) {
-                np = of_find_node_by_name(NULL, "data-only");
-                if (!np) {
-                        WARN_ON(1);
-                        return;
-                }
-        }
-
-        address = of_get_address(np, 0, &size, &flags);
-        WARN_ON(!address);
-
-        of_node_put(np);
-        if (address)
-                rh_attach_region(&qe_muram_info, *address, (int)size);
-}
-
-/* This function returns an index into the MURAM area.
- */
-unsigned long qe_muram_alloc(int size, int align)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&qe_muram_lock, flags);
-        start = rh_alloc_align(&qe_muram_info, size, align, "QE");
-        spin_unlock_irqrestore(&qe_muram_lock, flags);
-
-        return start;
-}
-EXPORT_SYMBOL(qe_muram_alloc);
-
-int qe_muram_free(unsigned long offset)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&qe_muram_lock, flags);
-        ret = rh_free(&qe_muram_info, offset);
-        spin_unlock_irqrestore(&qe_muram_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(qe_muram_free);
-
-/* not sure if this is ever needed */
-unsigned long qe_muram_alloc_fixed(unsigned long offset, int size)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&qe_muram_lock, flags);
-        start = rh_alloc_fixed(&qe_muram_info, offset, size, "commproc");
-        spin_unlock_irqrestore(&qe_muram_lock, flags);
-
-        return start;
-}
-EXPORT_SYMBOL(qe_muram_alloc_fixed);
-
-void qe_muram_dump(void)
-{
-        rh_dump(&qe_muram_info);
-}
-EXPORT_SYMBOL(qe_muram_dump);
-
 /* The maximum number of RISCs we support */
 #define MAX_QE_RISC     2
 
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index f59444d3be75..63cdf9887f36 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -329,21 +329,19 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
         struct resource res;
         u32 temp = 0, ret, high_active = 0;
 
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret)
+                return;
+
         qe_ic = alloc_bootmem(sizeof(struct qe_ic));
         if (qe_ic == NULL)
                 return;
 
         memset(qe_ic, 0, sizeof(struct qe_ic));
 
-        qe_ic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
+        qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
                                         NR_QE_IC_INTS, &qe_ic_host_ops, 0);
-        if (qe_ic->irqhost == NULL) {
-                of_node_put(node);
-                return;
-        }
-
-        ret = of_address_to_resource(node, 0, &res);
-        if (ret)
+        if (qe_ic->irqhost == NULL)
                 return;
 
         qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index 93916a48afec..7c87460179ef 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -28,21 +28,7 @@
 
 #undef DEBUG
 
-#define NUM_OF_PINS     32
-
-struct port_regs {
-        __be32  cpodr;          /* Open drain register */
-        __be32  cpdata;         /* Data register */
-        __be32  cpdir1;         /* Direction register */
-        __be32  cpdir2;         /* Direction register */
-        __be32  cppar1;         /* Pin assignment register */
-        __be32  cppar2;         /* Pin assignment register */
-#ifdef CONFIG_PPC_85xx
-        u8      pad[8];
-#endif
-};
-
-static struct port_regs __iomem *par_io;
+static struct qe_pio_regs __iomem *par_io;
 static int num_par_io_ports = 0;
 
 int par_io_init(struct device_node *np)
@@ -64,69 +50,79 @@ int par_io_init(struct device_node *np)
         return 0;
 }
 
-int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
-                      int assignment, int has_irq)
+void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
+                         int open_drain, int assignment, int has_irq)
 {
-        u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val;
-
-        if (!par_io)
-                return -1;
+        u32 pin_mask1bit;
+        u32 pin_mask2bits;
+        u32 new_mask2bits;
+        u32 tmp_val;
 
         /* calculate pin location for single and 2 bits information */
-        pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
+        pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
 
         /* Set open drain, if required */
-        tmp_val = in_be32(&par_io[port].cpodr);
+        tmp_val = in_be32(&par_io->cpodr);
         if (open_drain)
-                out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val);
+                out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
         else
-                out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val);
+                out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
 
         /* define direction */
-        tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
-                in_be32(&par_io[port].cpdir2) :
-                in_be32(&par_io[port].cpdir1);
+        tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
+                in_be32(&par_io->cpdir2) :
+                in_be32(&par_io->cpdir1);
 
         /* get all bits mask for 2 bit per port */
-        pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS -
-                                (pin % (NUM_OF_PINS / 2) + 1) * 2));
+        pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
+                                (pin % (QE_PIO_PINS / 2) + 1) * 2));
 
         /* Get the final mask we need for the right definition */
-        new_mask2bits = (u32) (dir << (NUM_OF_PINS -
-                                (pin % (NUM_OF_PINS / 2) + 1) * 2));
+        new_mask2bits = (u32) (dir << (QE_PIO_PINS -
+                                (pin % (QE_PIO_PINS / 2) + 1) * 2));
 
         /* clear and set 2 bits mask */
-        if (pin > (NUM_OF_PINS / 2) - 1) {
-                out_be32(&par_io[port].cpdir2,
+        if (pin > (QE_PIO_PINS / 2) - 1) {
+                out_be32(&par_io->cpdir2,
                          ~pin_mask2bits & tmp_val);
                 tmp_val &= ~pin_mask2bits;
-                out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val);
+                out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
         } else {
-                out_be32(&par_io[port].cpdir1,
+                out_be32(&par_io->cpdir1,
                          ~pin_mask2bits & tmp_val);
                 tmp_val &= ~pin_mask2bits;
-                out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val);
+                out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
         }
         /* define pin assignment */
-        tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
-                in_be32(&par_io[port].cppar2) :
-                in_be32(&par_io[port].cppar1);
+        tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
+                in_be32(&par_io->cppar2) :
+                in_be32(&par_io->cppar1);
 
-        new_mask2bits = (u32) (assignment << (NUM_OF_PINS -
-                        (pin % (NUM_OF_PINS / 2) + 1) * 2));
+        new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
+                        (pin % (QE_PIO_PINS / 2) + 1) * 2));
         /* clear and set 2 bits mask */
-        if (pin > (NUM_OF_PINS / 2) - 1) {
-                out_be32(&par_io[port].cppar2,
+        if (pin > (QE_PIO_PINS / 2) - 1) {
+                out_be32(&par_io->cppar2,
                          ~pin_mask2bits & tmp_val);
                 tmp_val &= ~pin_mask2bits;
-                out_be32(&par_io[port].cppar2, new_mask2bits | tmp_val);
+                out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
         } else {
-                out_be32(&par_io[port].cppar1,
+                out_be32(&par_io->cppar1,
                          ~pin_mask2bits & tmp_val);
                 tmp_val &= ~pin_mask2bits;
-                out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val);
+                out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
         }
+}
+EXPORT_SYMBOL(__par_io_config_pin);
+
+int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+                      int assignment, int has_irq)
+{
+        if (!par_io || port >= num_par_io_ports)
+                return -EINVAL;
 
+        __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment,
+                            has_irq);
         return 0;
 }
 EXPORT_SYMBOL(par_io_config_pin);
@@ -137,10 +133,10 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
 
         if (port >= num_par_io_ports)
                 return -EINVAL;
-        if (pin >= NUM_OF_PINS)
+        if (pin >= QE_PIO_PINS)
                 return -EINVAL;
         /* calculate pin location */
-        pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
+        pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
 
         tmp_val = in_be32(&par_io[port].cpdata);
 
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index 0e348d9af8a6..d3c7f5af9bc8 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -26,7 +26,8 @@
 #include <asm/qe.h>
 #include <asm/ucc.h>
 
-static DEFINE_SPINLOCK(ucc_lock);
+DEFINE_SPINLOCK(cmxgcr_lock);
+EXPORT_SYMBOL(cmxgcr_lock);
 
 int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
 {
@@ -35,10 +36,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
         if (ucc_num > UCC_MAX_NUM - 1)
                 return -EINVAL;
 
-        spin_lock_irqsave(&ucc_lock, flags);
+        spin_lock_irqsave(&cmxgcr_lock, flags);
         clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
                 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
-        spin_unlock_irqrestore(&ucc_lock, flags);
+        spin_unlock_irqrestore(&cmxgcr_lock, flags);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/qe_lib/usb.c b/arch/powerpc/sysdev/qe_lib/usb.c
new file mode 100644
index 000000000000..8105462078eb
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/usb.c
@@ -0,0 +1,55 @@
+/*
+ * QE USB routines
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ *               Shlomi Gridish <gridish@freescale.com>
+ *               Jerry Huang <Chang-Ming.Huang@freescale.com>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *               Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+int qe_usb_clock_set(enum qe_clock clk, int rate)
+{
+        struct qe_mux __iomem *mux = &qe_immr->qmx;
+        unsigned long flags;
+        u32 val;
+
+        switch (clk) {
+        case QE_CLK3:  val = QE_CMXGCR_USBCS_CLK3;  break;
+        case QE_CLK5:  val = QE_CMXGCR_USBCS_CLK5;  break;
+        case QE_CLK7:  val = QE_CMXGCR_USBCS_CLK7;  break;
+        case QE_CLK9:  val = QE_CMXGCR_USBCS_CLK9;  break;
+        case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
+        case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
+        case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
+        case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
+        case QE_BRG9:  val = QE_CMXGCR_USBCS_BRG9;  break;
+        case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
+        default:
+                pr_err("%s: requested unknown clock %d\n", __func__, clk);
+                return -EINVAL;
+        }
+
+        if (qe_clock_is_brg(clk))
+                qe_setbrg(clk, rate, 1);
+
+        spin_lock_irqsave(&cmxgcr_lock, flags);
+
+        clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+
+        spin_unlock_irqrestore(&cmxgcr_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(qe_usb_clock_set);