1 files changed, 91 insertions, 31 deletions

diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 2b69084d0f0c..fb4963abdf55 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -1,5 +1,5 @@
 /*
- * GPIOs on MPC8349/8572/8610 and compatible
+ * GPIOs on MPC512x/8349/8572/8610 and compatible
  *
  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
  *
@@ -26,6 +26,7 @@
 #define GPIO_IER                0x0c
 #define GPIO_IMR                0x10
 #define GPIO_ICR                0x14
+#define GPIO_ICR2               0x18
 
 struct mpc8xxx_gpio_chip {
         struct of_mm_gpio_chip mm_gc;
@@ -37,6 +38,7 @@ struct mpc8xxx_gpio_chip {
          */
         u32 data;
         struct irq_host *irq;
+        void *of_dev_id_data;
 };
 
 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
@@ -143,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 
 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
         unsigned int mask;
 
@@ -153,43 +155,43 @@ static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
                                                      32 - ffs(mask)));
 }
 
-static void mpc8xxx_irq_unmask(unsigned int virq)
+static void mpc8xxx_irq_unmask(struct irq_data *d)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
         unsigned long flags;
 
         spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 
-        setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+        setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 
         spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 }
 
-static void mpc8xxx_irq_mask(unsigned int virq)
+static void mpc8xxx_irq_mask(struct irq_data *d)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
         unsigned long flags;
 
         spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 
-        clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+        clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 
         spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 }
 
-static void mpc8xxx_irq_ack(unsigned int virq)
+static void mpc8xxx_irq_ack(struct irq_data *d)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 
-        out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq)));
+        out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 }
 
-static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
+static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
         unsigned long flags;
 
@@ -197,14 +199,59 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
         case IRQ_TYPE_EDGE_FALLING:
                 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
                 setbits32(mm->regs + GPIO_ICR,
-                          mpc8xxx_gpio2mask(virq_to_hw(virq)));
+                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
                 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
                 break;
 
         case IRQ_TYPE_EDGE_BOTH:
                 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
                 clrbits32(mm->regs + GPIO_ICR,
-                          mpc8xxx_gpio2mask(virq_to_hw(virq)));
+                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long gpio = irqd_to_hwirq(d);
+        void __iomem *reg;
+        unsigned int shift;
+        unsigned long flags;
+
+        if (gpio < 16) {
+                reg = mm->regs + GPIO_ICR;
+                shift = (15 - gpio) * 2;
+        } else {
+                reg = mm->regs + GPIO_ICR2;
+                shift = (15 - (gpio % 16)) * 2;
+        }
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_LEVEL_LOW:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 2 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_LEVEL_HIGH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 1 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrbits32(reg, 3 << shift);
                 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
                 break;
 
@@ -217,18 +264,23 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
 
 static struct irq_chip mpc8xxx_irq_chip = {
         .name           = "mpc8xxx-gpio",
-        .unmask         = mpc8xxx_irq_unmask,
-        .mask           = mpc8xxx_irq_mask,
-        .ack            = mpc8xxx_irq_ack,
-        .set_type       = mpc8xxx_irq_set_type,
+        .irq_unmask     = mpc8xxx_irq_unmask,
+        .irq_mask       = mpc8xxx_irq_mask,
+        .irq_ack        = mpc8xxx_irq_ack,
+        .irq_set_type   = mpc8xxx_irq_set_type,
 };
 
 static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
                                 irq_hw_number_t hw)
 {
-        set_irq_chip_data(virq, h->host_data);
-        set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
+
+        if (mpc8xxx_gc->of_dev_id_data)
+                mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
+
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         return 0;
 }
@@ -253,11 +305,21 @@ static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
         .xlate  = mpc8xxx_gpio_irq_xlate,
 };
 
+static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
+        { .compatible = "fsl,mpc8349-gpio", },
+        { .compatible = "fsl,mpc8572-gpio", },
+        { .compatible = "fsl,mpc8610-gpio", },
+        { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
+        { .compatible = "fsl,qoriq-gpio",   },
+        {}
+};
+
 static void __init mpc8xxx_add_controller(struct device_node *np)
 {
         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
         struct of_mm_gpio_chip *mm_gc;
         struct gpio_chip *gc;
+        const struct of_device_id *id;
         unsigned hwirq;
         int ret;
 
@@ -297,14 +359,18 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         if (!mpc8xxx_gc->irq)
                 goto skip_irq;
 
+        id = of_match_node(mpc8xxx_gpio_ids, np);
+        if (id)
+                mpc8xxx_gc->of_dev_id_data = id->data;
+
         mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
 
         /* ack and mask all irqs */
         out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
         out_be32(mm_gc->regs + GPIO_IMR, 0);
 
-        set_irq_data(hwirq, mpc8xxx_gc);
-        set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
+        irq_set_handler_data(hwirq, mpc8xxx_gc);
+        irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
 
 skip_irq:
         return;
@@ -321,13 +387,7 @@ static int __init mpc8xxx_add_gpiochips(void)
 {
         struct device_node *np;
 
-        for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
-                mpc8xxx_add_controller(np);
-
-        for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
-                mpc8xxx_add_controller(np);
-
-        for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
+        for_each_matching_node(np, mpc8xxx_gpio_ids)
                 mpc8xxx_add_controller(np);
 
         return 0;