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-rw-r--r--arch/powerpc/sysdev/fsl_rio.c1519
1 files changed, 271 insertions, 1248 deletions
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 22ffccd8bef5..a4c4f4a932d8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
10 * - Added Port-Write message handling 10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling 11 * - Added Machine Check exception handling
12 * 12 *
13 * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com> 14 * Zhang Wei <wei.zhang@freescale.com>
15 * 15 *
16 * Copyright 2005 MontaVista Software, Inc. 16 * Copyright 2005 MontaVista Software, Inc.
@@ -28,240 +28,33 @@
28#include <linux/dma-mapping.h> 28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/rio.h>
32#include <linux/rio_drv.h>
33#include <linux/of_platform.h> 31#include <linux/of_platform.h>
34#include <linux/delay.h> 32#include <linux/delay.h>
35#include <linux/slab.h> 33#include <linux/slab.h>
36#include <linux/kfifo.h>
37 34
38#include <asm/io.h> 35#include <linux/io.h>
36#include <linux/uaccess.h>
39#include <asm/machdep.h> 37#include <asm/machdep.h>
40#include <asm/uaccess.h>
41 38
42#undef DEBUG_PW /* Port-Write debugging */ 39#include "fsl_rio.h"
43 40
44/* RapidIO definition irq, which read from OF-tree */ 41#undef DEBUG_PW /* Port-Write debugging */
45#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
49
50#define IPWSR_CLEAR 0x98
51#define OMSR_CLEAR 0x1cb3
52#define IMSR_CLEAR 0x491
53#define IDSR_CLEAR 0x91
54#define ODSR_CLEAR 0x1c00
55#define LTLEECSR_ENABLE_ALL 0xFFC000FC
56#define ESCSR_CLEAR 0x07120204
57#define IECSR_CLEAR 0x80000000
58 42
59#define RIO_PORT1_EDCSR 0x0640 43#define RIO_PORT1_EDCSR 0x0640
60#define RIO_PORT2_EDCSR 0x0680 44#define RIO_PORT2_EDCSR 0x0680
61#define RIO_PORT1_IECSR 0x10130 45#define RIO_PORT1_IECSR 0x10130
62#define RIO_PORT2_IECSR 0x101B0 46#define RIO_PORT2_IECSR 0x101B0
63#define RIO_IM0SR 0x13064 47
64#define RIO_IM1SR 0x13164
65#define RIO_OM0SR 0x13004
66#define RIO_OM1SR 0x13104
67
68#define RIO_ATMU_REGS_OFFSET 0x10c00
69#define RIO_P_MSG_REGS_OFFSET 0x11000
70#define RIO_S_MSG_REGS_OFFSET 0x13000
71#define RIO_GCCSR 0x13c 48#define RIO_GCCSR 0x13c
72#define RIO_ESCSR 0x158 49#define RIO_ESCSR 0x158
50#define ESCSR_CLEAR 0x07120204
73#define RIO_PORT2_ESCSR 0x178 51#define RIO_PORT2_ESCSR 0x178
74#define RIO_CCSR 0x15c 52#define RIO_CCSR 0x15c
75#define RIO_LTLEDCSR 0x0608
76#define RIO_LTLEDCSR_IER 0x80000000 53#define RIO_LTLEDCSR_IER 0x80000000
77#define RIO_LTLEDCSR_PRT 0x01000000 54#define RIO_LTLEDCSR_PRT 0x01000000
78#define RIO_LTLEECSR 0x060c 55#define IECSR_CLEAR 0x80000000
79#define RIO_EPWISR 0x10010
80#define RIO_ISR_AACR 0x10120 56#define RIO_ISR_AACR 0x10120
81#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 57#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
82#define RIO_MAINT_WIN_SIZE 0x400000
83#define RIO_DBELL_WIN_SIZE 0x1000
84
85#define RIO_MSG_OMR_MUI 0x00000002
86#define RIO_MSG_OSR_TE 0x00000080
87#define RIO_MSG_OSR_QOI 0x00000020
88#define RIO_MSG_OSR_QFI 0x00000010
89#define RIO_MSG_OSR_MUB 0x00000004
90#define RIO_MSG_OSR_EOMI 0x00000002
91#define RIO_MSG_OSR_QEI 0x00000001
92
93#define RIO_MSG_IMR_MI 0x00000002
94#define RIO_MSG_ISR_TE 0x00000080
95#define RIO_MSG_ISR_QFI 0x00000010
96#define RIO_MSG_ISR_DIQI 0x00000001
97
98#define RIO_IPWMR_SEN 0x00100000
99#define RIO_IPWMR_QFIE 0x00000100
100#define RIO_IPWMR_EIE 0x00000020
101#define RIO_IPWMR_CQ 0x00000002
102#define RIO_IPWMR_PWE 0x00000001
103
104#define RIO_IPWSR_QF 0x00100000
105#define RIO_IPWSR_TE 0x00000080
106#define RIO_IPWSR_QFI 0x00000010
107#define RIO_IPWSR_PWD 0x00000008
108#define RIO_IPWSR_PWB 0x00000004
109
110/* EPWISR Error match value */
111#define RIO_EPWISR_PINT1 0x80000000
112#define RIO_EPWISR_PINT2 0x40000000
113#define RIO_EPWISR_MU 0x00000002
114#define RIO_EPWISR_PW 0x00000001
115
116#define RIO_MSG_DESC_SIZE 32
117#define RIO_MSG_BUFFER_SIZE 4096
118#define RIO_MIN_TX_RING_SIZE 2
119#define RIO_MAX_TX_RING_SIZE 2048
120#define RIO_MIN_RX_RING_SIZE 2
121#define RIO_MAX_RX_RING_SIZE 2048
122
123#define DOORBELL_DMR_DI 0x00000002
124#define DOORBELL_DSR_TE 0x00000080
125#define DOORBELL_DSR_QFI 0x00000010
126#define DOORBELL_DSR_DIQI 0x00000001
127#define DOORBELL_TID_OFFSET 0x02
128#define DOORBELL_SID_OFFSET 0x04
129#define DOORBELL_INFO_OFFSET 0x06
130
131#define DOORBELL_MESSAGE_SIZE 0x08
132#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
133#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
134#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
135
136struct rio_atmu_regs {
137 u32 rowtar;
138 u32 rowtear;
139 u32 rowbar;
140 u32 pad2;
141 u32 rowar;
142 u32 pad3[3];
143};
144
145struct rio_msg_regs {
146 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
147 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
148 u32 pad1;
149 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
150 dequeue pointer address register */
151 u32 pad2;
152 u32 osar; /* 0xD_3014 - Outbound message 0 source address
153 register */
154 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
155 register */
156 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
157 Register*/
158 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
159 register */
160 u32 pad3;
161 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
162 enqueue pointer address register */
163 u32 pad4[13];
164 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
165 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
166 u32 pad5;
167 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
168 pointer address register*/
169 u32 pad6;
170 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
171 pointer address register */
172 u32 pad7[226];
173 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
174 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
175 u32 res0[4];
176 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
177 register */
178 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
179 register */
180 u32 res1[3];
181 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
182 configuration register */
183 u32 res2[12];
184 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
185 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
186 u32 pad8;
187 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
188 address register */
189 u32 pad9;
190 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
191 address register */
192 u32 pad10[26];
193 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
194 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
195 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
196 register */
197 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
198 register */
199};
200
201struct rio_tx_desc {
202 u32 res1;
203 u32 saddr;
204 u32 dport;
205 u32 dattr;
206 u32 res2;
207 u32 res3;
208 u32 dwcnt;
209 u32 res4;
210};
211
212struct rio_dbell_ring {
213 void *virt;
214 dma_addr_t phys;
215};
216
217struct rio_msg_tx_ring {
218 void *virt;
219 dma_addr_t phys;
220 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
221 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
222 int tx_slot;
223 int size;
224 void *dev_id;
225};
226
227struct rio_msg_rx_ring {
228 void *virt;
229 dma_addr_t phys;
230 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
231 int rx_slot;
232 int size;
233 void *dev_id;
234};
235
236struct rio_port_write_msg {
237 void *virt;
238 dma_addr_t phys;
239 u32 msg_count;
240 u32 err_count;
241 u32 discard_count;
242};
243
244struct rio_priv {
245 struct device *dev;
246 void __iomem *regs_win;
247 struct rio_atmu_regs __iomem *atmu_regs;
248 struct rio_atmu_regs __iomem *maint_atmu_regs;
249 struct rio_atmu_regs __iomem *dbell_atmu_regs;
250 void __iomem *dbell_win;
251 void __iomem *maint_win;
252 struct rio_msg_regs __iomem *msg_regs;
253 struct rio_dbell_ring dbell_ring;
254 struct rio_msg_tx_ring msg_tx_ring;
255 struct rio_msg_rx_ring msg_rx_ring;
256 struct rio_port_write_msg port_write_msg;
257 int bellirq;
258 int txirq;
259 int rxirq;
260 int pwirq;
261 struct work_struct pw_work;
262 struct kfifo pw_fifo;
263 spinlock_t pw_fifo_lock;
264};
265 58
266#define __fsl_read_rio_config(x, addr, err, op) \ 59#define __fsl_read_rio_config(x, addr, err, op) \
267 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
@@ -279,7 +72,12 @@ struct rio_priv {
279 : "=r" (err), "=r" (x) \ 72 : "=r" (err), "=r" (x) \
280 : "b" (addr), "i" (-EFAULT), "0" (err)) 73 : "b" (addr), "i" (-EFAULT), "0" (err))
281 74
282static void __iomem *rio_regs_win; 75void __iomem *rio_regs_win;
76void __iomem *rmu_regs_win;
77resource_size_t rio_law_start;
78
79struct fsl_rio_dbell *dbell;
80struct fsl_rio_pw *pw;
283 81
284#ifdef CONFIG_E500 82#ifdef CONFIG_E500
285int fsl_rio_mcheck_exception(struct pt_regs *regs) 83int fsl_rio_mcheck_exception(struct pt_regs *regs)
@@ -311,42 +109,6 @@ EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
311#endif 109#endif
312 110
313/** 111/**
314 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
315 * @mport: RapidIO master port info
316 * @index: ID of RapidIO interface
317 * @destid: Destination ID of target device
318 * @data: 16-bit info field of RapidIO doorbell message
319 *
320 * Sends a MPC85xx doorbell message. Returns %0 on success or
321 * %-EINVAL on failure.
322 */
323static int fsl_rio_doorbell_send(struct rio_mport *mport,
324 int index, u16 destid, u16 data)
325{
326 struct rio_priv *priv = mport->priv;
327 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
328 index, destid, data);
329 switch (mport->phy_type) {
330 case RIO_PHY_PARALLEL:
331 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
332 out_be16(priv->dbell_win, data);
333 break;
334 case RIO_PHY_SERIAL:
335 /* In the serial version silicons, such as MPC8548, MPC8641,
336 * below operations is must be.
337 */
338 out_be32(&priv->msg_regs->odmr, 0x00000000);
339 out_be32(&priv->msg_regs->odretcr, 0x00000004);
340 out_be32(&priv->msg_regs->oddpr, destid << 16);
341 out_be32(&priv->msg_regs->oddatr, data);
342 out_be32(&priv->msg_regs->odmr, 0x00000001);
343 break;
344 }
345
346 return 0;
347}
348
349/**
350 * fsl_local_config_read - Generate a MPC85xx local config space read 112 * fsl_local_config_read - Generate a MPC85xx local config space read
351 * @mport: RapidIO master port info 113 * @mport: RapidIO master port info
352 * @index: ID of RapdiIO interface 114 * @index: ID of RapdiIO interface
@@ -384,8 +146,8 @@ static int fsl_local_config_write(struct rio_mport *mport,
384{ 146{
385 struct rio_priv *priv = mport->priv; 147 struct rio_priv *priv = mport->priv;
386 pr_debug 148 pr_debug
387 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 149 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
388 index, offset, data); 150 index, offset, data);
389 out_be32(priv->regs_win + offset, data); 151 out_be32(priv->regs_win + offset, data);
390 152
391 return 0; 153 return 0;
@@ -413,8 +175,9 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
413 u32 rval, err = 0; 175 u32 rval, err = 0;
414 176
415 pr_debug 177 pr_debug
416 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 178 ("fsl_rio_config_read:"
417 index, destid, hopcount, offset, len); 179 " index %d destid %d hopcount %d offset %8.8x len %d\n",
180 index, destid, hopcount, offset, len);
418 181
419 /* 16MB maintenance window possible */ 182 /* 16MB maintenance window possible */
420 /* allow only aligned access to maintenance registers */ 183 /* allow only aligned access to maintenance registers */
@@ -423,7 +186,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
423 186
424 out_be32(&priv->maint_atmu_regs->rowtar, 187 out_be32(&priv->maint_atmu_regs->rowtar,
425 (destid << 22) | (hopcount << 12) | (offset >> 12)); 188 (destid << 22) | (hopcount << 12) | (offset >> 12));
426 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 189 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
427 190
428 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 191 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
429 switch (len) { 192 switch (len) {
@@ -470,8 +233,9 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
470 struct rio_priv *priv = mport->priv; 233 struct rio_priv *priv = mport->priv;
471 u8 *data; 234 u8 *data;
472 pr_debug 235 pr_debug
473 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 236 ("fsl_rio_config_write:"
474 index, destid, hopcount, offset, len, val); 237 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
238 index, destid, hopcount, offset, len, val);
475 239
476 /* 16MB maintenance windows possible */ 240 /* 16MB maintenance windows possible */
477 /* allow only aligned access to maintenance registers */ 241 /* allow only aligned access to maintenance registers */
@@ -480,7 +244,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
480 244
481 out_be32(&priv->maint_atmu_regs->rowtar, 245 out_be32(&priv->maint_atmu_regs->rowtar,
482 (destid << 22) | (hopcount << 12) | (offset >> 12)); 246 (destid << 22) | (hopcount << 12) | (offset >> 12));
483 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 247 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
484 248
485 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 249 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
486 switch (len) { 250 switch (len) {
@@ -500,590 +264,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
500 return 0; 264 return 0;
501} 265}
502 266
503/** 267void fsl_rio_port_error_handler(int offset)
504 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
505 * @mport: Master port with outbound message queue
506 * @rdev: Target of outbound message
507 * @mbox: Outbound mailbox
508 * @buffer: Message to add to outbound queue
509 * @len: Length of message
510 *
511 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
512 * %0 on success or %-EINVAL on failure.
513 */
514static int
515fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
516 void *buffer, size_t len)
517{
518 struct rio_priv *priv = mport->priv;
519 u32 omr;
520 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
521 + priv->msg_tx_ring.tx_slot;
522 int ret = 0;
523
524 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
525 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
526
527 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
528 ret = -EINVAL;
529 goto out;
530 }
531
532 /* Copy and clear rest of buffer */
533 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
534 len);
535 if (len < (RIO_MAX_MSG_SIZE - 4))
536 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
537 + len, 0, RIO_MAX_MSG_SIZE - len);
538
539 switch (mport->phy_type) {
540 case RIO_PHY_PARALLEL:
541 /* Set mbox field for message */
542 desc->dport = mbox & 0x3;
543
544 /* Enable EOMI interrupt, set priority, and set destid */
545 desc->dattr = 0x28000000 | (rdev->destid << 2);
546 break;
547 case RIO_PHY_SERIAL:
548 /* Set mbox field for message, and set destid */
549 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
550
551 /* Enable EOMI interrupt and priority */
552 desc->dattr = 0x28000000;
553 break;
554 }
555
556 /* Set transfer size aligned to next power of 2 (in double words) */
557 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
558
559 /* Set snooping and source buffer address */
560 desc->saddr = 0x00000004
561 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
562
563 /* Increment enqueue pointer */
564 omr = in_be32(&priv->msg_regs->omr);
565 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
566
567 /* Go to next descriptor */
568 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
569 priv->msg_tx_ring.tx_slot = 0;
570
571 out:
572 return ret;
573}
574
575/**
576 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
577 * @irq: Linux interrupt number
578 * @dev_instance: Pointer to interrupt-specific data
579 *
580 * Handles outbound message interrupts. Executes a register outbound
581 * mailbox event handler and acks the interrupt occurrence.
582 */
583static irqreturn_t
584fsl_rio_tx_handler(int irq, void *dev_instance)
585{
586 int osr;
587 struct rio_mport *port = (struct rio_mport *)dev_instance;
588 struct rio_priv *priv = port->priv;
589
590 osr = in_be32(&priv->msg_regs->osr);
591
592 if (osr & RIO_MSG_OSR_TE) {
593 pr_info("RIO: outbound message transmission error\n");
594 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
595 goto out;
596 }
597
598 if (osr & RIO_MSG_OSR_QOI) {
599 pr_info("RIO: outbound message queue overflow\n");
600 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
601 goto out;
602 }
603
604 if (osr & RIO_MSG_OSR_EOMI) {
605 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
606 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
607 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
608 slot);
609
610 /* Ack the end-of-message interrupt */
611 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
612 }
613
614 out:
615 return IRQ_HANDLED;
616}
617
618/**
619 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
620 * @mport: Master port implementing the outbound message unit
621 * @dev_id: Device specific pointer to pass on event
622 * @mbox: Mailbox to open
623 * @entries: Number of entries in the outbound mailbox ring
624 *
625 * Initializes buffer ring, request the outbound message interrupt,
626 * and enables the outbound message unit. Returns %0 on success and
627 * %-EINVAL or %-ENOMEM on failure.
628 */
629static int
630fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
631{
632 int i, j, rc = 0;
633 struct rio_priv *priv = mport->priv;
634
635 if ((entries < RIO_MIN_TX_RING_SIZE) ||
636 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
637 rc = -EINVAL;
638 goto out;
639 }
640
641 /* Initialize shadow copy ring */
642 priv->msg_tx_ring.dev_id = dev_id;
643 priv->msg_tx_ring.size = entries;
644
645 for (i = 0; i < priv->msg_tx_ring.size; i++) {
646 priv->msg_tx_ring.virt_buffer[i] =
647 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
648 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
649 if (!priv->msg_tx_ring.virt_buffer[i]) {
650 rc = -ENOMEM;
651 for (j = 0; j < priv->msg_tx_ring.size; j++)
652 if (priv->msg_tx_ring.virt_buffer[j])
653 dma_free_coherent(priv->dev,
654 RIO_MSG_BUFFER_SIZE,
655 priv->msg_tx_ring.
656 virt_buffer[j],
657 priv->msg_tx_ring.
658 phys_buffer[j]);
659 goto out;
660 }
661 }
662
663 /* Initialize outbound message descriptor ring */
664 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
665 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
666 &priv->msg_tx_ring.phys, GFP_KERNEL);
667 if (!priv->msg_tx_ring.virt) {
668 rc = -ENOMEM;
669 goto out_dma;
670 }
671 memset(priv->msg_tx_ring.virt, 0,
672 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
673 priv->msg_tx_ring.tx_slot = 0;
674
675 /* Point dequeue/enqueue pointers at first entry in ring */
676 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
677 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
678
679 /* Configure for snooping */
680 out_be32(&priv->msg_regs->osar, 0x00000004);
681
682 /* Clear interrupt status */
683 out_be32(&priv->msg_regs->osr, 0x000000b3);
684
685 /* Hook up outbound message handler */
686 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
687 "msg_tx", (void *)mport);
688 if (rc < 0)
689 goto out_irq;
690
691 /*
692 * Configure outbound message unit
693 * Snooping
694 * Interrupts (all enabled, except QEIE)
695 * Chaining mode
696 * Disable
697 */
698 out_be32(&priv->msg_regs->omr, 0x00100220);
699
700 /* Set number of entries */
701 out_be32(&priv->msg_regs->omr,
702 in_be32(&priv->msg_regs->omr) |
703 ((get_bitmask_order(entries) - 2) << 12));
704
705 /* Now enable the unit */
706 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
707
708 out:
709 return rc;
710
711 out_irq:
712 dma_free_coherent(priv->dev,
713 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
714 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
715
716 out_dma:
717 for (i = 0; i < priv->msg_tx_ring.size; i++)
718 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
719 priv->msg_tx_ring.virt_buffer[i],
720 priv->msg_tx_ring.phys_buffer[i]);
721
722 return rc;
723}
724
725/**
726 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
727 * @mport: Master port implementing the outbound message unit
728 * @mbox: Mailbox to close
729 *
730 * Disables the outbound message unit, free all buffers, and
731 * frees the outbound message interrupt.
732 */
733static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
734{
735 struct rio_priv *priv = mport->priv;
736 /* Disable inbound message unit */
737 out_be32(&priv->msg_regs->omr, 0);
738
739 /* Free ring */
740 dma_free_coherent(priv->dev,
741 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
742 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
743
744 /* Free interrupt */
745 free_irq(IRQ_RIO_TX(mport), (void *)mport);
746}
747
748/**
749 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
750 * @irq: Linux interrupt number
751 * @dev_instance: Pointer to interrupt-specific data
752 *
753 * Handles inbound message interrupts. Executes a registered inbound
754 * mailbox event handler and acks the interrupt occurrence.
755 */
756static irqreturn_t
757fsl_rio_rx_handler(int irq, void *dev_instance)
758{
759 int isr;
760 struct rio_mport *port = (struct rio_mport *)dev_instance;
761 struct rio_priv *priv = port->priv;
762
763 isr = in_be32(&priv->msg_regs->isr);
764
765 if (isr & RIO_MSG_ISR_TE) {
766 pr_info("RIO: inbound message reception error\n");
767 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
768 goto out;
769 }
770
771 /* XXX Need to check/dispatch until queue empty */
772 if (isr & RIO_MSG_ISR_DIQI) {
773 /*
774 * We implement *only* mailbox 0, but can receive messages
775 * for any mailbox/letter to that mailbox destination. So,
776 * make the callback with an unknown/invalid mailbox number
777 * argument.
778 */
779 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
780
781 /* Ack the queueing interrupt */
782 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
783 }
784
785 out:
786 return IRQ_HANDLED;
787}
788
789/**
790 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
791 * @mport: Master port implementing the inbound message unit
792 * @dev_id: Device specific pointer to pass on event
793 * @mbox: Mailbox to open
794 * @entries: Number of entries in the inbound mailbox ring
795 *
796 * Initializes buffer ring, request the inbound message interrupt,
797 * and enables the inbound message unit. Returns %0 on success
798 * and %-EINVAL or %-ENOMEM on failure.
799 */
800static int
801fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
802{
803 int i, rc = 0;
804 struct rio_priv *priv = mport->priv;
805
806 if ((entries < RIO_MIN_RX_RING_SIZE) ||
807 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
808 rc = -EINVAL;
809 goto out;
810 }
811
812 /* Initialize client buffer ring */
813 priv->msg_rx_ring.dev_id = dev_id;
814 priv->msg_rx_ring.size = entries;
815 priv->msg_rx_ring.rx_slot = 0;
816 for (i = 0; i < priv->msg_rx_ring.size; i++)
817 priv->msg_rx_ring.virt_buffer[i] = NULL;
818
819 /* Initialize inbound message ring */
820 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
821 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
822 &priv->msg_rx_ring.phys, GFP_KERNEL);
823 if (!priv->msg_rx_ring.virt) {
824 rc = -ENOMEM;
825 goto out;
826 }
827
828 /* Point dequeue/enqueue pointers at first entry in ring */
829 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
830 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
831
832 /* Clear interrupt status */
833 out_be32(&priv->msg_regs->isr, 0x00000091);
834
835 /* Hook up inbound message handler */
836 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
837 "msg_rx", (void *)mport);
838 if (rc < 0) {
839 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
840 priv->msg_tx_ring.virt_buffer[i],
841 priv->msg_tx_ring.phys_buffer[i]);
842 goto out;
843 }
844
845 /*
846 * Configure inbound message unit:
847 * Snooping
848 * 4KB max message size
849 * Unmask all interrupt sources
850 * Disable
851 */
852 out_be32(&priv->msg_regs->imr, 0x001b0060);
853
854 /* Set number of queue entries */
855 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
856
857 /* Now enable the unit */
858 setbits32(&priv->msg_regs->imr, 0x1);
859
860 out:
861 return rc;
862}
863
864/**
865 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
866 * @mport: Master port implementing the inbound message unit
867 * @mbox: Mailbox to close
868 *
869 * Disables the inbound message unit, free all buffers, and
870 * frees the inbound message interrupt.
871 */
872static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
873{
874 struct rio_priv *priv = mport->priv;
875 /* Disable inbound message unit */
876 out_be32(&priv->msg_regs->imr, 0);
877
878 /* Free ring */
879 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
880 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
881
882 /* Free interrupt */
883 free_irq(IRQ_RIO_RX(mport), (void *)mport);
884}
885
886/**
887 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
888 * @mport: Master port implementing the inbound message unit
889 * @mbox: Inbound mailbox number
890 * @buf: Buffer to add to inbound queue
891 *
892 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
893 * %0 on success or %-EINVAL on failure.
894 */
895static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
896{
897 int rc = 0;
898 struct rio_priv *priv = mport->priv;
899
900 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
901 priv->msg_rx_ring.rx_slot);
902
903 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
904 printk(KERN_ERR
905 "RIO: error adding inbound buffer %d, buffer exists\n",
906 priv->msg_rx_ring.rx_slot);
907 rc = -EINVAL;
908 goto out;
909 }
910
911 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
912 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
913 priv->msg_rx_ring.rx_slot = 0;
914
915 out:
916 return rc;
917}
918
919/**
920 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
921 * @mport: Master port implementing the inbound message unit
922 * @mbox: Inbound mailbox number
923 *
924 * Gets the next available inbound message from the inbound message queue.
925 * A pointer to the message is returned on success or NULL on failure.
926 */
927static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
928{
929 struct rio_priv *priv = mport->priv;
930 u32 phys_buf, virt_buf;
931 void *buf = NULL;
932 int buf_idx;
933
934 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
935
936 /* If no more messages, then bail out */
937 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
938 goto out2;
939
940 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
941 - priv->msg_rx_ring.phys);
942 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
943 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
944
945 if (!buf) {
946 printk(KERN_ERR
947 "RIO: inbound message copy failed, no buffers\n");
948 goto out1;
949 }
950
951 /* Copy max message size, caller is expected to allocate that big */
952 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
953
954 /* Clear the available buffer */
955 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
956
957 out1:
958 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
959
960 out2:
961 return buf;
962}
963
964/**
965 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
966 * @irq: Linux interrupt number
967 * @dev_instance: Pointer to interrupt-specific data
968 *
969 * Handles doorbell interrupts. Parses a list of registered
970 * doorbell event handlers and executes a matching event handler.
971 */
972static irqreturn_t
973fsl_rio_dbell_handler(int irq, void *dev_instance)
974{
975 int dsr;
976 struct rio_mport *port = (struct rio_mport *)dev_instance;
977 struct rio_priv *priv = port->priv;
978
979 dsr = in_be32(&priv->msg_regs->dsr);
980
981 if (dsr & DOORBELL_DSR_TE) {
982 pr_info("RIO: doorbell reception error\n");
983 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
984 goto out;
985 }
986
987 if (dsr & DOORBELL_DSR_QFI) {
988 pr_info("RIO: doorbell queue full\n");
989 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
990 }
991
992 /* XXX Need to check/dispatch until queue empty */
993 if (dsr & DOORBELL_DSR_DIQI) {
994 u32 dmsg =
995 (u32) priv->dbell_ring.virt +
996 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
997 struct rio_dbell *dbell;
998 int found = 0;
999
1000 pr_debug
1001 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1002 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1003
1004 list_for_each_entry(dbell, &port->dbells, node) {
1005 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
1006 (dbell->res->end >= DBELL_INF(dmsg))) {
1007 found = 1;
1008 break;
1009 }
1010 }
1011 if (found) {
1012 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
1013 DBELL_INF(dmsg));
1014 } else {
1015 pr_debug
1016 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
1017 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
1018 }
1019 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
1020 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
1021 }
1022
1023 out:
1024 return IRQ_HANDLED;
1025}
1026
1027/**
1028 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1029 * @mport: Master port implementing the inbound doorbell unit
1030 *
1031 * Initializes doorbell unit hardware and inbound DMA buffer
1032 * ring. Called from fsl_rio_setup(). Returns %0 on success
1033 * or %-ENOMEM on failure.
1034 */
1035static int fsl_rio_doorbell_init(struct rio_mport *mport)
1036{
1037 struct rio_priv *priv = mport->priv;
1038 int rc = 0;
1039
1040 /* Map outbound doorbell window immediately after maintenance window */
1041 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1042 RIO_DBELL_WIN_SIZE);
1043 if (!priv->dbell_win) {
1044 printk(KERN_ERR
1045 "RIO: unable to map outbound doorbell window\n");
1046 rc = -ENOMEM;
1047 goto out;
1048 }
1049
1050 /* Initialize inbound doorbells */
1051 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1052 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1053 if (!priv->dbell_ring.virt) {
1054 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1055 rc = -ENOMEM;
1056 iounmap(priv->dbell_win);
1057 goto out;
1058 }
1059
1060 /* Point dequeue/enqueue pointers at first entry in ring */
1061 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1062 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1063
1064 /* Clear interrupt status */
1065 out_be32(&priv->msg_regs->dsr, 0x00000091);
1066
1067 /* Hook up doorbell handler */
1068 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1069 "dbell_rx", (void *)mport);
1070 if (rc < 0) {
1071 iounmap(priv->dbell_win);
1072 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1073 priv->dbell_ring.virt, priv->dbell_ring.phys);
1074 printk(KERN_ERR
1075 "MPC85xx RIO: unable to request inbound doorbell irq");
1076 goto out;
1077 }
1078
1079 /* Configure doorbells for snooping, 512 entries, and enable */
1080 out_be32(&priv->msg_regs->dmr, 0x00108161);
1081
1082 out:
1083 return rc;
1084}
1085
1086static void port_error_handler(struct rio_mport *port, int offset)
1087{ 268{
1088 /*XXX: Error recovery is not implemented, we just clear errors */ 269 /*XXX: Error recovery is not implemented, we just clear errors */
1089 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 270 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
@@ -1098,263 +279,6 @@ static void port_error_handler(struct rio_mport *port, int offset)
1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 279 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
1099 } 280 }
1100} 281}
1101
1102static void msg_unit_error_handler(struct rio_mport *port)
1103{
1104 struct rio_priv *priv = port->priv;
1105
1106 /*XXX: Error recovery is not implemented, we just clear errors */
1107 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
1108
1109 out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
1110 out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
1111 out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
1112 out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
1113
1114 out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
1115 out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
1116
1117 out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
1118}
1119
1120/**
1121 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1122 * @irq: Linux interrupt number
1123 * @dev_instance: Pointer to interrupt-specific data
1124 *
1125 * Handles port write interrupts. Parses a list of registered
1126 * port write event handlers and executes a matching event handler.
1127 */
1128static irqreturn_t
1129fsl_rio_port_write_handler(int irq, void *dev_instance)
1130{
1131 u32 ipwmr, ipwsr;
1132 struct rio_mport *port = (struct rio_mport *)dev_instance;
1133 struct rio_priv *priv = port->priv;
1134 u32 epwisr, tmp;
1135
1136 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1137 if (!(epwisr & RIO_EPWISR_PW))
1138 goto pw_done;
1139
1140 ipwmr = in_be32(&priv->msg_regs->pwmr);
1141 ipwsr = in_be32(&priv->msg_regs->pwsr);
1142
1143#ifdef DEBUG_PW
1144 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1145 if (ipwsr & RIO_IPWSR_QF)
1146 pr_debug(" QF");
1147 if (ipwsr & RIO_IPWSR_TE)
1148 pr_debug(" TE");
1149 if (ipwsr & RIO_IPWSR_QFI)
1150 pr_debug(" QFI");
1151 if (ipwsr & RIO_IPWSR_PWD)
1152 pr_debug(" PWD");
1153 if (ipwsr & RIO_IPWSR_PWB)
1154 pr_debug(" PWB");
1155 pr_debug(" )\n");
1156#endif
1157 /* Schedule deferred processing if PW was received */
1158 if (ipwsr & RIO_IPWSR_QFI) {
1159 /* Save PW message (if there is room in FIFO),
1160 * otherwise discard it.
1161 */
1162 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1163 priv->port_write_msg.msg_count++;
1164 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1165 RIO_PW_MSG_SIZE);
1166 } else {
1167 priv->port_write_msg.discard_count++;
1168 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1169 priv->port_write_msg.discard_count);
1170 }
1171 /* Clear interrupt and issue Clear Queue command. This allows
1172 * another port-write to be received.
1173 */
1174 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1175 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1176
1177 schedule_work(&priv->pw_work);
1178 }
1179
1180 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1181 priv->port_write_msg.err_count++;
1182 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1183 priv->port_write_msg.err_count);
1184 /* Clear Transaction Error: port-write controller should be
1185 * disabled when clearing this error
1186 */
1187 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1188 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1189 out_be32(&priv->msg_regs->pwmr, ipwmr);
1190 }
1191
1192 if (ipwsr & RIO_IPWSR_PWD) {
1193 priv->port_write_msg.discard_count++;
1194 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1195 priv->port_write_msg.discard_count);
1196 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1197 }
1198
1199pw_done:
1200 if (epwisr & RIO_EPWISR_PINT1) {
1201 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1202 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1203 port_error_handler(port, 0);
1204 }
1205
1206 if (epwisr & RIO_EPWISR_PINT2) {
1207 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1208 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1209 port_error_handler(port, 1);
1210 }
1211
1212 if (epwisr & RIO_EPWISR_MU) {
1213 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1214 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1215 msg_unit_error_handler(port);
1216 }
1217
1218 return IRQ_HANDLED;
1219}
1220
1221static void fsl_pw_dpc(struct work_struct *work)
1222{
1223 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1224 unsigned long flags;
1225 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1226
1227 /*
1228 * Process port-write messages
1229 */
1230 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1231 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1232 RIO_PW_MSG_SIZE)) {
1233 /* Process one message */
1234 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1235#ifdef DEBUG_PW
1236 {
1237 u32 i;
1238 pr_debug("%s : Port-Write Message:", __func__);
1239 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1240 if ((i%4) == 0)
1241 pr_debug("\n0x%02x: 0x%08x", i*4,
1242 msg_buffer[i]);
1243 else
1244 pr_debug(" 0x%08x", msg_buffer[i]);
1245 }
1246 pr_debug("\n");
1247 }
1248#endif
1249 /* Pass the port-write message to RIO core for processing */
1250 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1251 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1252 }
1253 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1254}
1255
1256/**
1257 * fsl_rio_pw_enable - enable/disable port-write interface init
1258 * @mport: Master port implementing the port write unit
1259 * @enable: 1=enable; 0=disable port-write message handling
1260 */
1261static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1262{
1263 struct rio_priv *priv = mport->priv;
1264 u32 rval;
1265
1266 rval = in_be32(&priv->msg_regs->pwmr);
1267
1268 if (enable)
1269 rval |= RIO_IPWMR_PWE;
1270 else
1271 rval &= ~RIO_IPWMR_PWE;
1272
1273 out_be32(&priv->msg_regs->pwmr, rval);
1274
1275 return 0;
1276}
1277
1278/**
1279 * fsl_rio_port_write_init - MPC85xx port write interface init
1280 * @mport: Master port implementing the port write unit
1281 *
1282 * Initializes port write unit hardware and DMA buffer
1283 * ring. Called from fsl_rio_setup(). Returns %0 on success
1284 * or %-ENOMEM on failure.
1285 */
1286static int fsl_rio_port_write_init(struct rio_mport *mport)
1287{
1288 struct rio_priv *priv = mport->priv;
1289 int rc = 0;
1290
1291 /* Following configurations require a disabled port write controller */
1292 out_be32(&priv->msg_regs->pwmr,
1293 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1294
1295 /* Initialize port write */
1296 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1297 RIO_PW_MSG_SIZE,
1298 &priv->port_write_msg.phys, GFP_KERNEL);
1299 if (!priv->port_write_msg.virt) {
1300 pr_err("RIO: unable allocate port write queue\n");
1301 return -ENOMEM;
1302 }
1303
1304 priv->port_write_msg.err_count = 0;
1305 priv->port_write_msg.discard_count = 0;
1306
1307 /* Point dequeue/enqueue pointers at first entry */
1308 out_be32(&priv->msg_regs->epwqbar, 0);
1309 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1310
1311 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1312 in_be32(&priv->msg_regs->epwqbar),
1313 in_be32(&priv->msg_regs->pwqbar));
1314
1315 /* Clear interrupt status IPWSR */
1316 out_be32(&priv->msg_regs->pwsr,
1317 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1318
1319 /* Configure port write contoller for snooping enable all reporting,
1320 clear queue full */
1321 out_be32(&priv->msg_regs->pwmr,
1322 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1323
1324
1325 /* Hook up port-write handler */
1326 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
1327 IRQF_SHARED, "port-write", (void *)mport);
1328 if (rc < 0) {
1329 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1330 goto err_out;
1331 }
1332 /* Enable Error Interrupt */
1333 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
1334
1335 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1336 spin_lock_init(&priv->pw_fifo_lock);
1337 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1338 pr_err("FIFO allocation failed\n");
1339 rc = -ENOMEM;
1340 goto err_out_irq;
1341 }
1342
1343 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1344 in_be32(&priv->msg_regs->pwmr),
1345 in_be32(&priv->msg_regs->pwsr));
1346
1347 return rc;
1348
1349err_out_irq:
1350 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1351err_out:
1352 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1353 priv->port_write_msg.virt,
1354 priv->port_write_msg.phys);
1355 return rc;
1356}
1357
1358static inline void fsl_rio_info(struct device *dev, u32 ccsr) 282static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1359{ 283{
1360 const char *str; 284 const char *str;
@@ -1411,16 +335,21 @@ int fsl_rio_setup(struct platform_device *dev)
1411 struct rio_mport *port; 335 struct rio_mport *port;
1412 struct rio_priv *priv; 336 struct rio_priv *priv;
1413 int rc = 0; 337 int rc = 0;
1414 const u32 *dt_range, *cell; 338 const u32 *dt_range, *cell, *port_index;
1415 struct resource regs; 339 u32 active_ports = 0;
340 struct resource regs, rmu_regs;
341 struct device_node *np, *rmu_node;
1416 int rlen; 342 int rlen;
1417 u32 ccsr; 343 u32 ccsr;
1418 u64 law_start, law_size; 344 u64 range_start, range_size;
1419 int paw, aw, sw; 345 int paw, aw, sw;
346 u32 i;
347 static int tmp;
348 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
1420 349
1421 if (!dev->dev.of_node) { 350 if (!dev->dev.of_node) {
1422 dev_err(&dev->dev, "Device OF-Node is NULL"); 351 dev_err(&dev->dev, "Device OF-Node is NULL");
1423 return -EFAULT; 352 return -ENODEV;
1424 } 353 }
1425 354
1426 rc = of_address_to_resource(dev->dev.of_node, 0, &regs); 355 rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
@@ -1429,37 +358,17 @@ int fsl_rio_setup(struct platform_device *dev)
1429 dev->dev.of_node->full_name); 358 dev->dev.of_node->full_name);
1430 return -EFAULT; 359 return -EFAULT;
1431 } 360 }
1432 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 361 dev_info(&dev->dev, "Of-device full name %s\n",
362 dev->dev.of_node->full_name);
1433 dev_info(&dev->dev, "Regs: %pR\n", &regs); 363 dev_info(&dev->dev, "Regs: %pR\n", &regs);
1434 364
1435 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); 365 rio_regs_win = ioremap(regs.start, resource_size(&regs));
1436 if (!dt_range) { 366 if (!rio_regs_win) {
1437 dev_err(&dev->dev, "Can't get %s property 'ranges'\n", 367 dev_err(&dev->dev, "Unable to map rio register window\n");
1438 dev->dev.of_node->full_name); 368 rc = -ENOMEM;
1439 return -EFAULT; 369 goto err_rio_regs;
1440 } 370 }
1441 371
1442 /* Get node address wide */
1443 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1444 if (cell)
1445 aw = *cell;
1446 else
1447 aw = of_n_addr_cells(dev->dev.of_node);
1448 /* Get node size wide */
1449 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1450 if (cell)
1451 sw = *cell;
1452 else
1453 sw = of_n_size_cells(dev->dev.of_node);
1454 /* Get parent address wide wide */
1455 paw = of_n_addr_cells(dev->dev.of_node);
1456
1457 law_start = of_read_number(dt_range + aw, paw);
1458 law_size = of_read_number(dt_range + aw + paw, sw);
1459
1460 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1461 law_start, law_size);
1462
1463 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); 372 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1464 if (!ops) { 373 if (!ops) {
1465 rc = -ENOMEM; 374 rc = -ENOMEM;
@@ -1479,143 +388,257 @@ int fsl_rio_setup(struct platform_device *dev)
1479 ops->add_inb_buffer = fsl_add_inb_buffer; 388 ops->add_inb_buffer = fsl_add_inb_buffer;
1480 ops->get_inb_message = fsl_get_inb_message; 389 ops->get_inb_message = fsl_get_inb_message;
1481 390
1482 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 391 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
1483 if (!port) { 392 if (!rmu_node)
393 goto err_rmu;
394 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
395 if (rc) {
396 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
397 rmu_node->full_name);
398 goto err_rmu;
399 }
400 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
401 if (!rmu_regs_win) {
402 dev_err(&dev->dev, "Unable to map rmu register window\n");
1484 rc = -ENOMEM; 403 rc = -ENOMEM;
1485 goto err_port; 404 goto err_rmu;
405 }
406 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
407 rmu_np[tmp] = np;
408 tmp++;
1486 } 409 }
1487 port->index = 0;
1488 410
1489 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 411 /*set up doobell node*/
1490 if (!priv) { 412 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
1491 printk(KERN_ERR "Can't alloc memory for 'priv'\n"); 413 if (!np) {
414 rc = -ENODEV;
415 goto err_dbell;
416 }
417 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
418 if (!(dbell)) {
419 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
1492 rc = -ENOMEM; 420 rc = -ENOMEM;
1493 goto err_priv; 421 goto err_dbell;
1494 } 422 }
423 dbell->dev = &dev->dev;
424 dbell->bellirq = irq_of_parse_and_map(np, 1);
425 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
1495 426
1496 INIT_LIST_HEAD(&port->dbells); 427 aw = of_n_addr_cells(np);
1497 port->iores.start = law_start; 428 dt_range = of_get_property(np, "reg", &rlen);
1498 port->iores.end = law_start + law_size - 1; 429 if (!dt_range) {
1499 port->iores.flags = IORESOURCE_MEM; 430 pr_err("%s: unable to find 'reg' property\n",
1500 port->iores.name = "rio_io_win"; 431 np->full_name);
1501 432 rc = -ENOMEM;
1502 if (request_resource(&iomem_resource, &port->iores) < 0) { 433 goto err_pw;
1503 dev_err(&dev->dev, "RIO: Error requesting master port region"
1504 " 0x%016llx-0x%016llx\n",
1505 (u64)port->iores.start, (u64)port->iores.end);
1506 rc = -ENOMEM;
1507 goto err_res;
1508 } 434 }
435 range_start = of_read_number(dt_range, aw);
436 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
437 (u32)range_start);
1509 438
1510 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 439 /*set up port write node*/
1511 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 440 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
1512 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 441 if (!np) {
1513 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 442 rc = -ENODEV;
1514 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 443 goto err_pw;
1515 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 444 }
1516 445 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
1517 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 446 if (!(pw)) {
1518 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 447 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
1519 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 448 rc = -ENOMEM;
1520 strcpy(port->name, "RIO0 mport"); 449 goto err_pw;
1521 450 }
1522 priv->dev = &dev->dev; 451 pw->dev = &dev->dev;
1523 452 pw->pwirq = irq_of_parse_and_map(np, 0);
1524 port->ops = ops; 453 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
1525 port->priv = priv; 454 aw = of_n_addr_cells(np);
1526 port->phys_efptr = 0x100; 455 dt_range = of_get_property(np, "reg", &rlen);
1527 456 if (!dt_range) {
1528 priv->regs_win = ioremap(regs.start, resource_size(&regs)); 457 pr_err("%s: unable to find 'reg' property\n",
1529 rio_regs_win = priv->regs_win; 458 np->full_name);
1530 459 rc = -ENOMEM;
1531 /* Probe the master port phy type */ 460 goto err;
1532 ccsr = in_be32(priv->regs_win + RIO_CCSR); 461 }
1533 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; 462 range_start = of_read_number(dt_range, aw);
1534 dev_info(&dev->dev, "RapidIO PHY type: %s\n", 463 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
1535 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : 464
1536 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : 465 /*set up ports node*/
1537 "unknown")); 466 for_each_child_of_node(dev->dev.of_node, np) {
1538 /* Checking the port training status */ 467 port_index = of_get_property(np, "cell-index", NULL);
1539 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 468 if (!port_index) {
1540 dev_err(&dev->dev, "Port is not ready. " 469 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
1541 "Try to restart connection...\n"); 470 np->full_name);
1542 switch (port->phy_type) { 471 continue;
1543 case RIO_PHY_SERIAL: 472 }
473
474 dt_range = of_get_property(np, "ranges", &rlen);
475 if (!dt_range) {
476 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
477 np->full_name);
478 continue;
479 }
480
481 /* Get node address wide */
482 cell = of_get_property(np, "#address-cells", NULL);
483 if (cell)
484 aw = *cell;
485 else
486 aw = of_n_addr_cells(np);
487 /* Get node size wide */
488 cell = of_get_property(np, "#size-cells", NULL);
489 if (cell)
490 sw = *cell;
491 else
492 sw = of_n_size_cells(np);
493 /* Get parent address wide wide */
494 paw = of_n_addr_cells(np);
495 range_start = of_read_number(dt_range + aw, paw);
496 range_size = of_read_number(dt_range + aw + paw, sw);
497
498 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
499 np->full_name, range_start, range_size);
500
501 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
502 if (!port)
503 continue;
504
505 i = *port_index - 1;
506 port->index = (unsigned char)i;
507
508 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
509 if (!priv) {
510 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
511 kfree(port);
512 continue;
513 }
514
515 INIT_LIST_HEAD(&port->dbells);
516 port->iores.start = range_start;
517 port->iores.end = port->iores.start + range_size - 1;
518 port->iores.flags = IORESOURCE_MEM;
519 port->iores.name = "rio_io_win";
520
521 if (request_resource(&iomem_resource, &port->iores) < 0) {
522 dev_err(&dev->dev, "RIO: Error requesting master port region"
523 " 0x%016llx-0x%016llx\n",
524 (u64)port->iores.start, (u64)port->iores.end);
525 kfree(priv);
526 kfree(port);
527 continue;
528 }
529 sprintf(port->name, "RIO mport %d", i);
530
531 priv->dev = &dev->dev;
532 port->ops = ops;
533 port->priv = priv;
534 port->phys_efptr = 0x100;
535 priv->regs_win = rio_regs_win;
536
537 /* Probe the master port phy type */
538 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
539 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
540 if (port->phy_type == RIO_PHY_PARALLEL) {
541 dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
542 release_resource(&port->iores);
543 kfree(priv);
544 kfree(port);
545 continue;
546 }
547 dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
548 /* Checking the port training status */
549 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
550 dev_err(&dev->dev, "Port %d is not ready. "
551 "Try to restart connection...\n", i);
1544 /* Disable ports */ 552 /* Disable ports */
1545 out_be32(priv->regs_win + RIO_CCSR, 0); 553 out_be32(priv->regs_win
554 + RIO_CCSR + i*0x20, 0);
1546 /* Set 1x lane */ 555 /* Set 1x lane */
1547 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); 556 setbits32(priv->regs_win
557 + RIO_CCSR + i*0x20, 0x02000000);
1548 /* Enable ports */ 558 /* Enable ports */
1549 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); 559 setbits32(priv->regs_win
1550 break; 560 + RIO_CCSR + i*0x20, 0x00600000);
1551 case RIO_PHY_PARALLEL: 561 msleep(100);
1552 /* Disable ports */ 562 if (in_be32((priv->regs_win
1553 out_be32(priv->regs_win + RIO_CCSR, 0x22000000); 563 + RIO_ESCSR + i*0x20)) & 1) {
1554 /* Enable ports */ 564 dev_err(&dev->dev,
1555 out_be32(priv->regs_win + RIO_CCSR, 0x44000000); 565 "Port %d restart failed.\n", i);
1556 break; 566 release_resource(&port->iores);
1557 } 567 kfree(priv);
1558 msleep(100); 568 kfree(port);
1559 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 569 continue;
1560 dev_err(&dev->dev, "Port restart failed.\n"); 570 }
1561 rc = -ENOLINK; 571 dev_info(&dev->dev, "Port %d restart success!\n", i);
1562 goto err;
1563 } 572 }
1564 dev_info(&dev->dev, "Port restart success!\n"); 573 fsl_rio_info(&dev->dev, ccsr);
1565 }
1566 fsl_rio_info(&dev->dev, ccsr);
1567 574
1568 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 575 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1569 & RIO_PEF_CTLS) >> 4; 576 & RIO_PEF_CTLS) >> 4;
1570 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 577 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1571 port->sys_size ? 65536 : 256); 578 port->sys_size ? 65536 : 256);
579
580 if (rio_register_mport(port)) {
581 release_resource(&port->iores);
582 kfree(priv);
583 kfree(port);
584 continue;
585 }
586 if (port->host_deviceid >= 0)
587 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
588 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
589 else
590 out_be32(priv->regs_win + RIO_GCCSR,
591 RIO_PORT_GEN_MASTER);
592
593 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
594 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
595 RIO_ATMU_REGS_PORT2_OFFSET));
1572 596
1573 if (rio_register_mport(port)) 597 priv->maint_atmu_regs = priv->atmu_regs + 1;
598
599 /* Set to receive any dist ID for serial RapidIO controller. */
600 if (port->phy_type == RIO_PHY_SERIAL)
601 out_be32((priv->regs_win
602 + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
603
604 /* Configure maintenance transaction window */
605 out_be32(&priv->maint_atmu_regs->rowbar,
606 port->iores.start >> 12);
607 out_be32(&priv->maint_atmu_regs->rowar,
608 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
609
610 priv->maint_win = ioremap(port->iores.start,
611 RIO_MAINT_WIN_SIZE);
612
613 rio_law_start = range_start;
614
615 fsl_rio_setup_rmu(port, rmu_np[i]);
616
617 dbell->mport[i] = port;
618
619 active_ports++;
620 }
621
622 if (!active_ports) {
623 rc = -ENOLINK;
1574 goto err; 624 goto err;
625 }
1575 626
1576 if (port->host_deviceid >= 0) 627 fsl_rio_doorbell_init(dbell);
1577 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 628 fsl_rio_port_write_init(pw);
1578 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
1579 else
1580 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
1581
1582 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1583 + RIO_ATMU_REGS_OFFSET);
1584 priv->maint_atmu_regs = priv->atmu_regs + 1;
1585 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1586 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1587 ((port->phy_type == RIO_PHY_SERIAL) ?
1588 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1589
1590 /* Set to receive any dist ID for serial RapidIO controller. */
1591 if (port->phy_type == RIO_PHY_SERIAL)
1592 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1593
1594 /* Configure maintenance transaction window */
1595 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1596 out_be32(&priv->maint_atmu_regs->rowar,
1597 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1598
1599 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1600
1601 /* Configure outbound doorbell window */
1602 out_be32(&priv->dbell_atmu_regs->rowbar,
1603 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1604 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1605 fsl_rio_doorbell_init(port);
1606 fsl_rio_port_write_init(port);
1607 629
1608 return 0; 630 return 0;
1609err: 631err:
1610 iounmap(priv->regs_win); 632 kfree(pw);
1611 release_resource(&port->iores); 633err_pw:
1612err_res: 634 kfree(dbell);
1613 kfree(priv); 635err_dbell:
1614err_priv: 636 iounmap(rmu_regs_win);
1615 kfree(port); 637err_rmu:
1616err_port:
1617 kfree(ops); 638 kfree(ops);
1618err_ops: 639err_ops:
640 iounmap(rio_regs_win);
641err_rio_regs:
1619 return rc; 642 return rc;
1620} 643}
1621 644
@@ -1631,7 +654,7 @@ static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
1631 654
1632static const struct of_device_id fsl_of_rio_rpn_ids[] = { 655static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1633 { 656 {
1634 .compatible = "fsl,rapidio-delta", 657 .compatible = "fsl,srio",
1635 }, 658 },
1636 {}, 659 {},
1637}; 660};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 20:56:12 -0500