diff options
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.c | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 028ac1f71b51..46ac1ddea683 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
@@ -97,22 +97,14 @@ static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, | |||
97 | return indirect_read_config(bus, devfn, offset, len, val); | 97 | return indirect_read_config(bus, devfn, offset, len, val); |
98 | } | 98 | } |
99 | 99 | ||
100 | static struct pci_ops fsl_indirect_pci_ops = | 100 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
101 | |||
102 | static struct pci_ops fsl_indirect_pcie_ops = | ||
101 | { | 103 | { |
102 | .read = fsl_indirect_read_config, | 104 | .read = fsl_indirect_read_config, |
103 | .write = indirect_write_config, | 105 | .write = indirect_write_config, |
104 | }; | 106 | }; |
105 | 107 | ||
106 | static void __init fsl_setup_indirect_pci(struct pci_controller* hose, | ||
107 | resource_size_t cfg_addr, | ||
108 | resource_size_t cfg_data, u32 flags) | ||
109 | { | ||
110 | setup_indirect_pci(hose, cfg_addr, cfg_data, flags); | ||
111 | hose->ops = &fsl_indirect_pci_ops; | ||
112 | } | ||
113 | |||
114 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | ||
115 | |||
116 | #define MAX_PHYS_ADDR_BITS 40 | 108 | #define MAX_PHYS_ADDR_BITS 40 |
117 | static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; | 109 | static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; |
118 | 110 | ||
@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) | |||
504 | if (!hose->private_data) | 496 | if (!hose->private_data) |
505 | goto no_bridge; | 497 | goto no_bridge; |
506 | 498 | ||
507 | fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, | 499 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
508 | PPC_INDIRECT_TYPE_BIG_ENDIAN); | 500 | PPC_INDIRECT_TYPE_BIG_ENDIAN); |
509 | 501 | ||
510 | if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) | 502 | if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) |
511 | hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; | 503 | hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; |
512 | 504 | ||
513 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { | 505 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
506 | /* use fsl_indirect_read_config for PCIe */ | ||
507 | hose->ops = &fsl_indirect_pcie_ops; | ||
514 | /* For PCIE read HEADER_TYPE to identify controler mode */ | 508 | /* For PCIE read HEADER_TYPE to identify controler mode */ |
515 | early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); | 509 | early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); |
516 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) | 510 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) |
@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) | |||
814 | if (ret) | 808 | if (ret) |
815 | goto err0; | 809 | goto err0; |
816 | } else { | 810 | } else { |
817 | fsl_setup_indirect_pci(hose, rsrc_cfg.start, | 811 | setup_indirect_pci(hose, rsrc_cfg.start, |
818 | rsrc_cfg.start + 4, 0); | 812 | rsrc_cfg.start + 4, 0); |
819 | } | 813 | } |
820 | 814 | ||
821 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " | 815 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |