1 files changed, 15 insertions, 30 deletions

diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 5a6c5dfc53ef..f1c3395633b9 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -115,16 +115,10 @@ EXPORT_SYMBOL(cpm_command);
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK     (get_brgfreq())
-#define BRG_UART_CLK    (BRG_INT_CLK/16)
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-void
-cpm_setbrg(uint brg, uint rate)
+void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
 {
         u32 __iomem *bp;
+        u32 val;
 
         /* This is good enough to get SMCs running.....
         */
@@ -135,34 +129,14 @@ cpm_setbrg(uint brg, uint rate)
                 brg -= 4;
         }
         bp += brg;
-        out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
-
-        cpm2_unmap(bp);
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-void
-cpm2_fastbrg(uint brg, uint rate, int div16)
-{
-        u32 __iomem *bp;
-        u32 val;
-
-        if (brg < 4) {
-                bp = cpm2_map_size(im_brgc1, 16);
-        } else {
-                bp = cpm2_map_size(im_brgc5, 16);
-                brg -= 4;
-        }
-        bp += brg;
-        val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
+        val = (((clk / rate) - 1) << 1) | CPM_BRG_EN | src;
         if (div16)
                 val |= CPM_BRG_DIV16;
 
         out_be32(bp, val);
         cpm2_unmap(bp);
 }
+EXPORT_SYMBOL(__cpm2_setbrg);
 
 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 {
@@ -377,3 +351,14 @@ void cpm2_set_pin(int port, int pin, int flags)
         else
                 clrbits32(&iop[port].odr, pin);
 }
+
+static int cpm_init_par_io(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
+                cpm2_gpiochip_add32(np);
+        return 0;
+}
+arch_initcall(cpm_init_par_io);
+