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-rw-r--r--arch/powerpc/platforms/85xx/mpc8544_ds.c2
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c2
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c2
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c2
-rw-r--r--arch/powerpc/platforms/Kconfig1
-rw-r--r--arch/powerpc/platforms/cell/spu_base.c24
-rw-r--r--arch/powerpc/platforms/cell/spu_manage.c8
-rw-r--r--arch/powerpc/platforms/cell/spufs/backing_ops.c3
-rw-r--r--arch/powerpc/platforms/cell/spufs/run.c6
-rw-r--r--arch/powerpc/platforms/ps3/platform.h1
-rw-r--r--arch/powerpc/platforms/ps3/repository.c29
-rw-r--r--arch/powerpc/platforms/ps3/setup.c3
-rw-r--r--arch/powerpc/platforms/ps3/spu.c2
13 files changed, 68 insertions, 17 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c
index 0f834d8be444..48983bc56d46 100644
--- a/arch/powerpc/platforms/85xx/mpc8544_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c
@@ -178,7 +178,9 @@ define_machine(mpc8544_ds) {
178 .probe = mpc8544_ds_probe, 178 .probe = mpc8544_ds_probe,
179 .setup_arch = mpc8544_ds_setup_arch, 179 .setup_arch = mpc8544_ds_setup_arch,
180 .init_IRQ = mpc8544_ds_pic_init, 180 .init_IRQ = mpc8544_ds_pic_init,
181#ifdef CONFIG_PCI
181 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 182 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
183#endif
182 .get_irq = mpic_get_irq, 184 .get_irq = mpic_get_irq,
183 .restart = mpc85xx_restart, 185 .restart = mpc85xx_restart,
184 .calibrate_decr = generic_calibrate_decr, 186 .calibrate_decr = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 040233472385..b46c8d50f6d1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -350,10 +350,10 @@ define_machine(mpc85xx_cds) {
350 .get_irq = mpic_get_irq, 350 .get_irq = mpic_get_irq,
351#ifdef CONFIG_PCI 351#ifdef CONFIG_PCI
352 .restart = mpc85xx_cds_restart, 352 .restart = mpc85xx_cds_restart,
353 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
353#else 354#else
354 .restart = mpc85xx_restart, 355 .restart = mpc85xx_restart,
355#endif 356#endif
356 .calibrate_decr = generic_calibrate_decr, 357 .calibrate_decr = generic_calibrate_decr,
357 .progress = udbg_progress, 358 .progress = udbg_progress,
358 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
359}; 359};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 53830c9a88fd..66366a023820 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,5 +206,7 @@ define_machine(mpc85xx_mds) {
206 .restart = mpc85xx_restart, 206 .restart = mpc85xx_restart,
207 .calibrate_decr = generic_calibrate_decr, 207 .calibrate_decr = generic_calibrate_decr,
208 .progress = udbg_progress, 208 .progress = udbg_progress,
209#ifdef CONFIG_PCI
209 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 210 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
211#endif
210}; 212};
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 56b27caf7a27..47aafa76c933 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -250,5 +250,7 @@ define_machine(mpc86xx_hpcn) {
250 .time_init = mpc86xx_time_init, 250 .time_init = mpc86xx_time_init,
251 .calibrate_decr = generic_calibrate_decr, 251 .calibrate_decr = generic_calibrate_decr,
252 .progress = udbg_progress, 252 .progress = udbg_progress,
253#ifdef CONFIG_PCI
253 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 254 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
255#endif
254}; 256};
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 8eb8d400ecb2..065f3b19d6c7 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -286,6 +286,7 @@ config AXON_RAM
286config FSL_ULI1575 286config FSL_ULI1575
287 bool 287 bool
288 default n 288 default n
289 select GENERIC_ISA_DMA
289 help 290 help
290 Supports for the ULI1575 PCIe south bridge that exists on some 291 Supports for the ULI1575 PCIe south bridge that exists on some
291 Freescale reference boards. The boards all use the ULI in pretty 292 Freescale reference boards. The boards all use the ULI in pretty
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 095a30304c56..106d2921e2d9 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -236,27 +236,34 @@ static irqreturn_t
236spu_irq_class_0(int irq, void *data) 236spu_irq_class_0(int irq, void *data)
237{ 237{
238 struct spu *spu; 238 struct spu *spu;
239 unsigned long stat, mask;
239 240
240 spu = data; 241 spu = data;
241 spu->class_0_pending = 1; 242
243 mask = spu_int_mask_get(spu, 0);
244 stat = spu_int_stat_get(spu, 0);
245 stat &= mask;
246
247 spin_lock(&spu->register_lock);
248 spu->class_0_pending |= stat;
249 spin_unlock(&spu->register_lock);
250
242 spu->stop_callback(spu); 251 spu->stop_callback(spu);
243 252
253 spu_int_stat_clear(spu, 0, stat);
254
244 return IRQ_HANDLED; 255 return IRQ_HANDLED;
245} 256}
246 257
247int 258int
248spu_irq_class_0_bottom(struct spu *spu) 259spu_irq_class_0_bottom(struct spu *spu)
249{ 260{
250 unsigned long stat, mask;
251 unsigned long flags; 261 unsigned long flags;
252 262 unsigned long stat;
253 spu->class_0_pending = 0;
254 263
255 spin_lock_irqsave(&spu->register_lock, flags); 264 spin_lock_irqsave(&spu->register_lock, flags);
256 mask = spu_int_mask_get(spu, 0); 265 stat = spu->class_0_pending;
257 stat = spu_int_stat_get(spu, 0); 266 spu->class_0_pending = 0;
258
259 stat &= mask;
260 267
261 if (stat & 1) /* invalid DMA alignment */ 268 if (stat & 1) /* invalid DMA alignment */
262 __spu_trap_dma_align(spu); 269 __spu_trap_dma_align(spu);
@@ -267,7 +274,6 @@ spu_irq_class_0_bottom(struct spu *spu)
267 if (stat & 4) /* error on SPU */ 274 if (stat & 4) /* error on SPU */
268 __spu_trap_error(spu); 275 __spu_trap_error(spu);
269 276
270 spu_int_stat_clear(spu, 0, stat);
271 spin_unlock_irqrestore(&spu->register_lock, flags); 277 spin_unlock_irqrestore(&spu->register_lock, flags);
272 278
273 return (stat & 0x7) ? -EIO : 0; 279 return (stat & 0x7) ? -EIO : 0;
diff --git a/arch/powerpc/platforms/cell/spu_manage.c b/arch/powerpc/platforms/cell/spu_manage.c
index 7c0668a9dcc7..0e14f532500e 100644
--- a/arch/powerpc/platforms/cell/spu_manage.c
+++ b/arch/powerpc/platforms/cell/spu_manage.c
@@ -48,10 +48,18 @@ static u64 __init find_spu_unit_number(struct device_node *spe)
48{ 48{
49 const unsigned int *prop; 49 const unsigned int *prop;
50 int proplen; 50 int proplen;
51
52 /* new device trees should provide the physical-id attribute */
51 prop = of_get_property(spe, "physical-id", &proplen); 53 prop = of_get_property(spe, "physical-id", &proplen);
52 if (proplen == 4) 54 if (proplen == 4)
53 return (u64)*prop; 55 return (u64)*prop;
54 56
57 /* celleb device tree provides the unit-id */
58 prop = of_get_property(spe, "unit-id", &proplen);
59 if (proplen == 4)
60 return (u64)*prop;
61
62 /* legacy device trees provide the id in the reg attribute */
55 prop = of_get_property(spe, "reg", &proplen); 63 prop = of_get_property(spe, "reg", &proplen);
56 if (proplen == 4) 64 if (proplen == 4)
57 return (u64)*prop; 65 return (u64)*prop;
diff --git a/arch/powerpc/platforms/cell/spufs/backing_ops.c b/arch/powerpc/platforms/cell/spufs/backing_ops.c
index 07a0e815abf5..ec01214e51ee 100644
--- a/arch/powerpc/platforms/cell/spufs/backing_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/backing_ops.c
@@ -162,7 +162,8 @@ static int spu_backing_wbox_write(struct spu_context *ctx, u32 data)
162 BUG_ON(avail != (4 - slot)); 162 BUG_ON(avail != (4 - slot));
163 ctx->csa.spu_mailbox_data[slot] = data; 163 ctx->csa.spu_mailbox_data[slot] = data;
164 ctx->csa.spu_chnlcnt_RW[29] = ++slot; 164 ctx->csa.spu_chnlcnt_RW[29] = ++slot;
165 ctx->csa.prob.mb_stat_R = (((4 - slot) & 0xff) << 8); 165 ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
166 ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
166 gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT); 167 gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT);
167 ret = 4; 168 ret = 4;
168 } else { 169 } else {
diff --git a/arch/powerpc/platforms/cell/spufs/run.c b/arch/powerpc/platforms/cell/spufs/run.c
index 6abdd8fe2098..958f10e90fdd 100644
--- a/arch/powerpc/platforms/cell/spufs/run.c
+++ b/arch/powerpc/platforms/cell/spufs/run.c
@@ -193,11 +193,7 @@ static int spu_reacquire_runnable(struct spu_context *ctx, u32 *npc,
193 if (ret) 193 if (ret)
194 return ret; 194 return ret;
195 195
196 ret = spu_run_init(ctx, npc); 196 spuctx_switch_state(ctx, SPU_UTIL_USER);
197 if (ret) {
198 spu_release(ctx);
199 return ret;
200 }
201 return 0; 197 return 0;
202} 198}
203 199
diff --git a/arch/powerpc/platforms/ps3/platform.h b/arch/powerpc/platforms/ps3/platform.h
index 87d52060fec0..2eb8f92704b4 100644
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -83,6 +83,7 @@ enum ps3_dev_type {
83 PS3_DEV_TYPE_STOR_ROM = TYPE_ROM, /* 5 */ 83 PS3_DEV_TYPE_STOR_ROM = TYPE_ROM, /* 5 */
84 PS3_DEV_TYPE_SB_GPIO = 6, 84 PS3_DEV_TYPE_SB_GPIO = 6,
85 PS3_DEV_TYPE_STOR_FLASH = TYPE_RBC, /* 14 */ 85 PS3_DEV_TYPE_STOR_FLASH = TYPE_RBC, /* 14 */
86 PS3_DEV_TYPE_STOR_DUMMY = 32,
86 PS3_DEV_TYPE_NOACCESS = 255, 87 PS3_DEV_TYPE_NOACCESS = 255,
87}; 88};
88 89
diff --git a/arch/powerpc/platforms/ps3/repository.c b/arch/powerpc/platforms/ps3/repository.c
index 8cc37cfea0f2..1c94824f7b63 100644
--- a/arch/powerpc/platforms/ps3/repository.c
+++ b/arch/powerpc/platforms/ps3/repository.c
@@ -349,6 +349,35 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
349 return result; 349 return result;
350 } 350 }
351 351
352 if (tmp.bus_type == PS3_BUS_TYPE_STORAGE) {
353 /*
354 * A storage device may show up in the repository before the
355 * hypervisor has finished probing its type and regions
356 */
357 unsigned int num_regions;
358
359 if (tmp.dev_type == PS3_DEV_TYPE_STOR_DUMMY) {
360 pr_debug("%s:%u storage device not ready\n", __func__,
361 __LINE__);
362 return -ENODEV;
363 }
364
365 result = ps3_repository_read_stor_dev_num_regions(tmp.bus_index,
366 tmp.dev_index,
367 &num_regions);
368 if (result) {
369 pr_debug("%s:%d read_stor_dev_num_regions failed\n",
370 __func__, __LINE__);
371 return result;
372 }
373
374 if (!num_regions) {
375 pr_debug("%s:%u storage device has no regions yet\n",
376 __func__, __LINE__);
377 return -ENODEV;
378 }
379 }
380
352 result = ps3_repository_read_dev_id(tmp.bus_index, tmp.dev_index, 381 result = ps3_repository_read_dev_id(tmp.bus_index, tmp.dev_index,
353 &tmp.dev_id); 382 &tmp.dev_id);
354 383
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index 2952b22f1c84..609945dbe394 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -63,7 +63,8 @@ int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev)
63 x.minor = minor; 63 x.minor = minor;
64 x.rev = rev; 64 x.rev = rev;
65 65
66 return (ps3_firmware_version.raw - x.raw); 66 return (ps3_firmware_version.raw > x.raw) -
67 (ps3_firmware_version.raw < x.raw);
67} 68}
68EXPORT_SYMBOL_GPL(ps3_compare_firmware_version); 69EXPORT_SYMBOL_GPL(ps3_compare_firmware_version);
69 70
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index ac2a4b8a4c14..d1630a074acf 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -505,6 +505,8 @@ static void mfc_sr1_set(struct spu *spu, u64 sr1)
505 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 505 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
506 | MFC_STATE1_PROBLEM_STATE_MASK); 506 | MFC_STATE1_PROBLEM_STATE_MASK);
507 507
508 sr1 |= MFC_STATE1_MASTER_RUN_CONTROL_MASK;
509
508 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); 510 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
509 511
510 spu_pdata(spu)->cache.sr1 = sr1; 512 spu_pdata(spu)->cache.sr1 = sr1;