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-rw-r--r--arch/powerpc/platforms/52xx/Kconfig5
-rw-r--r--arch/powerpc/platforms/52xx/Makefile1
-rw-r--r--arch/powerpc/platforms/52xx/media5200.c6
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpt.c432
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c560
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_pic.c10
6 files changed, 991 insertions, 23 deletions
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 8b8e9560a315..47ea1be1481b 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -62,3 +62,8 @@ config PPC_MPC5200_GPIO
62 select GENERIC_GPIO 62 select GENERIC_GPIO
63 help 63 help
64 Enable gpiolib support for mpc5200 based boards 64 Enable gpiolib support for mpc5200 based boards
65
66config PPC_MPC5200_LPBFIFO
67 tristate "MPC5200 LocalPlus bus FIFO driver"
68 depends on PPC_MPC52xx
69 select PPC_BESTCOMM_GEN_BD
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index bfd4f52cf3dd..2bc8cd0c5cfc 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -15,3 +15,4 @@ ifeq ($(CONFIG_PPC_LITE5200),y)
15endif 15endif
16 16
17obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o 17obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o
18obj-$(CONFIG_PPC_MPC5200_LPBFIFO) += mpc52xx_lpbfifo.o
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 68e4f1696d14..cc0c854291d7 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -74,7 +74,7 @@ static void media5200_irq_mask(unsigned int virq)
74} 74}
75 75
76static struct irq_chip media5200_irq_chip = { 76static struct irq_chip media5200_irq_chip = {
77 .typename = "Media5200 FPGA", 77 .name = "Media5200 FPGA",
78 .unmask = media5200_irq_unmask, 78 .unmask = media5200_irq_unmask,
79 .mask = media5200_irq_mask, 79 .mask = media5200_irq_mask,
80 .mask_ack = media5200_irq_mask, 80 .mask_ack = media5200_irq_mask,
@@ -114,7 +114,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
114static int media5200_irq_map(struct irq_host *h, unsigned int virq, 114static int media5200_irq_map(struct irq_host *h, unsigned int virq,
115 irq_hw_number_t hw) 115 irq_hw_number_t hw)
116{ 116{
117 struct irq_desc *desc = get_irq_desc(virq); 117 struct irq_desc *desc = irq_to_desc(virq);
118 118
119 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); 119 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
120 set_irq_chip_data(virq, &media5200_irq); 120 set_irq_chip_data(virq, &media5200_irq);
@@ -127,7 +127,7 @@ static int media5200_irq_map(struct irq_host *h, unsigned int virq,
127} 127}
128 128
129static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct, 129static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
130 u32 *intspec, unsigned int intsize, 130 const u32 *intspec, unsigned int intsize,
131 irq_hw_number_t *out_hwirq, 131 irq_hw_number_t *out_hwirq,
132 unsigned int *out_flags) 132 unsigned int *out_flags)
133{ 133{
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index bfbcd418e690..6f8ebe1085b3 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -16,8 +16,14 @@
16 * output signals or measure input signals. 16 * output signals or measure input signals.
17 * 17 *
18 * This driver supports the GPIO and IRQ controller functions of the GPT 18 * This driver supports the GPIO and IRQ controller functions of the GPT
19 * device. Timer functions are not yet supported, nor is the watchdog 19 * device. Timer functions are not yet supported.
20 * timer. 20 *
21 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
22 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
23 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
24 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
25 * this means that gpt0 is locked in wdt mode until the next reboot - this
26 * may be a requirement in safety applications.
21 * 27 *
22 * To use the GPIO function, the following two properties must be added 28 * To use the GPIO function, the following two properties must be added
23 * to the device tree node for the gpt device (typically in the .dts file 29 * to the device tree node for the gpt device (typically in the .dts file
@@ -46,17 +52,24 @@
46 * the output mode. This driver does not change the output mode setting. 52 * the output mode. This driver does not change the output mode setting.
47 */ 53 */
48 54
55#include <linux/device.h>
49#include <linux/irq.h> 56#include <linux/irq.h>
50#include <linux/interrupt.h> 57#include <linux/interrupt.h>
51#include <linux/io.h> 58#include <linux/io.h>
59#include <linux/list.h>
60#include <linux/mutex.h>
52#include <linux/of.h> 61#include <linux/of.h>
53#include <linux/of_platform.h> 62#include <linux/of_platform.h>
54#include <linux/of_gpio.h> 63#include <linux/of_gpio.h>
55#include <linux/kernel.h> 64#include <linux/kernel.h>
65#include <linux/watchdog.h>
66#include <linux/miscdevice.h>
67#include <linux/uaccess.h>
68#include <asm/div64.h>
56#include <asm/mpc52xx.h> 69#include <asm/mpc52xx.h>
57 70
58MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); 71MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
59MODULE_AUTHOR("Sascha Hauer, Grant Likely"); 72MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
60MODULE_LICENSE("GPL"); 73MODULE_LICENSE("GPL");
61 74
62/** 75/**
@@ -66,18 +79,27 @@ MODULE_LICENSE("GPL");
66 * @lock: spinlock to coordinate between different functions. 79 * @lock: spinlock to coordinate between different functions.
67 * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled 80 * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
68 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported 81 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
82 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
83 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
84 * if the timer is actively used as wdt which blocks gpt functions
69 */ 85 */
70struct mpc52xx_gpt_priv { 86struct mpc52xx_gpt_priv {
87 struct list_head list; /* List of all GPT devices */
71 struct device *dev; 88 struct device *dev;
72 struct mpc52xx_gpt __iomem *regs; 89 struct mpc52xx_gpt __iomem *regs;
73 spinlock_t lock; 90 spinlock_t lock;
74 struct irq_host *irqhost; 91 struct irq_host *irqhost;
92 u32 ipb_freq;
93 u8 wdt_mode;
75 94
76#if defined(CONFIG_GPIOLIB) 95#if defined(CONFIG_GPIOLIB)
77 struct of_gpio_chip of_gc; 96 struct of_gpio_chip of_gc;
78#endif 97#endif
79}; 98};
80 99
100LIST_HEAD(mpc52xx_gpt_list);
101DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
102
81#define MPC52xx_GPT_MODE_MS_MASK (0x07) 103#define MPC52xx_GPT_MODE_MS_MASK (0x07)
82#define MPC52xx_GPT_MODE_MS_IC (0x01) 104#define MPC52xx_GPT_MODE_MS_IC (0x01)
83#define MPC52xx_GPT_MODE_MS_OC (0x02) 105#define MPC52xx_GPT_MODE_MS_OC (0x02)
@@ -88,15 +110,25 @@ struct mpc52xx_gpt_priv {
88#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) 110#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
89#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) 111#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
90 112
113#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
114#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
115#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
91#define MPC52xx_GPT_MODE_IRQ_EN (0x0100) 116#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
117#define MPC52xx_GPT_MODE_WDT_EN (0x8000)
92 118
93#define MPC52xx_GPT_MODE_ICT_MASK (0x030000) 119#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
94#define MPC52xx_GPT_MODE_ICT_RISING (0x010000) 120#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
95#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) 121#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
96#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) 122#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
97 123
124#define MPC52xx_GPT_MODE_WDT_PING (0xa5)
125
98#define MPC52xx_GPT_STATUS_IRQMASK (0x000f) 126#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
99 127
128#define MPC52xx_GPT_CAN_WDT (1 << 0)
129#define MPC52xx_GPT_IS_WDT (1 << 1)
130
131
100/* --------------------------------------------------------------------- 132/* ---------------------------------------------------------------------
101 * Cascaded interrupt controller hooks 133 * Cascaded interrupt controller hooks
102 */ 134 */
@@ -149,7 +181,7 @@ static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
149} 181}
150 182
151static struct irq_chip mpc52xx_gpt_irq_chip = { 183static struct irq_chip mpc52xx_gpt_irq_chip = {
152 .typename = "MPC52xx GPT", 184 .name = "MPC52xx GPT",
153 .unmask = mpc52xx_gpt_irq_unmask, 185 .unmask = mpc52xx_gpt_irq_unmask,
154 .mask = mpc52xx_gpt_irq_mask, 186 .mask = mpc52xx_gpt_irq_mask,
155 .ack = mpc52xx_gpt_irq_ack, 187 .ack = mpc52xx_gpt_irq_ack,
@@ -182,7 +214,7 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
182} 214}
183 215
184static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, 216static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
185 u32 *intspec, unsigned int intsize, 217 const u32 *intspec, unsigned int intsize,
186 irq_hw_number_t *out_hwirq, 218 irq_hw_number_t *out_hwirq,
187 unsigned int *out_flags) 219 unsigned int *out_flags)
188{ 220{
@@ -190,7 +222,7 @@ static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
190 222
191 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); 223 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
192 224
193 if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) { 225 if ((intsize < 1) || (intspec[0] > 3)) {
194 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name); 226 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
195 return -EINVAL; 227 return -EINVAL;
196 } 228 }
@@ -211,13 +243,11 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
211{ 243{
212 int cascade_virq; 244 int cascade_virq;
213 unsigned long flags; 245 unsigned long flags;
214 246 u32 mode;
215 /* Only setup cascaded IRQ if device tree claims the GPT is
216 * an interrupt controller */
217 if (!of_find_property(node, "interrupt-controller", NULL))
218 return;
219 247
220 cascade_virq = irq_of_parse_and_map(node, 0); 248 cascade_virq = irq_of_parse_and_map(node, 0);
249 if (!cascade_virq)
250 return;
221 251
222 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1, 252 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
223 &mpc52xx_gpt_irq_ops, -1); 253 &mpc52xx_gpt_irq_ops, -1);
@@ -227,14 +257,16 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
227 } 257 }
228 258
229 gpt->irqhost->host_data = gpt; 259 gpt->irqhost->host_data = gpt;
230
231 set_irq_data(cascade_virq, gpt); 260 set_irq_data(cascade_virq, gpt);
232 set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); 261 set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
233 262
234 /* Set to Input Capture mode */ 263 /* If the GPT is currently disabled, then change it to be in Input
264 * Capture mode. If the mode is non-zero, then the pin could be
265 * already in use for something. */
235 spin_lock_irqsave(&gpt->lock, flags); 266 spin_lock_irqsave(&gpt->lock, flags);
236 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, 267 mode = in_be32(&gpt->regs->mode);
237 MPC52xx_GPT_MODE_MS_IC); 268 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
269 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
238 spin_unlock_irqrestore(&gpt->lock, flags); 270 spin_unlock_irqrestore(&gpt->lock, flags);
239 271
240 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); 272 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
@@ -335,6 +367,354 @@ static void
335mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } 367mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
336#endif /* defined(CONFIG_GPIOLIB) */ 368#endif /* defined(CONFIG_GPIOLIB) */
337 369
370/***********************************************************************
371 * Timer API
372 */
373
374/**
375 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
376 * @irq: irq of timer.
377 */
378struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
379{
380 struct mpc52xx_gpt_priv *gpt;
381 struct list_head *pos;
382
383 /* Iterate over the list of timers looking for a matching device */
384 mutex_lock(&mpc52xx_gpt_list_mutex);
385 list_for_each(pos, &mpc52xx_gpt_list) {
386 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
387 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
388 mutex_unlock(&mpc52xx_gpt_list_mutex);
389 return gpt;
390 }
391 }
392 mutex_unlock(&mpc52xx_gpt_list_mutex);
393
394 return NULL;
395}
396EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
397
398static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
399 int continuous, int as_wdt)
400{
401 u32 clear, set;
402 u64 clocks;
403 u32 prescale;
404 unsigned long flags;
405
406 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
407 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
408 if (as_wdt) {
409 clear |= MPC52xx_GPT_MODE_IRQ_EN;
410 set |= MPC52xx_GPT_MODE_WDT_EN;
411 } else if (continuous)
412 set |= MPC52xx_GPT_MODE_CONTINUOUS;
413
414 /* Determine the number of clocks in the requested period. 64 bit
415 * arithmatic is done here to preserve the precision until the value
416 * is scaled back down into the u32 range. Period is in 'ns', bus
417 * frequency is in Hz. */
418 clocks = period * (u64)gpt->ipb_freq;
419 do_div(clocks, 1000000000); /* Scale it down to ns range */
420
421 /* This device cannot handle a clock count greater than 32 bits */
422 if (clocks > 0xffffffff)
423 return -EINVAL;
424
425 /* Calculate the prescaler and count values from the clocks value.
426 * 'clocks' is the number of clock ticks in the period. The timer
427 * has 16 bit precision and a 16 bit prescaler. Prescaler is
428 * calculated by integer dividing the clocks by 0x10000 (shifting
429 * down 16 bits) to obtain the smallest possible divisor for clocks
430 * to get a 16 bit count value.
431 *
432 * Note: the prescale register is '1' based, not '0' based. ie. a
433 * value of '1' means divide the clock by one. 0xffff divides the
434 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
435 * around and divides by 0x10000. That is why prescale must be
436 * a u32 variable, not a u16, for this calculation. */
437 prescale = (clocks >> 16) + 1;
438 do_div(clocks, prescale);
439 if (clocks > 0xffff) {
440 pr_err("calculation error; prescale:%x clocks:%llx\n",
441 prescale, clocks);
442 return -EINVAL;
443 }
444
445 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
446 spin_lock_irqsave(&gpt->lock, flags);
447 if (as_wdt)
448 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
449 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
450 spin_unlock_irqrestore(&gpt->lock, flags);
451 return -EBUSY;
452 }
453 out_be32(&gpt->regs->count, prescale << 16 | clocks);
454 clrsetbits_be32(&gpt->regs->mode, clear, set);
455 spin_unlock_irqrestore(&gpt->lock, flags);
456
457 return 0;
458}
459
460/**
461 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
462 * @gpt: Pointer to gpt private data structure
463 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
464 * @continuous: set to 1 to make timer continuous free running
465 *
466 * An interrupt will be generated every time the timer fires
467 */
468int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
469 int continuous)
470{
471 return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
472}
473EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
474
475/**
476 * mpc52xx_gpt_stop_timer - Stop a gpt
477 * @gpt: Pointer to gpt private data structure
478 *
479 * Returns an error if attempting to stop a wdt
480 */
481int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
482{
483 unsigned long flags;
484
485 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
486 spin_lock_irqsave(&gpt->lock, flags);
487 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
488 spin_unlock_irqrestore(&gpt->lock, flags);
489 return -EBUSY;
490 }
491
492 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
493 spin_unlock_irqrestore(&gpt->lock, flags);
494 return 0;
495}
496EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
497
498/**
499 * mpc52xx_gpt_timer_period - Read the timer period
500 * @gpt: Pointer to gpt private data structure
501 *
502 * Returns the timer period in ns
503 */
504u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
505{
506 u64 period;
507 u64 prescale;
508 unsigned long flags;
509
510 spin_lock_irqsave(&gpt->lock, flags);
511 period = in_be32(&gpt->regs->count);
512 spin_unlock_irqrestore(&gpt->lock, flags);
513
514 prescale = period >> 16;
515 period &= 0xffff;
516 if (prescale == 0)
517 prescale = 0x10000;
518 period = period * prescale * 1000000000ULL;
519 do_div(period, (u64)gpt->ipb_freq);
520 return period;
521}
522EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
523
524#if defined(CONFIG_MPC5200_WDT)
525/***********************************************************************
526 * Watchdog API for gpt0
527 */
528
529#define WDT_IDENTITY "mpc52xx watchdog on GPT0"
530
531/* wdt_is_active stores wether or not the /dev/watchdog device is opened */
532static unsigned long wdt_is_active;
533
534/* wdt-capable gpt */
535static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
536
537/* low-level wdt functions */
538static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
539{
540 unsigned long flags;
541
542 spin_lock_irqsave(&gpt_wdt->lock, flags);
543 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
544 spin_unlock_irqrestore(&gpt_wdt->lock, flags);
545}
546
547/* wdt misc device api */
548static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
549 size_t len, loff_t *ppos)
550{
551 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
552 mpc52xx_gpt_wdt_ping(gpt_wdt);
553 return 0;
554}
555
556static struct watchdog_info mpc5200_wdt_info = {
557 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
558 .identity = WDT_IDENTITY,
559};
560
561static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
562 unsigned long arg)
563{
564 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
565 int __user *data = (int __user *)arg;
566 int timeout;
567 u64 real_timeout;
568 int ret = 0;
569
570 switch (cmd) {
571 case WDIOC_GETSUPPORT:
572 ret = copy_to_user(data, &mpc5200_wdt_info,
573 sizeof(mpc5200_wdt_info));
574 if (ret)
575 ret = -EFAULT;
576 break;
577
578 case WDIOC_GETSTATUS:
579 case WDIOC_GETBOOTSTATUS:
580 ret = put_user(0, data);
581 break;
582
583 case WDIOC_KEEPALIVE:
584 mpc52xx_gpt_wdt_ping(gpt_wdt);
585 break;
586
587 case WDIOC_SETTIMEOUT:
588 ret = get_user(timeout, data);
589 if (ret)
590 break;
591 real_timeout = (u64) timeout * 1000000000ULL;
592 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
593 if (ret)
594 break;
595 /* fall through and return the timeout */
596
597 case WDIOC_GETTIMEOUT:
598 /* we need to round here as to avoid e.g. the following
599 * situation:
600 * - timeout requested is 1 second;
601 * - real timeout @33MHz is 999997090ns
602 * - the int divide by 10^9 will return 0.
603 */
604 real_timeout =
605 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
606 do_div(real_timeout, 1000000000ULL);
607 timeout = (int) real_timeout;
608 ret = put_user(timeout, data);
609 break;
610
611 default:
612 ret = -ENOTTY;
613 }
614 return ret;
615}
616
617static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
618{
619 int ret;
620
621 /* sanity check */
622 if (!mpc52xx_gpt_wdt)
623 return -ENODEV;
624
625 /* /dev/watchdog can only be opened once */
626 if (test_and_set_bit(0, &wdt_is_active))
627 return -EBUSY;
628
629 /* Set and activate the watchdog with 30 seconds timeout */
630 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
631 0, 1);
632 if (ret) {
633 clear_bit(0, &wdt_is_active);
634 return ret;
635 }
636
637 file->private_data = mpc52xx_gpt_wdt;
638 return nonseekable_open(inode, file);
639}
640
641static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
642{
643 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
644#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
645 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
646 unsigned long flags;
647
648 spin_lock_irqsave(&gpt_wdt->lock, flags);
649 clrbits32(&gpt_wdt->regs->mode,
650 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
651 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
652 spin_unlock_irqrestore(&gpt_wdt->lock, flags);
653#endif
654 clear_bit(0, &wdt_is_active);
655 return 0;
656}
657
658
659static const struct file_operations mpc52xx_wdt_fops = {
660 .owner = THIS_MODULE,
661 .llseek = no_llseek,
662 .write = mpc52xx_wdt_write,
663 .unlocked_ioctl = mpc52xx_wdt_ioctl,
664 .open = mpc52xx_wdt_open,
665 .release = mpc52xx_wdt_release,
666};
667
668static struct miscdevice mpc52xx_wdt_miscdev = {
669 .minor = WATCHDOG_MINOR,
670 .name = "watchdog",
671 .fops = &mpc52xx_wdt_fops,
672};
673
674static int __devinit mpc52xx_gpt_wdt_init(void)
675{
676 int err;
677
678 /* try to register the watchdog misc device */
679 err = misc_register(&mpc52xx_wdt_miscdev);
680 if (err)
681 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
682 else
683 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
684 return err;
685}
686
687static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
688 const u32 *period)
689{
690 u64 real_timeout;
691
692 /* remember the gpt for the wdt operation */
693 mpc52xx_gpt_wdt = gpt;
694
695 /* configure the wdt if the device tree contained a timeout */
696 if (!period || *period == 0)
697 return 0;
698
699 real_timeout = (u64) *period * 1000000000ULL;
700 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
701 dev_warn(gpt->dev, "starting as wdt failed\n");
702 else
703 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
704 return 0;
705}
706
707#else
708
709static int __devinit mpc52xx_gpt_wdt_init(void)
710{
711 return 0;
712}
713
714#define mpc52xx_gpt_wdt_setup(x, y) (0)
715
716#endif /* CONFIG_MPC5200_WDT */
717
338/* --------------------------------------------------------------------- 718/* ---------------------------------------------------------------------
339 * of_platform bus binding code 719 * of_platform bus binding code
340 */ 720 */
@@ -349,6 +729,7 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
349 729
350 spin_lock_init(&gpt->lock); 730 spin_lock_init(&gpt->lock);
351 gpt->dev = &ofdev->dev; 731 gpt->dev = &ofdev->dev;
732 gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->node);
352 gpt->regs = of_iomap(ofdev->node, 0); 733 gpt->regs = of_iomap(ofdev->node, 0);
353 if (!gpt->regs) { 734 if (!gpt->regs) {
354 kfree(gpt); 735 kfree(gpt);
@@ -360,6 +741,26 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
360 mpc52xx_gpt_gpio_setup(gpt, ofdev->node); 741 mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
361 mpc52xx_gpt_irq_setup(gpt, ofdev->node); 742 mpc52xx_gpt_irq_setup(gpt, ofdev->node);
362 743
744 mutex_lock(&mpc52xx_gpt_list_mutex);
745 list_add(&gpt->list, &mpc52xx_gpt_list);
746 mutex_unlock(&mpc52xx_gpt_list_mutex);
747
748 /* check if this device could be a watchdog */
749 if (of_get_property(ofdev->node, "fsl,has-wdt", NULL) ||
750 of_get_property(ofdev->node, "has-wdt", NULL)) {
751 const u32 *on_boot_wdt;
752
753 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
754 on_boot_wdt = of_get_property(ofdev->node, "fsl,wdt-on-boot",
755 NULL);
756 if (on_boot_wdt) {
757 dev_info(gpt->dev, "used as watchdog\n");
758 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
759 } else
760 dev_info(gpt->dev, "can function as watchdog\n");
761 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
762 }
763
363 return 0; 764 return 0;
364} 765}
365 766
@@ -394,3 +795,4 @@ static int __init mpc52xx_gpt_init(void)
394 795
395/* Make sure GPIOs and IRQs get set up before anyone tries to use them */ 796/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
396subsys_initcall(mpc52xx_gpt_init); 797subsys_initcall(mpc52xx_gpt_init);
798device_initcall(mpc52xx_gpt_wdt_init);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
new file mode 100644
index 000000000000..929d017535a3
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -0,0 +1,560 @@
1/*
2 * LocalPlus Bus FIFO driver for the Freescale MPC52xx.
3 *
4 * Copyright (C) 2009 Secret Lab Technologies Ltd.
5 *
6 * This file is released under the GPLv2
7 *
8 * Todo:
9 * - Add support for multiple requests to be queued.
10 */
11
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16#include <linux/spinlock.h>
17#include <asm/io.h>
18#include <asm/prom.h>
19#include <asm/mpc52xx.h>
20#include <asm/time.h>
21
22#include <sysdev/bestcomm/bestcomm.h>
23#include <sysdev/bestcomm/bestcomm_priv.h>
24#include <sysdev/bestcomm/gen_bd.h>
25
26MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
27MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
28MODULE_LICENSE("GPL");
29
30#define LPBFIFO_REG_PACKET_SIZE (0x00)
31#define LPBFIFO_REG_START_ADDRESS (0x04)
32#define LPBFIFO_REG_CONTROL (0x08)
33#define LPBFIFO_REG_ENABLE (0x0C)
34#define LPBFIFO_REG_BYTES_DONE_STATUS (0x14)
35#define LPBFIFO_REG_FIFO_DATA (0x40)
36#define LPBFIFO_REG_FIFO_STATUS (0x44)
37#define LPBFIFO_REG_FIFO_CONTROL (0x48)
38#define LPBFIFO_REG_FIFO_ALARM (0x4C)
39
40struct mpc52xx_lpbfifo {
41 struct device *dev;
42 phys_addr_t regs_phys;
43 void __iomem *regs;
44 int irq;
45 spinlock_t lock;
46
47 struct bcom_task *bcom_tx_task;
48 struct bcom_task *bcom_rx_task;
49 struct bcom_task *bcom_cur_task;
50
51 /* Current state data */
52 struct mpc52xx_lpbfifo_request *req;
53 int dma_irqs_enabled;
54};
55
56/* The MPC5200 has only one fifo, so only need one instance structure */
57static struct mpc52xx_lpbfifo lpbfifo;
58
59/**
60 * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transfered
61 */
62static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req)
63{
64 size_t transfer_size = req->size - req->pos;
65 struct bcom_bd *bd;
66 void __iomem *reg;
67 u32 *data;
68 int i;
69 int bit_fields;
70 int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
71 int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
72 int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
73
74 /* Set and clear the reset bits; is good practice in User Manual */
75 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
76
77 /* set master enable bit */
78 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000001);
79 if (!dma) {
80 /* While the FIFO can be setup for transfer sizes as large as
81 * 16M-1, the FIFO itself is only 512 bytes deep and it does
82 * not generate interrupts for FIFO full events (only transfer
83 * complete will raise an IRQ). Therefore when not using
84 * Bestcomm to drive the FIFO it needs to either be polled, or
85 * transfers need to constrained to the size of the fifo.
86 *
87 * This driver restricts the size of the transfer
88 */
89 if (transfer_size > 512)
90 transfer_size = 512;
91
92 /* Load the FIFO with data */
93 if (write) {
94 reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
95 data = req->data + req->pos;
96 for (i = 0; i < transfer_size; i += 4)
97 out_be32(reg, *data++);
98 }
99
100 /* Unmask both error and completion irqs */
101 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000301);
102 } else {
103 /* Choose the correct direction
104 *
105 * Configure the watermarks so DMA will always complete correctly.
106 * It may be worth experimenting with the ALARM value to see if
107 * there is a performance impacit. However, if it is wrong there
108 * is a risk of DMA not transferring the last chunk of data
109 */
110 if (write) {
111 out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1e4);
112 out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7);
113 lpbfifo.bcom_cur_task = lpbfifo.bcom_tx_task;
114 } else {
115 out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1ff);
116 out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0);
117 lpbfifo.bcom_cur_task = lpbfifo.bcom_rx_task;
118
119 if (poll_dma) {
120 if (lpbfifo.dma_irqs_enabled) {
121 disable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
122 lpbfifo.dma_irqs_enabled = 0;
123 }
124 } else {
125 if (!lpbfifo.dma_irqs_enabled) {
126 enable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
127 lpbfifo.dma_irqs_enabled = 1;
128 }
129 }
130 }
131
132 bd = bcom_prepare_next_buffer(lpbfifo.bcom_cur_task);
133 bd->status = transfer_size;
134 if (!write) {
135 /*
136 * In the DMA read case, the DMA doesn't complete,
137 * possibly due to incorrect watermarks in the ALARM
138 * and CONTROL regs. For now instead of trying to
139 * determine the right watermarks that will make this
140 * work, just increase the number of bytes the FIFO is
141 * expecting.
142 *
143 * When submitting another operation, the FIFO will get
144 * reset, so the condition of the FIFO waiting for a
145 * non-existent 4 bytes will get cleared.
146 */
147 transfer_size += 4; /* BLECH! */
148 }
149 bd->data[0] = req->data_phys + req->pos;
150 bcom_submit_next_buffer(lpbfifo.bcom_cur_task, NULL);
151
152 /* error irq & master enabled bit */
153 bit_fields = 0x00000201;
154
155 /* Unmask irqs */
156 if (write && (!poll_dma))
157 bit_fields |= 0x00000100; /* completion irq too */
158 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, bit_fields);
159 }
160
161 /* Set transfer size, width, chip select and READ mode */
162 out_be32(lpbfifo.regs + LPBFIFO_REG_START_ADDRESS,
163 req->offset + req->pos);
164 out_be32(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, transfer_size);
165
166 bit_fields = req->cs << 24 | 0x000008;
167 if (!write)
168 bit_fields |= 0x010000; /* read mode */
169 out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields);
170
171 /* Kick it off */
172 out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
173 if (dma)
174 bcom_enable(lpbfifo.bcom_cur_task);
175}
176
177/**
178 * mpc52xx_lpbfifo_irq - IRQ handler for LPB FIFO
179 *
180 * On transmit, the dma completion irq triggers before the fifo completion
181 * triggers. Handle the dma completion here instead of the LPB FIFO Bestcomm
182 * task completion irq becuase everyting is not really done until the LPB FIFO
183 * completion irq triggers.
184 *
185 * In other words:
186 * For DMA, on receive, the "Fat Lady" is the bestcom completion irq. on
187 * transmit, the fifo completion irq is the "Fat Lady". The opera (or in this
188 * case the DMA/FIFO operation) is not finished until the "Fat Lady" sings.
189 *
190 * Reasons for entering this routine:
191 * 1) PIO mode rx and tx completion irq
192 * 2) DMA interrupt mode tx completion irq
193 * 3) DMA polled mode tx
194 *
195 * Exit conditions:
196 * 1) Transfer aborted
197 * 2) FIFO complete without DMA; more data to do
198 * 3) FIFO complete without DMA; all data transfered
199 * 4) FIFO complete using DMA
200 *
201 * Condition 1 can occur regardless of whether or not DMA is used.
202 * It requires executing the callback to report the error and exiting
203 * immediately.
204 *
205 * Condition 2 requires programming the FIFO with the next block of data
206 *
207 * Condition 3 requires executing the callback to report completion
208 *
209 * Condition 4 means the same as 3, except that we also retrieve the bcom
210 * buffer so DMA doesn't get clogged up.
211 *
212 * To make things trickier, the spinlock must be dropped before
213 * executing the callback, otherwise we could end up with a deadlock
214 * or nested spinlock condition. The out path is non-trivial, so
215 * extra fiddling is done to make sure all paths lead to the same
216 * outbound code.
217 */
218static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id)
219{
220 struct mpc52xx_lpbfifo_request *req;
221 u32 status = in_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
222 void __iomem *reg;
223 u32 *data;
224 int count, i;
225 int do_callback = 0;
226 u32 ts;
227 unsigned long flags;
228 int dma, write, poll_dma;
229
230 spin_lock_irqsave(&lpbfifo.lock, flags);
231 ts = get_tbl();
232
233 req = lpbfifo.req;
234 if (!req) {
235 spin_unlock_irqrestore(&lpbfifo.lock, flags);
236 pr_err("bogus LPBFIFO IRQ\n");
237 return IRQ_HANDLED;
238 }
239
240 dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
241 write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
242 poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
243
244 if (dma && !write) {
245 spin_unlock_irqrestore(&lpbfifo.lock, flags);
246 pr_err("bogus LPBFIFO IRQ (dma and not writting)\n");
247 return IRQ_HANDLED;
248 }
249
250 if ((status & 0x01) == 0) {
251 goto out;
252 }
253
254 /* check abort bit */
255 if (status & 0x10) {
256 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
257 do_callback = 1;
258 goto out;
259 }
260
261 /* Read result from hardware */
262 count = in_be32(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
263 count &= 0x00ffffff;
264
265 if (!dma && !write) {
266 /* copy the data out of the FIFO */
267 reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
268 data = req->data + req->pos;
269 for (i = 0; i < count; i += 4)
270 *data++ = in_be32(reg);
271 }
272
273 /* Update transfer position and count */
274 req->pos += count;
275
276 /* Decide what to do next */
277 if (req->size - req->pos)
278 mpc52xx_lpbfifo_kick(req); /* more work to do */
279 else
280 do_callback = 1;
281
282 out:
283 /* Clear the IRQ */
284 out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01);
285
286 if (dma && (status & 0x11)) {
287 /*
288 * Count the DMA as complete only when the FIFO completion
289 * status or abort bits are set.
290 *
291 * (status & 0x01) should always be the case except sometimes
292 * when using polled DMA.
293 *
294 * (status & 0x10) {transfer aborted}: This case needs more
295 * testing.
296 */
297 bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
298 }
299 req->last_byte = ((u8 *)req->data)[req->size - 1];
300
301 /* When the do_callback flag is set; it means the transfer is finished
302 * so set the FIFO as idle */
303 if (do_callback)
304 lpbfifo.req = NULL;
305
306 if (irq != 0) /* don't increment on polled case */
307 req->irq_count++;
308
309 req->irq_ticks += get_tbl() - ts;
310 spin_unlock_irqrestore(&lpbfifo.lock, flags);
311
312 /* Spinlock is released; it is now safe to call the callback */
313 if (do_callback && req->callback)
314 req->callback(req);
315
316 return IRQ_HANDLED;
317}
318
319/**
320 * mpc52xx_lpbfifo_bcom_irq - IRQ handler for LPB FIFO Bestcomm task
321 *
322 * Only used when receiving data.
323 */
324static irqreturn_t mpc52xx_lpbfifo_bcom_irq(int irq, void *dev_id)
325{
326 struct mpc52xx_lpbfifo_request *req;
327 unsigned long flags;
328 u32 status;
329 u32 ts;
330
331 spin_lock_irqsave(&lpbfifo.lock, flags);
332 ts = get_tbl();
333
334 req = lpbfifo.req;
335 if (!req || (req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA)) {
336 spin_unlock_irqrestore(&lpbfifo.lock, flags);
337 return IRQ_HANDLED;
338 }
339
340 if (irq != 0) /* don't increment on polled case */
341 req->irq_count++;
342
343 if (!bcom_buffer_done(lpbfifo.bcom_cur_task)) {
344 spin_unlock_irqrestore(&lpbfifo.lock, flags);
345
346 req->buffer_not_done_cnt++;
347 if ((req->buffer_not_done_cnt % 1000) == 0)
348 pr_err("transfer stalled\n");
349
350 return IRQ_HANDLED;
351 }
352
353 bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
354
355 req->last_byte = ((u8 *)req->data)[req->size - 1];
356
357 req->pos = status & 0x00ffffff;
358
359 /* Mark the FIFO as idle */
360 lpbfifo.req = NULL;
361
362 /* Release the lock before calling out to the callback. */
363 req->irq_ticks += get_tbl() - ts;
364 spin_unlock_irqrestore(&lpbfifo.lock, flags);
365
366 if (req->callback)
367 req->callback(req);
368
369 return IRQ_HANDLED;
370}
371
372/**
373 * mpc52xx_lpbfifo_bcom_poll - Poll for DMA completion
374 */
375void mpc52xx_lpbfifo_poll(void)
376{
377 struct mpc52xx_lpbfifo_request *req = lpbfifo.req;
378 int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
379 int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
380
381 /*
382 * For more information, see comments on the "Fat Lady"
383 */
384 if (dma && write)
385 mpc52xx_lpbfifo_irq(0, NULL);
386 else
387 mpc52xx_lpbfifo_bcom_irq(0, NULL);
388}
389EXPORT_SYMBOL(mpc52xx_lpbfifo_poll);
390
391/**
392 * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request.
393 * @req: Pointer to request structure
394 */
395int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req)
396{
397 unsigned long flags;
398
399 if (!lpbfifo.regs)
400 return -ENODEV;
401
402 spin_lock_irqsave(&lpbfifo.lock, flags);
403
404 /* If the req pointer is already set, then a transfer is in progress */
405 if (lpbfifo.req) {
406 spin_unlock_irqrestore(&lpbfifo.lock, flags);
407 return -EBUSY;
408 }
409
410 /* Setup the transfer */
411 lpbfifo.req = req;
412 req->irq_count = 0;
413 req->irq_ticks = 0;
414 req->buffer_not_done_cnt = 0;
415 req->pos = 0;
416
417 mpc52xx_lpbfifo_kick(req);
418 spin_unlock_irqrestore(&lpbfifo.lock, flags);
419 return 0;
420}
421EXPORT_SYMBOL(mpc52xx_lpbfifo_submit);
422
423void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
424{
425 unsigned long flags;
426
427 spin_lock_irqsave(&lpbfifo.lock, flags);
428 if (lpbfifo.req == req) {
429 /* Put it into reset and clear the state */
430 bcom_gen_bd_rx_reset(lpbfifo.bcom_rx_task);
431 bcom_gen_bd_tx_reset(lpbfifo.bcom_tx_task);
432 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
433 lpbfifo.req = NULL;
434 }
435 spin_unlock_irqrestore(&lpbfifo.lock, flags);
436}
437EXPORT_SYMBOL(mpc52xx_lpbfifo_abort);
438
439static int __devinit
440mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match)
441{
442 struct resource res;
443 int rc = -ENOMEM;
444
445 if (lpbfifo.dev != NULL)
446 return -ENOSPC;
447
448 lpbfifo.irq = irq_of_parse_and_map(op->node, 0);
449 if (!lpbfifo.irq)
450 return -ENODEV;
451
452 if (of_address_to_resource(op->node, 0, &res))
453 return -ENODEV;
454 lpbfifo.regs_phys = res.start;
455 lpbfifo.regs = of_iomap(op->node, 0);
456 if (!lpbfifo.regs)
457 return -ENOMEM;
458
459 spin_lock_init(&lpbfifo.lock);
460
461 /* Put FIFO into reset */
462 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
463
464 /* Register the interrupt handler */
465 rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0,
466 "mpc52xx-lpbfifo", &lpbfifo);
467 if (rc)
468 goto err_irq;
469
470 /* Request the Bestcomm receive (fifo --> memory) task and IRQ */
471 lpbfifo.bcom_rx_task =
472 bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
473 BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC,
474 16*1024*1024);
475 if (!lpbfifo.bcom_rx_task)
476 goto err_bcom_rx;
477
478 rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task),
479 mpc52xx_lpbfifo_bcom_irq, 0,
480 "mpc52xx-lpbfifo-rx", &lpbfifo);
481 if (rc)
482 goto err_bcom_rx_irq;
483
484 /* Request the Bestcomm transmit (memory --> fifo) task and IRQ */
485 lpbfifo.bcom_tx_task =
486 bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
487 BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC);
488 if (!lpbfifo.bcom_tx_task)
489 goto err_bcom_tx;
490
491 lpbfifo.dev = &op->dev;
492 return 0;
493
494 err_bcom_tx:
495 free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
496 err_bcom_rx_irq:
497 bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
498 err_bcom_rx:
499 err_irq:
500 iounmap(lpbfifo.regs);
501 lpbfifo.regs = NULL;
502
503 dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n");
504 return -ENODEV;
505}
506
507
508static int __devexit mpc52xx_lpbfifo_remove(struct of_device *op)
509{
510 if (lpbfifo.dev != &op->dev)
511 return 0;
512
513 /* Put FIFO in reset */
514 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
515
516 /* Release the bestcomm transmit task */
517 free_irq(bcom_get_task_irq(lpbfifo.bcom_tx_task), &lpbfifo);
518 bcom_gen_bd_tx_release(lpbfifo.bcom_tx_task);
519
520 /* Release the bestcomm receive task */
521 free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
522 bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
523
524 free_irq(lpbfifo.irq, &lpbfifo);
525 iounmap(lpbfifo.regs);
526 lpbfifo.regs = NULL;
527 lpbfifo.dev = NULL;
528
529 return 0;
530}
531
532static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = {
533 { .compatible = "fsl,mpc5200-lpbfifo", },
534 {},
535};
536
537static struct of_platform_driver mpc52xx_lpbfifo_driver = {
538 .owner = THIS_MODULE,
539 .name = "mpc52xx-lpbfifo",
540 .match_table = mpc52xx_lpbfifo_match,
541 .probe = mpc52xx_lpbfifo_probe,
542 .remove = __devexit_p(mpc52xx_lpbfifo_remove),
543};
544
545/***********************************************************************
546 * Module init/exit
547 */
548static int __init mpc52xx_lpbfifo_init(void)
549{
550 pr_debug("Registering LocalPlus bus FIFO driver\n");
551 return of_register_platform_driver(&mpc52xx_lpbfifo_driver);
552}
553module_init(mpc52xx_lpbfifo_init);
554
555static void __exit mpc52xx_lpbfifo_exit(void)
556{
557 pr_debug("Unregistering LocalPlus bus FIFO driver\n");
558 of_unregister_platform_driver(&mpc52xx_lpbfifo_driver);
559}
560module_exit(mpc52xx_lpbfifo_exit);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 480f806fd0a9..4bf4bf7b063e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -220,7 +220,7 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
220} 220}
221 221
222static struct irq_chip mpc52xx_extirq_irqchip = { 222static struct irq_chip mpc52xx_extirq_irqchip = {
223 .typename = "MPC52xx External", 223 .name = "MPC52xx External",
224 .mask = mpc52xx_extirq_mask, 224 .mask = mpc52xx_extirq_mask,
225 .unmask = mpc52xx_extirq_unmask, 225 .unmask = mpc52xx_extirq_unmask,
226 .ack = mpc52xx_extirq_ack, 226 .ack = mpc52xx_extirq_ack,
@@ -258,7 +258,7 @@ static void mpc52xx_main_unmask(unsigned int virq)
258} 258}
259 259
260static struct irq_chip mpc52xx_main_irqchip = { 260static struct irq_chip mpc52xx_main_irqchip = {
261 .typename = "MPC52xx Main", 261 .name = "MPC52xx Main",
262 .mask = mpc52xx_main_mask, 262 .mask = mpc52xx_main_mask,
263 .mask_ack = mpc52xx_main_mask, 263 .mask_ack = mpc52xx_main_mask,
264 .unmask = mpc52xx_main_unmask, 264 .unmask = mpc52xx_main_unmask,
@@ -291,7 +291,7 @@ static void mpc52xx_periph_unmask(unsigned int virq)
291} 291}
292 292
293static struct irq_chip mpc52xx_periph_irqchip = { 293static struct irq_chip mpc52xx_periph_irqchip = {
294 .typename = "MPC52xx Peripherals", 294 .name = "MPC52xx Peripherals",
295 .mask = mpc52xx_periph_mask, 295 .mask = mpc52xx_periph_mask,
296 .mask_ack = mpc52xx_periph_mask, 296 .mask_ack = mpc52xx_periph_mask,
297 .unmask = mpc52xx_periph_unmask, 297 .unmask = mpc52xx_periph_unmask,
@@ -335,7 +335,7 @@ static void mpc52xx_sdma_ack(unsigned int virq)
335} 335}
336 336
337static struct irq_chip mpc52xx_sdma_irqchip = { 337static struct irq_chip mpc52xx_sdma_irqchip = {
338 .typename = "MPC52xx SDMA", 338 .name = "MPC52xx SDMA",
339 .mask = mpc52xx_sdma_mask, 339 .mask = mpc52xx_sdma_mask,
340 .unmask = mpc52xx_sdma_unmask, 340 .unmask = mpc52xx_sdma_unmask,
341 .ack = mpc52xx_sdma_ack, 341 .ack = mpc52xx_sdma_ack,
@@ -355,7 +355,7 @@ static int mpc52xx_is_extirq(int l1, int l2)
355 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property 355 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
356 */ 356 */
357static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, 357static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
358 u32 *intspec, unsigned int intsize, 358 const u32 *intspec, unsigned int intsize,
359 irq_hw_number_t *out_hwirq, 359 irq_hw_number_t *out_hwirq,
360 unsigned int *out_flags) 360 unsigned int *out_flags)
361{ 361{