12 files changed, 317 insertions, 69 deletions

diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 5b7dd4ea02b5..a242b5d7cbe4 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K)
 BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         /* Calc va and put it in r29 */
         rldicr  r29,r5,28,63-28
         rldicl  r3,r3,0,36
@@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K)
 BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         /* Calc va and put it in r29 */
         rldicr  r29,r5,28,63-28         /* r29 = (vsid << 28) */
         rldicl  r3,r3,0,36              /* r3 = (ea & 0x0fffffff) */
@@ -715,7 +715,7 @@ BEGIN_FTR_SECTION
         andi.   r0,r31,_PAGE_NO_CACHE
         /* If so, bail out and refault as a 4k page */
         bne-    ht64_bail_ok
-END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
         /* Prepare new PTE value (turn access RW into DIRTY, then
          * add BUSY and ACCESSED)
          */
@@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
 BEGIN_FTR_SECTION
         cmpdi   r9,0                    /* check segment size */
         bne     3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         /* Calc va and put it in r29 */
         rldicr  r29,r5,28,63-28
         rldicl  r3,r3,0,36
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 784a400e0781..dfd764896db0 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -50,9 +50,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
         case MMU_PAGE_4K:
                 va &= ~0xffful;
                 va |= ssize << 8;
-                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
-                                               %2)
-                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
+                             : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
                              : "memory");
                 break;
         default:
@@ -61,9 +60,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
                 va |= penc << 12;
                 va |= ssize << 8;
                 va |= 1; /* L */
-                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
-                                               %2)
-                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
+                             : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
                              : "memory");
                 break;
         }
@@ -98,8 +96,8 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
 
 static inline void tlbie(unsigned long va, int psize, int ssize, int local)
 {
-        unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL);
-        int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+        unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
+        int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 
         if (use_local)
                 use_local = mmu_psize_defs[psize].tlbiel;
@@ -503,7 +501,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                 } pte_iterate_hashed_end();
         }
 
-        if (cpu_has_feature(CPU_FTR_TLBIEL) &&
+        if (mmu_has_feature(MMU_FTR_TLBIEL) &&
             mmu_psize_defs[psize].tlbiel && local) {
                 asm volatile("ptesync":::"memory");
                 for (i = 0; i < number; i++) {
@@ -517,7 +515,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                 }
                 asm volatile("ptesync":::"memory");
         } else {
-                int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+                int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 
                 if (lock_tlbie)
                         raw_spin_lock(&native_tlbie_lock);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 58a022d0f463..26b2872b3d00 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -53,6 +53,7 @@
 #include <asm/sections.h>
 #include <asm/spu.h>
 #include <asm/udbg.h>
+#include <asm/code-patching.h>
 
 #ifdef DEBUG
 #define DBG(fmt...) udbg_printf(fmt)
@@ -258,11 +259,11 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
         for (; size >= 4; size -= 4, ++prop) {
                 if (prop[0] == 40) {
                         DBG("1T segment support detected\n");
-                        cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
+                        cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
                         return 1;
                 }
         }
-        cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
+        cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
         return 0;
 }
 
@@ -288,7 +289,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
         if (prop != NULL) {
                 DBG("Page sizes from device-tree:\n");
                 size /= 4;
-                cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
+                cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
                 while(size > 0) {
                         unsigned int shift = prop[0];
                         unsigned int slbenc = prop[1];
@@ -316,7 +317,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
                                 break;
                         case 0x18:
                                 idx = MMU_PAGE_16M;
-                                cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
+                                cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
                                 break;
                         case 0x22:
                                 idx = MMU_PAGE_16G;
@@ -411,7 +412,7 @@ static void __init htab_init_page_sizes(void)
          * Not in the device-tree, let's fallback on known size
          * list for 16M capable GP & GR
          */
-        if (cpu_has_feature(CPU_FTR_16M_PAGE))
+        if (mmu_has_feature(MMU_FTR_16M_PAGE))
                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
                        sizeof(mmu_psize_defaults_gp));
  found:
@@ -441,7 +442,7 @@ static void __init htab_init_page_sizes(void)
                 mmu_vmalloc_psize = MMU_PAGE_64K;
                 if (mmu_linear_psize == MMU_PAGE_4K)
                         mmu_linear_psize = MMU_PAGE_64K;
-                if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
+                if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
                         /*
                          * Don't use 64k pages for ioremap on pSeries, since
                          * that would stop us accessing the HEA ethernet.
@@ -547,15 +548,7 @@ int remove_section_mapping(unsigned long start, unsigned long end)
 }
 #endif /* CONFIG_MEMORY_HOTPLUG */
 
-static inline void make_bl(unsigned int *insn_addr, void *func)
-{
-        unsigned long funcp = *((unsigned long *)func);
-        int offset = funcp - (unsigned long)insn_addr;
-
-        *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
-        flush_icache_range((unsigned long)insn_addr, 4+
-                           (unsigned long)insn_addr);
-}
+#define FUNCTION_TEXT(A)        ((*(unsigned long *)(A)))
 
 static void __init htab_finish_init(void)
 {
@@ -570,16 +563,33 @@ static void __init htab_finish_init(void)
         extern unsigned int *ht64_call_hpte_remove;
         extern unsigned int *ht64_call_hpte_updatepp;
 
-        make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
-        make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
-        make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
-        make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
+        patch_branch(ht64_call_hpte_insert1,
+                FUNCTION_TEXT(ppc_md.hpte_insert),
+                BRANCH_SET_LINK);
+        patch_branch(ht64_call_hpte_insert2,
+                FUNCTION_TEXT(ppc_md.hpte_insert),
+                BRANCH_SET_LINK);
+        patch_branch(ht64_call_hpte_remove,
+                FUNCTION_TEXT(ppc_md.hpte_remove),
+                BRANCH_SET_LINK);
+        patch_branch(ht64_call_hpte_updatepp,
+                FUNCTION_TEXT(ppc_md.hpte_updatepp),
+                BRANCH_SET_LINK);
+
 #endif /* CONFIG_PPC_HAS_HASH_64K */
 
-        make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
-        make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
-        make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
-        make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
+        patch_branch(htab_call_hpte_insert1,
+                FUNCTION_TEXT(ppc_md.hpte_insert),
+                BRANCH_SET_LINK);
+        patch_branch(htab_call_hpte_insert2,
+                FUNCTION_TEXT(ppc_md.hpte_insert),
+                BRANCH_SET_LINK);
+        patch_branch(htab_call_hpte_remove,
+                FUNCTION_TEXT(ppc_md.hpte_remove),
+                BRANCH_SET_LINK);
+        patch_branch(htab_call_hpte_updatepp,
+                FUNCTION_TEXT(ppc_md.hpte_updatepp),
+                BRANCH_SET_LINK);
 }
 
 static void __init htab_initialize(void)
@@ -598,7 +608,7 @@ static void __init htab_initialize(void)
         /* Initialize page sizes */
         htab_init_page_sizes();
 
-        if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+        if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
                 printk(KERN_INFO "Using 1TB segments\n");
@@ -739,7 +749,7 @@ void __init early_init_mmu(void)
 
         /* Initialize stab / SLB management except on iSeries
          */
-        if (cpu_has_feature(CPU_FTR_SLB))
+        if (mmu_has_feature(MMU_FTR_SLB))
                 slb_initialize();
         else if (!firmware_has_feature(FW_FEATURE_ISERIES))
                 stab_initialize(get_paca()->stab_real);
@@ -756,7 +766,7 @@ void __cpuinit early_init_mmu_secondary(void)
          * in real mode on pSeries and we want a virtual address on
          * iSeries anyway
          */
-        if (cpu_has_feature(CPU_FTR_SLB))
+        if (mmu_has_feature(MMU_FTR_SLB))
                 slb_initialize();
         else
                 stab_initialize(get_paca()->stab_addr);
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 9bb249c3046e..0b9a5c1901b9 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -529,7 +529,7 @@ static int __init hugetlbpage_init(void)
 {
         int psize;
 
-        if (!cpu_has_feature(CPU_FTR_16M_PAGE))
+        if (!mmu_has_feature(MMU_FTR_16M_PAGE))
                 return -ENODEV;
 
         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 2535828aa84b..3bafc3deca6d 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -20,9 +20,205 @@
 #include <linux/idr.h>
 #include <linux/module.h>
 #include <linux/gfp.h>
+#include <linux/slab.h>
 
 #include <asm/mmu_context.h>
 
+#ifdef CONFIG_PPC_ICSWX
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has
+ * no address, and the processor does not perform an MMU access
+ * to authenticate the transaction. The command portion of the
+ * PowerBus COP_REQ transaction includes the LPAR_ID (LPID) and
+ * the coprocessor Process ID (PID), which the coprocessor compares
+ * to the authorized LPID and PID held in the coprocessor, to determine
+ * if the process is authorized to generate the transaction.
+ * The data of the COP_REQ transaction is 128-byte or less and is
+ * placed in cacheable memory on a 128-byte cache line boundary.
+ *
+ * The task to use a coprocessor should use use_cop() to allocate
+ * a coprocessor PID before executing icswx instruction. use_cop()
+ * also enables the coprocessor context switching. Drop_cop() is
+ * used to free the coprocessor PID.
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+
+#define COP_PID_NONE 0
+#define COP_PID_MIN (COP_PID_NONE + 1)
+#define COP_PID_MAX (0xFFFF)
+
+static DEFINE_SPINLOCK(mmu_context_acop_lock);
+static DEFINE_IDA(cop_ida);
+
+void switch_cop(struct mm_struct *next)
+{
+        mtspr(SPRN_PID, next->context.cop_pid);
+        mtspr(SPRN_ACOP, next->context.acop);
+}
+
+static int new_cop_pid(struct ida *ida, int min_id, int max_id,
+                       spinlock_t *lock)
+{
+        int index;
+        int err;
+
+again:
+        if (!ida_pre_get(ida, GFP_KERNEL))
+                return -ENOMEM;
+
+        spin_lock(lock);
+        err = ida_get_new_above(ida, min_id, &index);
+        spin_unlock(lock);
+
+        if (err == -EAGAIN)
+                goto again;
+        else if (err)
+                return err;
+
+        if (index > max_id) {
+                spin_lock(lock);
+                ida_remove(ida, index);
+                spin_unlock(lock);
+                return -ENOMEM;
+        }
+
+        return index;
+}
+
+static void sync_cop(void *arg)
+{
+        struct mm_struct *mm = arg;
+
+        if (mm == current->active_mm)
+                switch_cop(current->active_mm);
+}
+
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise.
+ * The returned PID will be fed to the coprocessor to determine if an
+ * icswx transaction is authenticated.
+ */
+int use_cop(unsigned long acop, struct mm_struct *mm)
+{
+        int ret;
+
+        if (!cpu_has_feature(CPU_FTR_ICSWX))
+                return -ENODEV;
+
+        if (!mm || !acop)
+                return -EINVAL;
+
+        /* We need to make sure mm_users doesn't change */
+        down_read(&mm->mmap_sem);
+        spin_lock(mm->context.cop_lockp);
+
+        if (mm->context.cop_pid == COP_PID_NONE) {
+                ret = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
+                                  &mmu_context_acop_lock);
+                if (ret < 0)
+                        goto out;
+
+                mm->context.cop_pid = ret;
+        }
+        mm->context.acop |= acop;
+
+        sync_cop(mm);
+
+        /*
+         * If this is a threaded process then there might be other threads
+         * running. We need to send an IPI to force them to pick up any
+         * change in PID and ACOP.
+         */
+        if (atomic_read(&mm->mm_users) > 1)
+                smp_call_function(sync_cop, mm, 1);
+
+        ret = mm->context.cop_pid;
+
+out:
+        spin_unlock(mm->context.cop_lockp);
+        up_read(&mm->mmap_sem);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(use_cop);
+
+/**
+ * Stop using a coprocessor.
+ * @acop: mask of coprocessor to be stopped.
+ * @mm: The mm the coprocessor associated with.
+ */
+void drop_cop(unsigned long acop, struct mm_struct *mm)
+{
+        int free_pid = COP_PID_NONE;
+
+        if (!cpu_has_feature(CPU_FTR_ICSWX))
+                return;
+
+        if (WARN_ON_ONCE(!mm))
+                return;
+
+        /* We need to make sure mm_users doesn't change */
+        down_read(&mm->mmap_sem);
+        spin_lock(mm->context.cop_lockp);
+
+        mm->context.acop &= ~acop;
+
+        if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
+                free_pid = mm->context.cop_pid;
+                mm->context.cop_pid = COP_PID_NONE;
+        }
+
+        sync_cop(mm);
+
+        /*
+         * If this is a threaded process then there might be other threads
+         * running. We need to send an IPI to force them to pick up any
+         * change in PID and ACOP.
+         */
+        if (atomic_read(&mm->mm_users) > 1)
+                smp_call_function(sync_cop, mm, 1);
+
+        if (free_pid != COP_PID_NONE) {
+                spin_lock(&mmu_context_acop_lock);
+                ida_remove(&cop_ida, free_pid);
+                spin_unlock(&mmu_context_acop_lock);
+        }
+
+        spin_unlock(mm->context.cop_lockp);
+        up_read(&mm->mmap_sem);
+}
+EXPORT_SYMBOL_GPL(drop_cop);
+
+#endif /* CONFIG_PPC_ICSWX */
+
 static DEFINE_SPINLOCK(mmu_context_lock);
 static DEFINE_IDA(mmu_context_ida);
 
@@ -31,7 +227,6 @@ static DEFINE_IDA(mmu_context_ida);
  * Each segment contains 2^28 bytes.  Each context maps 2^44 bytes,
  * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
  */
-#define NO_CONTEXT      0
 #define MAX_CONTEXT     ((1UL << 19) - 1)
 
 int __init_new_context(void)
@@ -79,6 +274,16 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
                 slice_set_user_psize(mm, mmu_virtual_psize);
         subpage_prot_init_new_context(mm);
         mm->context.id = index;
+#ifdef CONFIG_PPC_ICSWX
+        mm->context.cop_lockp = kmalloc(sizeof(spinlock_t), GFP_KERNEL);
+        if (!mm->context.cop_lockp) {
+                __destroy_context(index);
+                subpage_prot_free(mm);
+                mm->context.id = MMU_NO_CONTEXT;
+                return -ENOMEM;
+        }
+        spin_lock_init(mm->context.cop_lockp);
+#endif /* CONFIG_PPC_ICSWX */
 
         return 0;
 }
@@ -93,7 +298,12 @@ EXPORT_SYMBOL_GPL(__destroy_context);
 
 void destroy_context(struct mm_struct *mm)
 {
+#ifdef CONFIG_PPC_ICSWX
+        drop_cop(mm->context.acop, mm);
+        kfree(mm->context.cop_lockp);
+        mm->context.cop_lockp = NULL;
+#endif /* CONFIG_PPC_ICSWX */
         __destroy_context(mm->context.id);
         subpage_prot_free(mm);
-        mm->context.id = NO_CONTEXT;
+        mm->context.id = MMU_NO_CONTEXT;
 }
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index c0aab52da3a5..336807de550e 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -338,12 +338,14 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                 return NOTIFY_OK;
 
         switch (action) {
-        case CPU_ONLINE:
-        case CPU_ONLINE_FROZEN:
+        case CPU_UP_PREPARE:
+        case CPU_UP_PREPARE_FROZEN:
                 pr_devel("MMU: Allocating stale context map for CPU %d\n", cpu);
                 stale_map[cpu] = kzalloc(CTX_MAP_SIZE, GFP_KERNEL);
                 break;
 #ifdef CONFIG_HOTPLUG_CPU
+        case CPU_UP_CANCELED:
+        case CPU_UP_CANCELED_FROZEN:
         case CPU_DEAD:
         case CPU_DEAD_FROZEN:
                 pr_devel("MMU: Freeing stale context map for CPU %d\n", cpu);
@@ -407,7 +409,17 @@ void __init mmu_context_init(void)
         } else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
                 first_context = 1;
                 last_context = 65535;
-        } else {
+        } else
+#ifdef CONFIG_PPC_BOOK3E_MMU
+        if (mmu_has_feature(MMU_FTR_TYPE_3E)) {
+                u32 mmucfg = mfspr(SPRN_MMUCFG);
+                u32 pid_bits = (mmucfg & MMUCFG_PIDSIZE_MASK)
+                                >> MMUCFG_PIDSIZE_SHIFT;
+                first_context = 1;
+                last_context = (1UL << (pid_bits + 1)) - 1;
+        } else
+#endif
+        {
                 first_context = 1;
                 last_context = 255;
         }
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 5ec1dad2a19d..2164006fe170 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -311,14 +311,13 @@ EXPORT_SYMBOL_GPL(of_node_to_nid);
 static int __init find_min_common_depth(void)
 {
         int depth;
-        struct device_node *rtas_root;
         struct device_node *chosen;
+        struct device_node *root;
         const char *vec5;
 
-        rtas_root = of_find_node_by_path("/rtas");
-
-        if (!rtas_root)
-                return -1;
+        root = of_find_node_by_path("/rtas");
+        if (!root)
+                root = of_find_node_by_path("/");
 
         /*
          * This property is a set of 32-bit integers, each representing
@@ -332,7 +331,7 @@ static int __init find_min_common_depth(void)
          * NUMA boundary and the following are progressively less significant
          * boundaries. There can be more than one level of NUMA.
          */
-        distance_ref_points = of_get_property(rtas_root,
+        distance_ref_points = of_get_property(root,
                                         "ibm,associativity-reference-points",
                                         &distance_ref_points_depth);
 
@@ -376,11 +375,11 @@ static int __init find_min_common_depth(void)
                 distance_ref_points_depth = MAX_DISTANCE_REF_POINTS;
         }
 
-        of_node_put(rtas_root);
+        of_node_put(root);
         return depth;
 
 err:
-        of_node_put(rtas_root);
+        of_node_put(root);
         return -1;
 }
 
@@ -1453,7 +1452,7 @@ int arch_update_cpu_topology(void)
         unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0};
         struct sys_device *sysdev;
 
-        for_each_cpu_mask(cpu, cpu_associativity_changes_mask) {
+        for_each_cpu(cpu,&cpu_associativity_changes_mask) {
                 vphn_get_associativity(cpu, associativity);
                 nid = associativity_to_nid(associativity);
 
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 8dc41c0157fe..51f87956f8f8 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -133,7 +133,15 @@ ioremap(phys_addr_t addr, unsigned long size)
 EXPORT_SYMBOL(ioremap);
 
 void __iomem *
-ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags)
+ioremap_wc(phys_addr_t addr, unsigned long size)
+{
+        return __ioremap_caller(addr, size, _PAGE_NO_CACHE,
+                                __builtin_return_address(0));
+}
+EXPORT_SYMBOL(ioremap_wc);
+
+void __iomem *
+ioremap_prot(phys_addr_t addr, unsigned long size, unsigned long flags)
 {
         /* writeable implies dirty for kernel addresses */
         if (flags & _PAGE_RW)
@@ -152,7 +160,7 @@ ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags)
 
         return __ioremap_caller(addr, size, flags, __builtin_return_address(0));
 }
-EXPORT_SYMBOL(ioremap_flags);
+EXPORT_SYMBOL(ioremap_prot);
 
 void __iomem *
 __ioremap(phys_addr_t addr, unsigned long size, unsigned long flags)
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 88927a05cdc2..6e595f6496d4 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -255,7 +255,17 @@ void __iomem * ioremap(phys_addr_t addr, unsigned long size)
         return __ioremap_caller(addr, size, flags, caller);
 }
 
-void __iomem * ioremap_flags(phys_addr_t addr, unsigned long size,
+void __iomem * ioremap_wc(phys_addr_t addr, unsigned long size)
+{
+        unsigned long flags = _PAGE_NO_CACHE;
+        void *caller = __builtin_return_address(0);
+
+        if (ppc_md.ioremap)
+                return ppc_md.ioremap(addr, size, flags, caller);
+        return __ioremap_caller(addr, size, flags, caller);
+}
+
+void __iomem * ioremap_prot(phys_addr_t addr, unsigned long size,
                              unsigned long flags)
 {
         void *caller = __builtin_return_address(0);
@@ -311,7 +321,8 @@ void iounmap(volatile void __iomem *token)
 }
 
 EXPORT_SYMBOL(ioremap);
-EXPORT_SYMBOL(ioremap_flags);
+EXPORT_SYMBOL(ioremap_wc);
+EXPORT_SYMBOL(ioremap_prot);
 EXPORT_SYMBOL(__ioremap);
 EXPORT_SYMBOL(__ioremap_at);
 EXPORT_SYMBOL(iounmap);
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 1d98ecc8eecd..e22276cb67a4 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -24,6 +24,7 @@
 #include <asm/firmware.h>
 #include <linux/compiler.h>
 #include <asm/udbg.h>
+#include <asm/code-patching.h>
 
 
 extern void slb_allocate_realmode(unsigned long ea);
@@ -166,7 +167,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
         int esid_1t_count;
 
         /* System is not 1T segment size capable. */
-        if (!cpu_has_feature(CPU_FTR_1T_SEGMENT))
+        if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
                 return (GET_ESID(addr1) == GET_ESID(addr2));
 
         esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -201,7 +202,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
          */
         hard_irq_disable();
         offset = get_paca()->slb_cache_ptr;
-        if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+        if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
             offset <= SLB_CACHE_ENTRIES) {
                 int i;
                 asm volatile("isync" : : : "memory");
@@ -249,9 +250,8 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 static inline void patch_slb_encoding(unsigned int *insn_addr,
                                       unsigned int immed)
 {
-        *insn_addr = (*insn_addr & 0xffff0000) | immed;
-        flush_icache_range((unsigned long)insn_addr, 4+
-                           (unsigned long)insn_addr);
+        int insn = (*insn_addr & 0xffff0000) | immed;
+        patch_instruction(insn_addr, insn);
 }
 
 void slb_set_size(u16 size)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 95ce35581696..ef653dc95b65 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -58,7 +58,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
         li      r11,0
 BEGIN_FTR_SECTION
         b       slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
         b       slb_finish_load_1T
 
 1:
@@ -87,7 +87,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
 6:
 BEGIN_FTR_SECTION
         b       slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
         b       slb_finish_load_1T
 
 0:      /* user address: proto-VSID = context << 15 | ESID. First check
@@ -138,11 +138,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
         ld      r9,PACACONTEXTID(r13)
 BEGIN_FTR_SECTION
         cmpldi  r10,0x1000
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         rldimi  r10,r9,USER_ESID_BITS,0
 BEGIN_FTR_SECTION
         bge     slb_finish_load_1T
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         b       slb_finish_load
 
 8:      /* invalid EA */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 446a01842a73..41e31642a86a 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -243,7 +243,7 @@ void __init stabs_alloc(void)
 {
         int cpu;
 
-        if (cpu_has_feature(CPU_FTR_SLB))
+        if (mmu_has_feature(MMU_FTR_SLB))
                 return;
 
         for_each_possible_cpu(cpu) {