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-rw-r--r--arch/powerpc/mm/hash_utils_64.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index c0d2a694fa30..3c7fe2c65b5a 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -685,6 +685,9 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
685 "non-cacheable mapping\n"); 685 "non-cacheable mapping\n");
686 psize = mmu_vmalloc_psize = MMU_PAGE_4K; 686 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
687 } 687 }
688#ifdef CONFIG_SPE_BASE
689 spu_flush_all_slbs(mm);
690#endif
688 } 691 }
689 if (user_region) { 692 if (user_region) {
690 if (psize != get_paca()->context.user_psize) { 693 if (psize != get_paca()->context.user_psize) {
@@ -759,6 +762,9 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
759 mmu_psize_defs[MMU_PAGE_4K].sllp; 762 mmu_psize_defs[MMU_PAGE_4K].sllp;
760 get_paca()->context = mm->context; 763 get_paca()->context = mm->context;
761 slb_flush_and_rebolt(); 764 slb_flush_and_rebolt();
765#ifdef CONFIG_SPE_BASE
766 spu_flush_all_slbs(mm);
767#endif
762 } 768 }
763 } 769 }
764 if (mm->context.user_psize == MMU_PAGE_64K) 770 if (mm->context.user_psize == MMU_PAGE_64K)